1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4 * 5 * Device Tree binding constants clock controllers of Samsung S3C2410 and later. 6 */ 7 8#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 9#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 10 11/* 12 * Let each exported clock get a unique index, which is used on DT-enabled 13 * platforms to lookup the clock from a clock specifier. These indices are 14 * therefore considered an ABI and so must not be changed. This implies 15 * that new clocks should be added either in free spaces between clock groups 16 * or at the end. 17 */ 18 19/* Core clocks. */ 20 21/* id 1 is reserved */ 22#define MPLL 2 23#define UPLL 3 24#define FCLK 4 25#define HCLK 5 26#define PCLK 6 27#define UCLK 7 28#define ARMCLK 8 29 30/* pclk-gates */ 31#define PCLK_UART0 16 32#define PCLK_UART1 17 33#define PCLK_UART2 18 34#define PCLK_I2C 19 35#define PCLK_SDI 20 36#define PCLK_SPI 21 37#define PCLK_ADC 22 38#define PCLK_AC97 23 39#define PCLK_I2S 24 40#define PCLK_PWM 25 41#define PCLK_RTC 26 42#define PCLK_GPIO 27 43 44 45/* hclk-gates */ 46#define HCLK_LCD 32 47#define HCLK_USBH 33 48#define HCLK_USBD 34 49#define HCLK_NAND 35 50#define HCLK_CAM 36 51 52 53#define CAMIF 40 54 55 56/* Total number of clocks. */ 57#define NR_CLKS (CAMIF + 1) 58 59#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 60