linux/include/kvm/arm_vgic.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2015, 2016 ARM Ltd.
   4 */
   5#ifndef __KVM_ARM_VGIC_H
   6#define __KVM_ARM_VGIC_H
   7
   8#include <linux/kernel.h>
   9#include <linux/kvm.h>
  10#include <linux/irqreturn.h>
  11#include <linux/spinlock.h>
  12#include <linux/static_key.h>
  13#include <linux/types.h>
  14#include <kvm/iodev.h>
  15#include <linux/list.h>
  16#include <linux/jump_label.h>
  17
  18#include <linux/irqchip/arm-gic-v4.h>
  19
  20#define VGIC_V3_MAX_CPUS        512
  21#define VGIC_V2_MAX_CPUS        8
  22#define VGIC_NR_IRQS_LEGACY     256
  23#define VGIC_NR_SGIS            16
  24#define VGIC_NR_PPIS            16
  25#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  26#define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  27#define VGIC_MAX_SPI            1019
  28#define VGIC_MAX_RESERVED       1023
  29#define VGIC_MIN_LPI            8192
  30#define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  31
  32#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
  33#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
  34                         (irq) <= VGIC_MAX_SPI)
  35
  36enum vgic_type {
  37        VGIC_V2,                /* Good ol' GICv2 */
  38        VGIC_V3,                /* New fancy GICv3 */
  39};
  40
  41/* same for all guests, as depending only on the _host's_ GIC model */
  42struct vgic_global {
  43        /* type of the host GIC */
  44        enum vgic_type          type;
  45
  46        /* Physical address of vgic virtual cpu interface */
  47        phys_addr_t             vcpu_base;
  48
  49        /* GICV mapping, kernel VA */
  50        void __iomem            *vcpu_base_va;
  51        /* GICV mapping, HYP VA */
  52        void __iomem            *vcpu_hyp_va;
  53
  54        /* virtual control interface mapping, kernel VA */
  55        void __iomem            *vctrl_base;
  56        /* virtual control interface mapping, HYP VA */
  57        void __iomem            *vctrl_hyp;
  58
  59        /* Number of implemented list registers */
  60        int                     nr_lr;
  61
  62        /* Maintenance IRQ number */
  63        unsigned int            maint_irq;
  64
  65        /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  66        int                     max_gic_vcpus;
  67
  68        /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  69        bool                    can_emulate_gicv2;
  70
  71        /* Hardware has GICv4? */
  72        bool                    has_gicv4;
  73
  74        /* GIC system register CPU interface */
  75        struct static_key_false gicv3_cpuif;
  76
  77        u32                     ich_vtr_el2;
  78};
  79
  80extern struct vgic_global kvm_vgic_global_state;
  81
  82#define VGIC_V2_MAX_LRS         (1 << 6)
  83#define VGIC_V3_MAX_LRS         16
  84#define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  85
  86enum vgic_irq_config {
  87        VGIC_CONFIG_EDGE = 0,
  88        VGIC_CONFIG_LEVEL
  89};
  90
  91struct vgic_irq {
  92        raw_spinlock_t irq_lock;        /* Protects the content of the struct */
  93        struct list_head lpi_list;      /* Used to link all LPIs together */
  94        struct list_head ap_list;
  95
  96        struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
  97                                         * SPIs and LPIs: The VCPU whose ap_list
  98                                         * this is queued on.
  99                                         */
 100
 101        struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 102                                         * be sent to, as a result of the
 103                                         * targets reg (v2) or the
 104                                         * affinity reg (v3).
 105                                         */
 106
 107        u32 intid;                      /* Guest visible INTID */
 108        bool line_level;                /* Level only */
 109        bool pending_latch;             /* The pending latch state used to calculate
 110                                         * the pending state for both level
 111                                         * and edge triggered IRQs. */
 112        bool active;                    /* not used for LPIs */
 113        bool enabled;
 114        bool hw;                        /* Tied to HW IRQ */
 115        struct kref refcount;           /* Used for LPIs */
 116        u32 hwintid;                    /* HW INTID number */
 117        unsigned int host_irq;          /* linux irq corresponding to hwintid */
 118        union {
 119                u8 targets;                     /* GICv2 target VCPUs mask */
 120                u32 mpidr;                      /* GICv3 target VCPU */
 121        };
 122        u8 source;                      /* GICv2 SGIs only */
 123        u8 active_source;               /* GICv2 SGIs only */
 124        u8 priority;
 125        u8 group;                       /* 0 == group 0, 1 == group 1 */
 126        enum vgic_irq_config config;    /* Level or edge */
 127
 128        /*
 129         * Callback function pointer to in-kernel devices that can tell us the
 130         * state of the input level of mapped level-triggered IRQ faster than
 131         * peaking into the physical GIC.
 132         *
 133         * Always called in non-preemptible section and the functions can use
 134         * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
 135         * IRQs.
 136         */
 137        bool (*get_input_level)(int vintid);
 138
 139        void *owner;                    /* Opaque pointer to reserve an interrupt
 140                                           for in-kernel devices. */
 141};
 142
 143struct vgic_register_region;
 144struct vgic_its;
 145
 146enum iodev_type {
 147        IODEV_CPUIF,
 148        IODEV_DIST,
 149        IODEV_REDIST,
 150        IODEV_ITS
 151};
 152
 153struct vgic_io_device {
 154        gpa_t base_addr;
 155        union {
 156                struct kvm_vcpu *redist_vcpu;
 157                struct vgic_its *its;
 158        };
 159        const struct vgic_register_region *regions;
 160        enum iodev_type iodev_type;
 161        int nr_regions;
 162        struct kvm_io_device dev;
 163};
 164
 165struct vgic_its {
 166        /* The base address of the ITS control register frame */
 167        gpa_t                   vgic_its_base;
 168
 169        bool                    enabled;
 170        struct vgic_io_device   iodev;
 171        struct kvm_device       *dev;
 172
 173        /* These registers correspond to GITS_BASER{0,1} */
 174        u64                     baser_device_table;
 175        u64                     baser_coll_table;
 176
 177        /* Protects the command queue */
 178        struct mutex            cmd_lock;
 179        u64                     cbaser;
 180        u32                     creadr;
 181        u32                     cwriter;
 182
 183        /* migration ABI revision in use */
 184        u32                     abi_rev;
 185
 186        /* Protects the device and collection lists */
 187        struct mutex            its_lock;
 188        struct list_head        device_list;
 189        struct list_head        collection_list;
 190};
 191
 192struct vgic_state_iter;
 193
 194struct vgic_redist_region {
 195        u32 index;
 196        gpa_t base;
 197        u32 count; /* number of redistributors or 0 if single region */
 198        u32 free_index; /* index of the next free redistributor */
 199        struct list_head list;
 200};
 201
 202struct vgic_dist {
 203        bool                    in_kernel;
 204        bool                    ready;
 205        bool                    initialized;
 206
 207        /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 208        u32                     vgic_model;
 209
 210        /* Implementation revision as reported in the GICD_IIDR */
 211        u32                     implementation_rev;
 212
 213        /* Userspace can write to GICv2 IGROUPR */
 214        bool                    v2_groups_user_writable;
 215
 216        /* Do injected MSIs require an additional device ID? */
 217        bool                    msis_require_devid;
 218
 219        int                     nr_spis;
 220
 221        /* base addresses in guest physical address space: */
 222        gpa_t                   vgic_dist_base;         /* distributor */
 223        union {
 224                /* either a GICv2 CPU interface */
 225                gpa_t                   vgic_cpu_base;
 226                /* or a number of GICv3 redistributor regions */
 227                struct list_head rd_regions;
 228        };
 229
 230        /* distributor enabled */
 231        bool                    enabled;
 232
 233        struct vgic_irq         *spis;
 234
 235        struct vgic_io_device   dist_iodev;
 236
 237        bool                    has_its;
 238
 239        /*
 240         * Contains the attributes and gpa of the LPI configuration table.
 241         * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 242         * one address across all redistributors.
 243         * GICv3 spec: 6.1.2 "LPI Configuration tables"
 244         */
 245        u64                     propbaser;
 246
 247        /* Protects the lpi_list and the count value below. */
 248        raw_spinlock_t          lpi_list_lock;
 249        struct list_head        lpi_list_head;
 250        int                     lpi_list_count;
 251
 252        /* LPI translation cache */
 253        struct list_head        lpi_translation_cache;
 254
 255        /* used by vgic-debug */
 256        struct vgic_state_iter *iter;
 257
 258        /*
 259         * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
 260         * array, the property table pointer as well as allocation
 261         * data. This essentially ties the Linux IRQ core and ITS
 262         * together, and avoids leaking KVM's data structures anywhere
 263         * else.
 264         */
 265        struct its_vm           its_vm;
 266};
 267
 268struct vgic_v2_cpu_if {
 269        u32             vgic_hcr;
 270        u32             vgic_vmcr;
 271        u32             vgic_apr;
 272        u32             vgic_lr[VGIC_V2_MAX_LRS];
 273};
 274
 275struct vgic_v3_cpu_if {
 276        u32             vgic_hcr;
 277        u32             vgic_vmcr;
 278        u32             vgic_sre;       /* Restored only, change ignored */
 279        u32             vgic_ap0r[4];
 280        u32             vgic_ap1r[4];
 281        u64             vgic_lr[VGIC_V3_MAX_LRS];
 282
 283        /*
 284         * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
 285         * pending table pointer, the its_vm pointer and a few other
 286         * HW specific things. As for the its_vm structure, this is
 287         * linking the Linux IRQ subsystem and the ITS together.
 288         */
 289        struct its_vpe  its_vpe;
 290};
 291
 292struct vgic_cpu {
 293        /* CPU vif control registers for world switch */
 294        union {
 295                struct vgic_v2_cpu_if   vgic_v2;
 296                struct vgic_v3_cpu_if   vgic_v3;
 297        };
 298
 299        unsigned int used_lrs;
 300        struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 301
 302        raw_spinlock_t ap_list_lock;    /* Protects the ap_list */
 303
 304        /*
 305         * List of IRQs that this VCPU should consider because they are either
 306         * Active or Pending (hence the name; AP list), or because they recently
 307         * were one of the two and need to be migrated off this list to another
 308         * VCPU.
 309         */
 310        struct list_head ap_list_head;
 311
 312        /*
 313         * Members below are used with GICv3 emulation only and represent
 314         * parts of the redistributor.
 315         */
 316        struct vgic_io_device   rd_iodev;
 317        struct vgic_redist_region *rdreg;
 318
 319        /* Contains the attributes and gpa of the LPI pending tables. */
 320        u64 pendbaser;
 321
 322        bool lpis_enabled;
 323
 324        /* Cache guest priority bits */
 325        u32 num_pri_bits;
 326
 327        /* Cache guest interrupt ID bits */
 328        u32 num_id_bits;
 329};
 330
 331extern struct static_key_false vgic_v2_cpuif_trap;
 332extern struct static_key_false vgic_v3_cpuif_trap;
 333
 334int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 335void kvm_vgic_early_init(struct kvm *kvm);
 336int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 337int kvm_vgic_create(struct kvm *kvm, u32 type);
 338void kvm_vgic_destroy(struct kvm *kvm);
 339void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 340int kvm_vgic_map_resources(struct kvm *kvm);
 341int kvm_vgic_hyp_init(void);
 342void kvm_vgic_init_cpu_hardware(void);
 343
 344int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 345                        bool level, void *owner);
 346int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
 347                          u32 vintid, bool (*get_input_level)(int vindid));
 348int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
 349bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
 350
 351int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 352
 353void kvm_vgic_load(struct kvm_vcpu *vcpu);
 354void kvm_vgic_put(struct kvm_vcpu *vcpu);
 355void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);
 356
 357#define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 358#define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 359#define vgic_ready(k)           ((k)->arch.vgic.ready)
 360#define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 361                        ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 362
 363bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 364void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 365void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 366void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
 367
 368void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);
 369
 370/**
 371 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 372 *
 373 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 374 * can use.
 375 */
 376static inline int kvm_vgic_get_max_vcpus(void)
 377{
 378        return kvm_vgic_global_state.max_gic_vcpus;
 379}
 380
 381int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 382
 383/**
 384 * kvm_vgic_setup_default_irq_routing:
 385 * Setup a default flat gsi routing table mapping all SPIs
 386 */
 387int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 388
 389int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
 390
 391struct kvm_kernel_irq_routing_entry;
 392
 393int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
 394                               struct kvm_kernel_irq_routing_entry *irq_entry);
 395
 396int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
 397                                 struct kvm_kernel_irq_routing_entry *irq_entry);
 398
 399void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
 400void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
 401
 402#endif /* __KVM_ARM_VGIC_H */
 403