1/* 2 * Generic EDAC defs 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12#ifndef _LINUX_EDAC_H_ 13#define _LINUX_EDAC_H_ 14 15#include <linux/atomic.h> 16#include <linux/device.h> 17#include <linux/completion.h> 18#include <linux/workqueue.h> 19#include <linux/debugfs.h> 20#include <linux/numa.h> 21 22#define EDAC_DEVICE_NAME_LEN 31 23 24struct device; 25 26#define EDAC_OPSTATE_INVAL -1 27#define EDAC_OPSTATE_POLL 0 28#define EDAC_OPSTATE_NMI 1 29#define EDAC_OPSTATE_INT 2 30 31extern int edac_op_state; 32 33struct bus_type *edac_get_sysfs_subsys(void); 34 35static inline void opstate_init(void) 36{ 37 switch (edac_op_state) { 38 case EDAC_OPSTATE_POLL: 39 case EDAC_OPSTATE_NMI: 40 break; 41 default: 42 edac_op_state = EDAC_OPSTATE_POLL; 43 } 44 return; 45} 46 47/* Max length of a DIMM label*/ 48#define EDAC_MC_LABEL_LEN 31 49 50/* Maximum size of the location string */ 51#define LOCATION_SIZE 256 52 53/* Defines the maximum number of labels that can be reported */ 54#define EDAC_MAX_LABELS 8 55 56/* String used to join two or more labels */ 57#define OTHER_LABEL " or " 58 59/** 60 * enum dev_type - describe the type of memory DRAM chips used at the stick 61 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it 62 * @DEV_X1: 1 bit for data 63 * @DEV_X2: 2 bits for data 64 * @DEV_X4: 4 bits for data 65 * @DEV_X8: 8 bits for data 66 * @DEV_X16: 16 bits for data 67 * @DEV_X32: 32 bits for data 68 * @DEV_X64: 64 bits for data 69 * 70 * Typical values are x4 and x8. 71 */ 72enum dev_type { 73 DEV_UNKNOWN = 0, 74 DEV_X1, 75 DEV_X2, 76 DEV_X4, 77 DEV_X8, 78 DEV_X16, 79 DEV_X32, /* Do these parts exist? */ 80 DEV_X64 /* Do these parts exist? */ 81}; 82 83#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 84#define DEV_FLAG_X1 BIT(DEV_X1) 85#define DEV_FLAG_X2 BIT(DEV_X2) 86#define DEV_FLAG_X4 BIT(DEV_X4) 87#define DEV_FLAG_X8 BIT(DEV_X8) 88#define DEV_FLAG_X16 BIT(DEV_X16) 89#define DEV_FLAG_X32 BIT(DEV_X32) 90#define DEV_FLAG_X64 BIT(DEV_X64) 91 92/** 93 * enum hw_event_mc_err_type - type of the detected error 94 * 95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC 96 * corrected error was detected 97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that 98 * can't be corrected by ECC, but it is not 99 * fatal (maybe it is on an unused memory area, 100 * or the memory controller could recover from 101 * it for example, by re-trying the operation). 102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable 103 * error whose handling is not urgent. This could 104 * be due to hardware data poisoning where the 105 * system can continue operation until the poisoned 106 * data is consumed. Preemptive measures may also 107 * be taken, e.g. offlining pages, etc. 108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not 109 * be recovered. 110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth 111 * type of error: informational logs. 112 */ 113enum hw_event_mc_err_type { 114 HW_EVENT_ERR_CORRECTED, 115 HW_EVENT_ERR_UNCORRECTED, 116 HW_EVENT_ERR_DEFERRED, 117 HW_EVENT_ERR_FATAL, 118 HW_EVENT_ERR_INFO, 119}; 120 121static inline char *mc_event_error_type(const unsigned int err_type) 122{ 123 switch (err_type) { 124 case HW_EVENT_ERR_CORRECTED: 125 return "Corrected"; 126 case HW_EVENT_ERR_UNCORRECTED: 127 return "Uncorrected"; 128 case HW_EVENT_ERR_DEFERRED: 129 return "Deferred"; 130 case HW_EVENT_ERR_FATAL: 131 return "Fatal"; 132 default: 133 case HW_EVENT_ERR_INFO: 134 return "Info"; 135 } 136} 137 138/** 139 * enum mem_type - memory types. For a more detailed reference, please see 140 * http://en.wikipedia.org/wiki/DRAM 141 * 142 * @MEM_EMPTY: Empty csrow 143 * @MEM_RESERVED: Reserved csrow type 144 * @MEM_UNKNOWN: Unknown csrow type 145 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. 146 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. 147 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. 148 * @MEM_SDR: SDR - Single data rate SDRAM 149 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory 150 * They use 3 pins for chip select: Pins 0 and 2 are 151 * for rank 0; pins 1 and 3 are for rank 1, if the memory 152 * is dual-rank. 153 * @MEM_RDR: Registered SDR SDRAM 154 * @MEM_DDR: Double data rate SDRAM 155 * http://en.wikipedia.org/wiki/DDR_SDRAM 156 * @MEM_RDDR: Registered Double data rate SDRAM 157 * This is a variant of the DDR memories. 158 * A registered memory has a buffer inside it, hiding 159 * part of the memory details to the memory controller. 160 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. 161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. 162 * Those memories are labeled as "PC2-" instead of "PC" to 163 * differentiate from DDR. 164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 165 * and JESD206. 166 * Those memories are accessed per DIMM slot, and not by 167 * a chip select signal. 168 * @MEM_RDDR2: Registered DDR2 RAM 169 * This is a variant of the DDR2 memories. 170 * @MEM_XDR: Rambus XDR 171 * It is an evolution of the original RAMBUS memories, 172 * created to compete with DDR2. Weren't used on any 173 * x86 arch, but cell_edac PPC memory controller uses it. 174 * @MEM_DDR3: DDR3 RAM 175 * @MEM_RDDR3: Registered DDR3 RAM 176 * This is a variant of the DDR3 memories. 177 * @MEM_LRDDR3: Load-Reduced DDR3 memory. 178 * @MEM_LPDDR3: Low-Power DDR3 memory. 179 * @MEM_DDR4: Unbuffered DDR4 RAM 180 * @MEM_RDDR4: Registered DDR4 RAM 181 * This is a variant of the DDR4 memories. 182 * @MEM_LRDDR4: Load-Reduced DDR4 memory. 183 * @MEM_LPDDR4: Low-Power DDR4 memory. 184 * @MEM_DDR5: Unbuffered DDR5 RAM 185 * @MEM_NVDIMM: Non-volatile RAM 186 * @MEM_WIO2: Wide I/O 2. 187 * @MEM_HBM2: High bandwidth Memory Gen 2. 188 */ 189enum mem_type { 190 MEM_EMPTY = 0, 191 MEM_RESERVED, 192 MEM_UNKNOWN, 193 MEM_FPM, 194 MEM_EDO, 195 MEM_BEDO, 196 MEM_SDR, 197 MEM_RDR, 198 MEM_DDR, 199 MEM_RDDR, 200 MEM_RMBS, 201 MEM_DDR2, 202 MEM_FB_DDR2, 203 MEM_RDDR2, 204 MEM_XDR, 205 MEM_DDR3, 206 MEM_RDDR3, 207 MEM_LRDDR3, 208 MEM_LPDDR3, 209 MEM_DDR4, 210 MEM_RDDR4, 211 MEM_LRDDR4, 212 MEM_LPDDR4, 213 MEM_DDR5, 214 MEM_NVDIMM, 215 MEM_WIO2, 216 MEM_HBM2, 217}; 218 219#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 220#define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 221#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 222#define MEM_FLAG_FPM BIT(MEM_FPM) 223#define MEM_FLAG_EDO BIT(MEM_EDO) 224#define MEM_FLAG_BEDO BIT(MEM_BEDO) 225#define MEM_FLAG_SDR BIT(MEM_SDR) 226#define MEM_FLAG_RDR BIT(MEM_RDR) 227#define MEM_FLAG_DDR BIT(MEM_DDR) 228#define MEM_FLAG_RDDR BIT(MEM_RDDR) 229#define MEM_FLAG_RMBS BIT(MEM_RMBS) 230#define MEM_FLAG_DDR2 BIT(MEM_DDR2) 231#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 232#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 233#define MEM_FLAG_XDR BIT(MEM_XDR) 234#define MEM_FLAG_DDR3 BIT(MEM_DDR3) 235#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) 236#define MEM_FLAG_LPDDR3 BIT(MEM_LPDDR3) 237#define MEM_FLAG_DDR4 BIT(MEM_DDR4) 238#define MEM_FLAG_RDDR4 BIT(MEM_RDDR4) 239#define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) 240#define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4) 241#define MEM_FLAG_DDR5 BIT(MEM_DDR5) 242#define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) 243#define MEM_FLAG_WIO2 BIT(MEM_WIO2) 244#define MEM_FLAG_HBM2 BIT(MEM_HBM2) 245 246/** 247 * enum edac_type - Error Detection and Correction capabilities and mode 248 * @EDAC_UNKNOWN: Unknown if ECC is available 249 * @EDAC_NONE: Doesn't support ECC 250 * @EDAC_RESERVED: Reserved ECC type 251 * @EDAC_PARITY: Detects parity errors 252 * @EDAC_EC: Error Checking - no correction 253 * @EDAC_SECDED: Single bit error correction, Double detection 254 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? 255 * @EDAC_S4ECD4ED: Chipkill x4 devices 256 * @EDAC_S8ECD8ED: Chipkill x8 devices 257 * @EDAC_S16ECD16ED: Chipkill x16 devices 258 */ 259enum edac_type { 260 EDAC_UNKNOWN = 0, 261 EDAC_NONE, 262 EDAC_RESERVED, 263 EDAC_PARITY, 264 EDAC_EC, 265 EDAC_SECDED, 266 EDAC_S2ECD2ED, 267 EDAC_S4ECD4ED, 268 EDAC_S8ECD8ED, 269 EDAC_S16ECD16ED, 270}; 271 272#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 273#define EDAC_FLAG_NONE BIT(EDAC_NONE) 274#define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 275#define EDAC_FLAG_EC BIT(EDAC_EC) 276#define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 277#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 278#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 279#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 280#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 281 282/** 283 * enum scrub_type - scrubbing capabilities 284 * @SCRUB_UNKNOWN: Unknown if scrubber is available 285 * @SCRUB_NONE: No scrubber 286 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing 287 * @SCRUB_SW_SRC: Software scrub only errors 288 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error 289 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable 290 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing 291 * @SCRUB_HW_SRC: Hardware scrub only errors 292 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error 293 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable 294 */ 295enum scrub_type { 296 SCRUB_UNKNOWN = 0, 297 SCRUB_NONE, 298 SCRUB_SW_PROG, 299 SCRUB_SW_SRC, 300 SCRUB_SW_PROG_SRC, 301 SCRUB_SW_TUNABLE, 302 SCRUB_HW_PROG, 303 SCRUB_HW_SRC, 304 SCRUB_HW_PROG_SRC, 305 SCRUB_HW_TUNABLE 306}; 307 308#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 309#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) 310#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) 311#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 312#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 313#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) 314#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) 315#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 316 317/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 318 319/* EDAC internal operation states */ 320#define OP_ALLOC 0x100 321#define OP_RUNNING_POLL 0x201 322#define OP_RUNNING_INTERRUPT 0x202 323#define OP_RUNNING_POLL_INTR 0x203 324#define OP_OFFLINE 0x300 325 326/** 327 * enum edac_mc_layer_type - memory controller hierarchy layer 328 * 329 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" 330 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" 331 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" 332 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" 333 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped 334 * as a single memory area. This is used when 335 * retrieving errors from a firmware driven driver. 336 * 337 * This enum is used by the drivers to tell edac_mc_sysfs what name should 338 * be used when describing a memory stick location. 339 */ 340enum edac_mc_layer_type { 341 EDAC_MC_LAYER_BRANCH, 342 EDAC_MC_LAYER_CHANNEL, 343 EDAC_MC_LAYER_SLOT, 344 EDAC_MC_LAYER_CHIP_SELECT, 345 EDAC_MC_LAYER_ALL_MEM, 346}; 347 348/** 349 * struct edac_mc_layer - describes the memory controller hierarchy 350 * @type: layer type 351 * @size: number of components per layer. For example, 352 * if the channel layer has two channels, size = 2 353 * @is_virt_csrow: This layer is part of the "csrow" when old API 354 * compatibility mode is enabled. Otherwise, it is 355 * a channel 356 */ 357struct edac_mc_layer { 358 enum edac_mc_layer_type type; 359 unsigned size; 360 bool is_virt_csrow; 361}; 362 363/* 364 * Maximum number of layers used by the memory controller to uniquely 365 * identify a single memory stick. 366 * NOTE: Changing this constant requires not only to change the constant 367 * below, but also to change the existing code at the core, as there are 368 * some code there that are optimized for 3 layers. 369 */ 370#define EDAC_MAX_LAYERS 3 371 372struct dimm_info { 373 struct device dev; 374 375 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 376 377 /* Memory location data */ 378 unsigned int location[EDAC_MAX_LAYERS]; 379 380 struct mem_ctl_info *mci; /* the parent */ 381 unsigned int idx; /* index within the parent dimm array */ 382 383 u32 grain; /* granularity of reported error in bytes */ 384 enum dev_type dtype; /* memory device type */ 385 enum mem_type mtype; /* memory dimm type */ 386 enum edac_type edac_mode; /* EDAC mode for this dimm */ 387 388 u32 nr_pages; /* number of pages on this dimm */ 389 390 unsigned int csrow, cschannel; /* Points to the old API data */ 391 392 u16 smbios_handle; /* Handle for SMBIOS type 17 */ 393 394 u32 ce_count; 395 u32 ue_count; 396}; 397 398/** 399 * struct rank_info - contains the information for one DIMM rank 400 * 401 * @chan_idx: channel number where the rank is (typically, 0 or 1) 402 * @ce_count: number of correctable errors for this rank 403 * @csrow: A pointer to the chip select row structure (the parent 404 * structure). The location of the rank is given by 405 * the (csrow->csrow_idx, chan_idx) vector. 406 * @dimm: A pointer to the DIMM structure, where the DIMM label 407 * information is stored. 408 * 409 * FIXME: Currently, the EDAC core model will assume one DIMM per rank. 410 * This is a bad assumption, but it makes this patch easier. Later 411 * patches in this series will fix this issue. 412 */ 413struct rank_info { 414 int chan_idx; 415 struct csrow_info *csrow; 416 struct dimm_info *dimm; 417 418 u32 ce_count; /* Correctable Errors for this csrow */ 419}; 420 421struct csrow_info { 422 struct device dev; 423 424 /* Used only by edac_mc_find_csrow_by_page() */ 425 unsigned long first_page; /* first page number in csrow */ 426 unsigned long last_page; /* last page number in csrow */ 427 unsigned long page_mask; /* used for interleaving - 428 * 0UL for non intlv */ 429 430 int csrow_idx; /* the chip-select row */ 431 432 u32 ue_count; /* Uncorrectable Errors for this csrow */ 433 u32 ce_count; /* Correctable Errors for this csrow */ 434 435 struct mem_ctl_info *mci; /* the parent */ 436 437 /* channel information for this csrow */ 438 u32 nr_channels; 439 struct rank_info **channels; 440}; 441 442/* 443 * struct errcount_attribute - used to store the several error counts 444 */ 445struct errcount_attribute_data { 446 int n_layers; 447 int pos[EDAC_MAX_LAYERS]; 448 int layer0, layer1, layer2; 449}; 450 451/** 452 * struct edac_raw_error_desc - Raw error report structure 453 * @grain: minimum granularity for an error report, in bytes 454 * @error_count: number of errors of the same type 455 * @type: severity of the error (CE/UE/Fatal) 456 * @top_layer: top layer of the error (layer[0]) 457 * @mid_layer: middle layer of the error (layer[1]) 458 * @low_layer: low layer of the error (layer[2]) 459 * @page_frame_number: page where the error happened 460 * @offset_in_page: page offset 461 * @syndrome: syndrome of the error (or 0 if unknown or if 462 * the syndrome is not applicable) 463 * @msg: error message 464 * @location: location of the error 465 * @label: label of the affected DIMM(s) 466 * @other_detail: other driver-specific detail about the error 467 */ 468struct edac_raw_error_desc { 469 char location[LOCATION_SIZE]; 470 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; 471 long grain; 472 473 u16 error_count; 474 enum hw_event_mc_err_type type; 475 int top_layer; 476 int mid_layer; 477 int low_layer; 478 unsigned long page_frame_number; 479 unsigned long offset_in_page; 480 unsigned long syndrome; 481 const char *msg; 482 const char *other_detail; 483}; 484 485/* MEMORY controller information structure 486 */ 487struct mem_ctl_info { 488 struct device dev; 489 struct bus_type *bus; 490 491 struct list_head link; /* for global list of mem_ctl_info structs */ 492 493 struct module *owner; /* Module owner of this control struct */ 494 495 unsigned long mtype_cap; /* memory types supported by mc */ 496 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 497 unsigned long edac_cap; /* configuration capabilities - this is 498 * closely related to edac_ctl_cap. The 499 * difference is that the controller may be 500 * capable of s4ecd4ed which would be listed 501 * in edac_ctl_cap, but if channels aren't 502 * capable of s4ecd4ed then the edac_cap would 503 * not have that capability. 504 */ 505 unsigned long scrub_cap; /* chipset scrub capabilities */ 506 enum scrub_type scrub_mode; /* current scrub mode */ 507 508 /* Translates sdram memory scrub rate given in bytes/sec to the 509 internal representation and configures whatever else needs 510 to be configured. 511 */ 512 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); 513 514 /* Get the current sdram memory scrub rate from the internal 515 representation and converts it to the closest matching 516 bandwidth in bytes/sec. 517 */ 518 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); 519 520 521 /* pointer to edac checking routine */ 522 void (*edac_check) (struct mem_ctl_info * mci); 523 524 /* 525 * Remaps memory pages: controller pages to physical pages. 526 * For most MC's, this will be NULL. 527 */ 528 /* FIXME - why not send the phys page to begin with? */ 529 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 530 unsigned long page); 531 int mc_idx; 532 struct csrow_info **csrows; 533 unsigned int nr_csrows, num_cschannel; 534 535 /* 536 * Memory Controller hierarchy 537 * 538 * There are basically two types of memory controller: the ones that 539 * sees memory sticks ("dimms"), and the ones that sees memory ranks. 540 * All old memory controllers enumerate memories per rank, but most 541 * of the recent drivers enumerate memories per DIMM, instead. 542 * When the memory controller is per rank, csbased is true. 543 */ 544 unsigned int n_layers; 545 struct edac_mc_layer *layers; 546 bool csbased; 547 548 /* 549 * DIMM info. Will eventually remove the entire csrows_info some day 550 */ 551 unsigned int tot_dimms; 552 struct dimm_info **dimms; 553 554 /* 555 * FIXME - what about controllers on other busses? - IDs must be 556 * unique. dev pointer should be sufficiently unique, but 557 * BUS:SLOT.FUNC numbers may not be unique. 558 */ 559 struct device *pdev; 560 const char *mod_name; 561 const char *ctl_name; 562 const char *dev_name; 563 void *pvt_info; 564 unsigned long start_time; /* mci load start time (in jiffies) */ 565 566 /* 567 * drivers shouldn't access those fields directly, as the core 568 * already handles that. 569 */ 570 u32 ce_noinfo_count, ue_noinfo_count; 571 u32 ue_mc, ce_mc; 572 573 struct completion complete; 574 575 /* Additional top controller level attributes, but specified 576 * by the low level driver. 577 * 578 * Set by the low level driver to provide attributes at the 579 * controller level. 580 * An array of structures, NULL terminated 581 * 582 * If attributes are desired, then set to array of attributes 583 * If no attributes are desired, leave NULL 584 */ 585 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; 586 587 /* work struct for this MC */ 588 struct delayed_work work; 589 590 /* 591 * Used to report an error - by being at the global struct 592 * makes the memory allocated by the EDAC core 593 */ 594 struct edac_raw_error_desc error_desc; 595 596 /* the internal state of this controller instance */ 597 int op_state; 598 599 struct dentry *debugfs; 600 u8 fake_inject_layer[EDAC_MAX_LAYERS]; 601 bool fake_inject_ue; 602 u16 fake_inject_count; 603}; 604 605#define mci_for_each_dimm(mci, dimm) \ 606 for ((dimm) = (mci)->dimms[0]; \ 607 (dimm); \ 608 (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \ 609 ? (mci)->dimms[(dimm)->idx + 1] \ 610 : NULL) 611 612/** 613 * edac_get_dimm - Get DIMM info from a memory controller given by 614 * [layer0,layer1,layer2] position 615 * 616 * @mci: MC descriptor struct mem_ctl_info 617 * @layer0: layer0 position 618 * @layer1: layer1 position. Unused if n_layers < 2 619 * @layer2: layer2 position. Unused if n_layers < 3 620 * 621 * For 1 layer, this function returns "dimms[layer0]"; 622 * 623 * For 2 layers, this function is similar to allocating a two-dimensional 624 * array and returning "dimms[layer0][layer1]"; 625 * 626 * For 3 layers, this function is similar to allocating a tri-dimensional 627 * array and returning "dimms[layer0][layer1][layer2]"; 628 */ 629static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci, 630 int layer0, int layer1, int layer2) 631{ 632 int index; 633 634 if (layer0 < 0 635 || (mci->n_layers > 1 && layer1 < 0) 636 || (mci->n_layers > 2 && layer2 < 0)) 637 return NULL; 638 639 index = layer0; 640 641 if (mci->n_layers > 1) 642 index = index * mci->layers[1].size + layer1; 643 644 if (mci->n_layers > 2) 645 index = index * mci->layers[2].size + layer2; 646 647 if (index < 0 || index >= mci->tot_dimms) 648 return NULL; 649 650 if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) 651 return NULL; 652 653 return mci->dimms[index]; 654} 655#endif /* _LINUX_EDAC_H_ */ 656