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14#ifndef _SC_MISC_API_H
15#define _SC_MISC_API_H
16
17#include <linux/firmware/imx/sci.h>
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21
22enum imx_misc_func {
23 IMX_SC_MISC_FUNC_UNKNOWN = 0,
24 IMX_SC_MISC_FUNC_SET_CONTROL = 1,
25 IMX_SC_MISC_FUNC_GET_CONTROL = 2,
26 IMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP = 4,
27 IMX_SC_MISC_FUNC_SET_DMA_GROUP = 5,
28 IMX_SC_MISC_FUNC_SECO_IMAGE_LOAD = 8,
29 IMX_SC_MISC_FUNC_SECO_AUTHENTICATE = 9,
30 IMX_SC_MISC_FUNC_DEBUG_OUT = 10,
31 IMX_SC_MISC_FUNC_WAVEFORM_CAPTURE = 6,
32 IMX_SC_MISC_FUNC_BUILD_INFO = 15,
33 IMX_SC_MISC_FUNC_UNIQUE_ID = 19,
34 IMX_SC_MISC_FUNC_SET_ARI = 3,
35 IMX_SC_MISC_FUNC_BOOT_STATUS = 7,
36 IMX_SC_MISC_FUNC_BOOT_DONE = 14,
37 IMX_SC_MISC_FUNC_OTP_FUSE_READ = 11,
38 IMX_SC_MISC_FUNC_OTP_FUSE_WRITE = 17,
39 IMX_SC_MISC_FUNC_SET_TEMP = 12,
40 IMX_SC_MISC_FUNC_GET_TEMP = 13,
41 IMX_SC_MISC_FUNC_GET_BOOT_DEV = 16,
42 IMX_SC_MISC_FUNC_GET_BUTTON_STATUS = 18,
43};
44
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46
47
48
49#ifdef CONFIG_IMX_SCU
50int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
51 u8 ctrl, u32 val);
52
53int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
54 u8 ctrl, u32 *val);
55
56int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
57 bool enable, u64 phys_addr);
58#else
59static inline int imx_sc_misc_set_control(struct imx_sc_ipc *ipc,
60 u32 resource, u8 ctrl, u32 val)
61{
62 return -ENOTSUPP;
63}
64
65static inline int imx_sc_misc_get_control(struct imx_sc_ipc *ipc,
66 u32 resource, u8 ctrl, u32 *val)
67{
68 return -ENOTSUPP;
69}
70
71static inline int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
72 bool enable, u64 phys_addr)
73{
74 return -ENOTSUPP;
75}
76#endif
77#endif
78