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6#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
7#define __LINUX_IRQCHIP_ARM_GIC_V3_H
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9
10
11
12
13#define GICD_CTLR 0x0000
14#define GICD_TYPER 0x0004
15#define GICD_IIDR 0x0008
16#define GICD_TYPER2 0x000C
17#define GICD_STATUSR 0x0010
18#define GICD_SETSPI_NSR 0x0040
19#define GICD_CLRSPI_NSR 0x0048
20#define GICD_SETSPI_SR 0x0050
21#define GICD_CLRSPI_SR 0x0058
22#define GICD_IGROUPR 0x0080
23#define GICD_ISENABLER 0x0100
24#define GICD_ICENABLER 0x0180
25#define GICD_ISPENDR 0x0200
26#define GICD_ICPENDR 0x0280
27#define GICD_ISACTIVER 0x0300
28#define GICD_ICACTIVER 0x0380
29#define GICD_IPRIORITYR 0x0400
30#define GICD_ICFGR 0x0C00
31#define GICD_IGRPMODR 0x0D00
32#define GICD_NSACR 0x0E00
33#define GICD_IGROUPRnE 0x1000
34#define GICD_ISENABLERnE 0x1200
35#define GICD_ICENABLERnE 0x1400
36#define GICD_ISPENDRnE 0x1600
37#define GICD_ICPENDRnE 0x1800
38#define GICD_ISACTIVERnE 0x1A00
39#define GICD_ICACTIVERnE 0x1C00
40#define GICD_IPRIORITYRnE 0x2000
41#define GICD_ICFGRnE 0x3000
42#define GICD_IROUTER 0x6000
43#define GICD_IROUTERnE 0x8000
44#define GICD_IDREGS 0xFFD0
45#define GICD_PIDR2 0xFFE8
46
47#define ESPI_BASE_INTID 4096
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49
50
51
52
53#define GICD_ITARGETSR 0x0800
54#define GICD_SGIR 0x0F00
55#define GICD_CPENDSGIR 0x0F10
56#define GICD_SPENDSGIR 0x0F20
57
58#define GICD_CTLR_RWP (1U << 31)
59#define GICD_CTLR_nASSGIreq (1U << 8)
60#define GICD_CTLR_DS (1U << 6)
61#define GICD_CTLR_ARE_NS (1U << 4)
62#define GICD_CTLR_ENABLE_G1A (1U << 1)
63#define GICD_CTLR_ENABLE_G1 (1U << 0)
64
65#define GICD_IIDR_IMPLEMENTER_SHIFT 0
66#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
67#define GICD_IIDR_REVISION_SHIFT 12
68#define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
69#define GICD_IIDR_VARIANT_SHIFT 16
70#define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
71#define GICD_IIDR_PRODUCT_ID_SHIFT 24
72#define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
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74
75
76
77
78
79#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
80#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
81
82#define GICD_TYPER_RSS (1U << 26)
83#define GICD_TYPER_LPIS (1U << 17)
84#define GICD_TYPER_MBIS (1U << 16)
85#define GICD_TYPER_ESPI (1U << 8)
86
87#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
88#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
89#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
90#define GICD_TYPER_ESPIS(typer) \
91 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
92
93#define GICD_TYPER2_nASSGIcap (1U << 8)
94#define GICD_TYPER2_VIL (1U << 7)
95#define GICD_TYPER2_VID GENMASK(4, 0)
96
97#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
98#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
99
100#define GIC_PIDR2_ARCH_MASK 0xf0
101#define GIC_PIDR2_ARCH_GICv3 0x30
102#define GIC_PIDR2_ARCH_GICv4 0x40
103
104#define GIC_V3_DIST_SIZE 0x10000
105
106#define GIC_PAGE_SIZE_4K 0ULL
107#define GIC_PAGE_SIZE_16K 1ULL
108#define GIC_PAGE_SIZE_64K 2ULL
109#define GIC_PAGE_SIZE_MASK 3ULL
110
111
112
113
114#define GICR_CTLR GICD_CTLR
115#define GICR_IIDR 0x0004
116#define GICR_TYPER 0x0008
117#define GICR_STATUSR GICD_STATUSR
118#define GICR_WAKER 0x0014
119#define GICR_SETLPIR 0x0040
120#define GICR_CLRLPIR 0x0048
121#define GICR_PROPBASER 0x0070
122#define GICR_PENDBASER 0x0078
123#define GICR_INVLPIR 0x00A0
124#define GICR_INVALLR 0x00B0
125#define GICR_SYNCR 0x00C0
126#define GICR_IDREGS GICD_IDREGS
127#define GICR_PIDR2 GICD_PIDR2
128
129#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
130#define GICR_CTLR_RWP (1UL << 3)
131
132#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
133
134#define EPPI_BASE_INTID 1056
135
136#define GICR_TYPER_NR_PPIS(r) \
137 ({ \
138 unsigned int __ppinum = ((r) >> 27) & 0x1f; \
139 unsigned int __nr_ppis = 16; \
140 if (__ppinum == 1 || __ppinum == 2) \
141 __nr_ppis += __ppinum * 32; \
142 \
143 __nr_ppis; \
144 })
145
146#define GICR_WAKER_ProcessorSleep (1U << 1)
147#define GICR_WAKER_ChildrenAsleep (1U << 2)
148
149#define GIC_BASER_CACHE_nCnB 0ULL
150#define GIC_BASER_CACHE_SameAsInner 0ULL
151#define GIC_BASER_CACHE_nC 1ULL
152#define GIC_BASER_CACHE_RaWt 2ULL
153#define GIC_BASER_CACHE_RaWb 3ULL
154#define GIC_BASER_CACHE_WaWt 4ULL
155#define GIC_BASER_CACHE_WaWb 5ULL
156#define GIC_BASER_CACHE_RaWaWt 6ULL
157#define GIC_BASER_CACHE_RaWaWb 7ULL
158#define GIC_BASER_CACHE_MASK 7ULL
159#define GIC_BASER_NonShareable 0ULL
160#define GIC_BASER_InnerShareable 1ULL
161#define GIC_BASER_OuterShareable 2ULL
162#define GIC_BASER_SHAREABILITY_MASK 3ULL
163
164#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
165 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
166
167#define GIC_BASER_SHAREABILITY(reg, type) \
168 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
169
170
171#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
172
173#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
174#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
175#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
176#define GICR_PROPBASER_SHAREABILITY_MASK \
177 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
178#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
179 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
180#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
182#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
183
184#define GICR_PROPBASER_InnerShareable \
185 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
186
187#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
188#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
189#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
190#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)
191#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
192#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
193#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
194#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
195
196#define GICR_PROPBASER_IDBITS_MASK (0x1f)
197#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
198#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
199
200#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
201#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
202#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
203#define GICR_PENDBASER_SHAREABILITY_MASK \
204 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
205#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
206 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
207#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
209#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
210
211#define GICR_PENDBASER_InnerShareable \
212 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
213
214#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
215#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
216#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
217#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)
218#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
219#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
220#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
221#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
222
223#define GICR_PENDBASER_PTZ BIT_ULL(62)
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225
226
227
228#define GICR_IGROUPR0 GICD_IGROUPR
229#define GICR_ISENABLER0 GICD_ISENABLER
230#define GICR_ICENABLER0 GICD_ICENABLER
231#define GICR_ISPENDR0 GICD_ISPENDR
232#define GICR_ICPENDR0 GICD_ICPENDR
233#define GICR_ISACTIVER0 GICD_ISACTIVER
234#define GICR_ICACTIVER0 GICD_ICACTIVER
235#define GICR_IPRIORITYR0 GICD_IPRIORITYR
236#define GICR_ICFGR0 GICD_ICFGR
237#define GICR_IGRPMODR0 GICD_IGRPMODR
238#define GICR_NSACR GICD_NSACR
239
240#define GICR_TYPER_PLPIS (1U << 0)
241#define GICR_TYPER_VLPIS (1U << 1)
242#define GICR_TYPER_DIRTY (1U << 2)
243#define GICR_TYPER_DirectLPIS (1U << 3)
244#define GICR_TYPER_LAST (1U << 4)
245#define GICR_TYPER_RVPEID (1U << 7)
246#define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
247#define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
248
249#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
250#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
251#define GICR_INVLPIR_V GENMASK_ULL(63, 63)
252
253#define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID
254#define GICR_INVALLR_V GICR_INVLPIR_V
255
256#define GIC_V3_REDIST_SIZE 0x20000
257
258#define LPI_PROP_GROUP1 (1 << 1)
259#define LPI_PROP_ENABLED (1 << 0)
260
261
262
263
264#define GICR_VPROPBASER 0x0070
265
266#define GICR_VPROPBASER_IDBITS_MASK 0x1f
267
268#define GICR_VPROPBASER_SHAREABILITY_SHIFT (10)
269#define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7)
270#define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56)
271
272#define GICR_VPROPBASER_SHAREABILITY_MASK \
273 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK)
274#define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \
275 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
276#define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \
277 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
278#define GICR_VPROPBASER_CACHEABILITY_MASK \
279 GICR_VPROPBASER_INNER_CACHEABILITY_MASK
280
281#define GICR_VPROPBASER_InnerShareable \
282 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable)
283
284#define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
285#define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
286#define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
287#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb)
288#define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
289#define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
290#define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
291#define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
292
293
294
295
296
297#define GICR_VPROPBASER_4_1_VALID (1ULL << 63)
298#define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
299#define GICR_VPROPBASER_4_1_INDIRECT (1ULL << 55)
300#define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
301#define GICR_VPROPBASER_4_1_Z (1ULL << 52)
302#define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)
303#define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)
304
305#define GICR_VPENDBASER 0x0078
306
307#define GICR_VPENDBASER_SHAREABILITY_SHIFT (10)
308#define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7)
309#define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56)
310#define GICR_VPENDBASER_SHAREABILITY_MASK \
311 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK)
312#define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \
313 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
314#define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \
315 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
316#define GICR_VPENDBASER_CACHEABILITY_MASK \
317 GICR_VPENDBASER_INNER_CACHEABILITY_MASK
318
319#define GICR_VPENDBASER_NonShareable \
320 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
321
322#define GICR_VPENDBASER_InnerShareable \
323 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
324
325#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
326#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
327#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
328#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb)
329#define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
330#define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
331#define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
332#define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb)
333
334#define GICR_VPENDBASER_Dirty (1ULL << 60)
335#define GICR_VPENDBASER_PendingLast (1ULL << 61)
336#define GICR_VPENDBASER_IDAI (1ULL << 62)
337#define GICR_VPENDBASER_Valid (1ULL << 63)
338
339
340
341
342
343#define GICR_VPENDBASER_4_1_DB (1ULL << 62)
344#define GICR_VPENDBASER_4_1_VGRP0EN (1ULL << 59)
345#define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58)
346#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)
347
348#define GICR_VSGIR 0x0080
349
350#define GICR_VSGIR_VPEID GENMASK(15, 0)
351
352#define GICR_VSGIPENDR 0x0088
353
354#define GICR_VSGIPENDR_BUSY (1U << 31)
355#define GICR_VSGIPENDR_PENDING GENMASK(15, 0)
356
357
358
359
360#define GITS_CTLR 0x0000
361#define GITS_IIDR 0x0004
362#define GITS_TYPER 0x0008
363#define GITS_MPIDR 0x0018
364#define GITS_CBASER 0x0080
365#define GITS_CWRITER 0x0088
366#define GITS_CREADR 0x0090
367#define GITS_BASER 0x0100
368#define GITS_IDREGS_BASE 0xffd0
369#define GITS_PIDR0 0xffe0
370#define GITS_PIDR1 0xffe4
371#define GITS_PIDR2 GICR_PIDR2
372#define GITS_PIDR4 0xffd0
373#define GITS_CIDR0 0xfff0
374#define GITS_CIDR1 0xfff4
375#define GITS_CIDR2 0xfff8
376#define GITS_CIDR3 0xfffc
377
378#define GITS_TRANSLATER 0x10040
379
380#define GITS_SGIR 0x20020
381
382#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
383#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
384
385#define GITS_CTLR_ENABLE (1U << 0)
386#define GITS_CTLR_ImDe (1U << 1)
387#define GITS_CTLR_ITS_NUMBER_SHIFT 4
388#define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
389#define GITS_CTLR_QUIESCENT (1U << 31)
390
391#define GITS_TYPER_PLPIS (1UL << 0)
392#define GITS_TYPER_VLPIS (1UL << 1)
393#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
394#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)
395#define GITS_TYPER_IDBITS_SHIFT 8
396#define GITS_TYPER_DEVBITS_SHIFT 13
397#define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)
398#define GITS_TYPER_PTA (1UL << 19)
399#define GITS_TYPER_HCC_SHIFT 24
400#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
401#define GITS_TYPER_VMOVP (1ULL << 37)
402#define GITS_TYPER_VMAPP (1ULL << 40)
403#define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
404
405#define GITS_IIDR_REV_SHIFT 12
406#define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
407#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
408#define GITS_IIDR_PRODUCTID_SHIFT 24
409
410#define GITS_CBASER_VALID (1ULL << 63)
411#define GITS_CBASER_SHAREABILITY_SHIFT (10)
412#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
413#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
414#define GITS_CBASER_SHAREABILITY_MASK \
415 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
416#define GITS_CBASER_INNER_CACHEABILITY_MASK \
417 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
418#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
419 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
420#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
421
422#define GITS_CBASER_InnerShareable \
423 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
424
425#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
426#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
427#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
428#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb)
429#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
430#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
431#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
432#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
433
434#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))
435
436#define GITS_BASER_NR_REGS 8
437
438#define GITS_BASER_VALID (1ULL << 63)
439#define GITS_BASER_INDIRECT (1ULL << 62)
440
441#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
442#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
443#define GITS_BASER_INNER_CACHEABILITY_MASK \
444 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
445#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
446#define GITS_BASER_OUTER_CACHEABILITY_MASK \
447 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
448#define GITS_BASER_SHAREABILITY_MASK \
449 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
450
451#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
452#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
453#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
454#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)
455#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
456#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
457#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
458#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
459
460#define GITS_BASER_TYPE_SHIFT (56)
461#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
462#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
463#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
464#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
465#define GITS_BASER_PHYS_52_to_48(phys) \
466 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
467#define GITS_BASER_ADDR_48_to_52(baser) \
468 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
469
470#define GITS_BASER_SHAREABILITY_SHIFT (10)
471#define GITS_BASER_InnerShareable \
472 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
473#define GITS_BASER_PAGE_SIZE_SHIFT (8)
474#define __GITS_BASER_PSZ(sz) (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT)
475#define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K)
476#define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K)
477#define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K)
478#define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK)
479#define GITS_BASER_PAGES_MAX 256
480#define GITS_BASER_PAGES_SHIFT (0)
481#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
482
483#define GITS_BASER_TYPE_NONE 0
484#define GITS_BASER_TYPE_DEVICE 1
485#define GITS_BASER_TYPE_VCPU 2
486#define GITS_BASER_TYPE_RESERVED3 3
487#define GITS_BASER_TYPE_COLLECTION 4
488#define GITS_BASER_TYPE_RESERVED5 5
489#define GITS_BASER_TYPE_RESERVED6 6
490#define GITS_BASER_TYPE_RESERVED7 7
491
492#define GITS_LVL1_ENTRY_SIZE (8UL)
493
494
495
496
497#define GITS_CMD_MAPD 0x08
498#define GITS_CMD_MAPC 0x09
499#define GITS_CMD_MAPTI 0x0a
500#define GITS_CMD_MAPI 0x0b
501#define GITS_CMD_MOVI 0x01
502#define GITS_CMD_DISCARD 0x0f
503#define GITS_CMD_INV 0x0c
504#define GITS_CMD_MOVALL 0x0e
505#define GITS_CMD_INVALL 0x0d
506#define GITS_CMD_INT 0x03
507#define GITS_CMD_CLEAR 0x04
508#define GITS_CMD_SYNC 0x05
509
510
511
512
513#define GITS_CMD_GICv4(x) ((x) | 0x20)
514#define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL)
515#define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC)
516#define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
517#define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
518#define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
519
520#define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
521#define GITS_CMD_VSGI GITS_CMD_GICv4(3)
522#define GITS_CMD_INVDB GITS_CMD_GICv4(0xe)
523
524
525
526
527#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
528#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
529#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
530#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
531#define E_ITS_MAPD_DEVICE_OOR 0x010801
532#define E_ITS_MAPD_ITTSIZE_OOR 0x010802
533#define E_ITS_MAPC_PROCNUM_OOR 0x010902
534#define E_ITS_MAPC_COLLECTION_OOR 0x010903
535#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
536#define E_ITS_MAPTI_ID_OOR 0x010a05
537#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
538#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
539#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
540#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
541#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
542
543
544
545
546#define ICC_CTLR_EL1_EOImode_SHIFT (1)
547#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
548#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
549#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
550#define ICC_CTLR_EL1_CBPR_SHIFT 0
551#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
552#define ICC_CTLR_EL1_PMHE_SHIFT 6
553#define ICC_CTLR_EL1_PMHE_MASK (1 << ICC_CTLR_EL1_PMHE_SHIFT)
554#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
555#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
556#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
557#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
558#define ICC_CTLR_EL1_SEIS_SHIFT 14
559#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
560#define ICC_CTLR_EL1_A3V_SHIFT 15
561#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
562#define ICC_CTLR_EL1_RSS (0x1 << 18)
563#define ICC_CTLR_EL1_ExtRange (0x1 << 19)
564#define ICC_PMR_EL1_SHIFT 0
565#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
566#define ICC_BPR0_EL1_SHIFT 0
567#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
568#define ICC_BPR1_EL1_SHIFT 0
569#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
570#define ICC_IGRPEN0_EL1_SHIFT 0
571#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
572#define ICC_IGRPEN1_EL1_SHIFT 0
573#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
574#define ICC_SRE_EL1_DIB (1U << 2)
575#define ICC_SRE_EL1_DFB (1U << 1)
576#define ICC_SRE_EL1_SRE (1U << 0)
577
578
579#define GICH_LR_VIRTUALID (0x3ffUL << 0)
580#define GICH_LR_PHYSID_CPUID_SHIFT (10)
581#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
582
583#define ICC_IAR1_EL1_SPURIOUS 0x3ff
584
585#define ICC_SRE_EL2_SRE (1 << 0)
586#define ICC_SRE_EL2_ENABLE (1 << 3)
587
588#define ICC_SGI1R_TARGET_LIST_SHIFT 0
589#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
590#define ICC_SGI1R_AFFINITY_1_SHIFT 16
591#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
592#define ICC_SGI1R_SGI_ID_SHIFT 24
593#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
594#define ICC_SGI1R_AFFINITY_2_SHIFT 32
595#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
596#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
597#define ICC_SGI1R_RS_SHIFT 44
598#define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
599#define ICC_SGI1R_AFFINITY_3_SHIFT 48
600#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
601
602#include <asm/arch_gicv3.h>
603
604#ifndef __ASSEMBLY__
605
606
607
608
609
610#define GIC_IRQ_TYPE_LPI 0xa110c8ed
611
612struct rdists {
613 struct {
614 raw_spinlock_t rd_lock;
615 void __iomem *rd_base;
616 struct page *pend_page;
617 phys_addr_t phys_base;
618 bool lpi_enabled;
619 cpumask_t *vpe_table_mask;
620 void *vpe_l1_base;
621 } __percpu *rdist;
622 phys_addr_t prop_table_pa;
623 void *prop_table_va;
624 u64 flags;
625 u32 gicd_typer;
626 u32 gicd_typer2;
627 bool has_vlpis;
628 bool has_rvpeid;
629 bool has_direct_lpi;
630 bool has_vpend_valid_dirty;
631};
632
633struct irq_domain;
634struct fwnode_handle;
635int its_cpu_init(void);
636int its_init(struct fwnode_handle *handle, struct rdists *rdists,
637 struct irq_domain *domain);
638int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
639
640static inline bool gic_enable_sre(void)
641{
642 u32 val;
643
644 val = gic_read_sre();
645 if (val & ICC_SRE_EL1_SRE)
646 return true;
647
648 val |= ICC_SRE_EL1_SRE;
649 gic_write_sre(val);
650 val = gic_read_sre();
651
652 return !!(val & ICC_SRE_EL1_SRE);
653}
654
655#endif
656
657#endif
658