1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * include/linux/irqchip/arm-gic.h 4 * 5 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 6 */ 7#ifndef __LINUX_IRQCHIP_ARM_GIC_H 8#define __LINUX_IRQCHIP_ARM_GIC_H 9 10#define GIC_CPU_CTRL 0x00 11#define GIC_CPU_PRIMASK 0x04 12#define GIC_CPU_BINPOINT 0x08 13#define GIC_CPU_INTACK 0x0c 14#define GIC_CPU_EOI 0x10 15#define GIC_CPU_RUNNINGPRI 0x14 16#define GIC_CPU_HIGHPRI 0x18 17#define GIC_CPU_ALIAS_BINPOINT 0x1c 18#define GIC_CPU_ACTIVEPRIO 0xd0 19#define GIC_CPU_IDENT 0xfc 20#define GIC_CPU_DEACTIVATE 0x1000 21 22#define GICC_ENABLE 0x1 23#define GICC_INT_PRI_THRESHOLD 0xf0 24 25#define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 26#define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) 27#define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 28#define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) 29#define GIC_CPU_CTRL_AckCtl_SHIFT 2 30#define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) 31#define GIC_CPU_CTRL_FIQEn_SHIFT 3 32#define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) 33#define GIC_CPU_CTRL_CBPR_SHIFT 4 34#define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) 35#define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 36#define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) 37 38#define GICC_IAR_INT_ID_MASK 0x3ff 39#define GICC_INT_SPURIOUS 1023 40#define GICC_DIS_BYPASS_MASK 0x1e0 41 42#define GIC_DIST_CTRL 0x000 43#define GIC_DIST_CTR 0x004 44#define GIC_DIST_IIDR 0x008 45#define GIC_DIST_IGROUP 0x080 46#define GIC_DIST_ENABLE_SET 0x100 47#define GIC_DIST_ENABLE_CLEAR 0x180 48#define GIC_DIST_PENDING_SET 0x200 49#define GIC_DIST_PENDING_CLEAR 0x280 50#define GIC_DIST_ACTIVE_SET 0x300 51#define GIC_DIST_ACTIVE_CLEAR 0x380 52#define GIC_DIST_PRI 0x400 53#define GIC_DIST_TARGET 0x800 54#define GIC_DIST_CONFIG 0xc00 55#define GIC_DIST_SOFTINT 0xf00 56#define GIC_DIST_SGI_PENDING_CLEAR 0xf10 57#define GIC_DIST_SGI_PENDING_SET 0xf20 58 59#define GICD_ENABLE 0x1 60#define GICD_DISABLE 0x0 61#define GICD_INT_ACTLOW_LVLTRIG 0x0 62#define GICD_INT_EN_CLR_X32 0xffffffff 63#define GICD_INT_EN_SET_SGI 0x0000ffff 64#define GICD_INT_EN_CLR_PPI 0xffff0000 65 66#define GICD_IIDR_IMPLEMENTER_SHIFT 0 67#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) 68#define GICD_IIDR_REVISION_SHIFT 12 69#define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) 70#define GICD_IIDR_VARIANT_SHIFT 16 71#define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) 72#define GICD_IIDR_PRODUCT_ID_SHIFT 24 73#define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) 74 75 76#define GICH_HCR 0x0 77#define GICH_VTR 0x4 78#define GICH_VMCR 0x8 79#define GICH_MISR 0x10 80#define GICH_EISR0 0x20 81#define GICH_EISR1 0x24 82#define GICH_ELRSR0 0x30 83#define GICH_ELRSR1 0x34 84#define GICH_APR 0xf0 85#define GICH_LR0 0x100 86 87#define GICH_HCR_EN (1 << 0) 88#define GICH_HCR_UIE (1 << 1) 89#define GICH_HCR_NPIE (1 << 3) 90 91#define GICH_LR_VIRTUALID (0x3ff << 0) 92#define GICH_LR_PHYSID_CPUID_SHIFT (10) 93#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) 94#define GICH_LR_PRIORITY_SHIFT 23 95#define GICH_LR_STATE (3 << 28) 96#define GICH_LR_PENDING_BIT (1 << 28) 97#define GICH_LR_ACTIVE_BIT (1 << 29) 98#define GICH_LR_EOI (1 << 19) 99#define GICH_LR_GROUP1 (1 << 30) 100#define GICH_LR_HW (1 << 31) 101 102#define GICH_VMCR_ENABLE_GRP0_SHIFT 0 103#define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) 104#define GICH_VMCR_ENABLE_GRP1_SHIFT 1 105#define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) 106#define GICH_VMCR_ACK_CTL_SHIFT 2 107#define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) 108#define GICH_VMCR_FIQ_EN_SHIFT 3 109#define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) 110#define GICH_VMCR_CBPR_SHIFT 4 111#define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) 112#define GICH_VMCR_EOI_MODE_SHIFT 9 113#define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) 114 115#define GICH_VMCR_PRIMASK_SHIFT 27 116#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) 117#define GICH_VMCR_BINPOINT_SHIFT 21 118#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) 119#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 120#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) 121 122#define GICH_MISR_EOI (1 << 0) 123#define GICH_MISR_U (1 << 1) 124 125#define GICV_PMR_PRIORITY_SHIFT 3 126#define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) 127 128#ifndef __ASSEMBLY__ 129 130#include <linux/irqdomain.h> 131 132struct device_node; 133struct gic_chip_data; 134 135void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 136int gic_cpu_if_down(unsigned int gic_nr); 137void gic_cpu_save(struct gic_chip_data *gic); 138void gic_cpu_restore(struct gic_chip_data *gic); 139void gic_dist_save(struct gic_chip_data *gic); 140void gic_dist_restore(struct gic_chip_data *gic); 141 142/* 143 * Subdrivers that need some preparatory work can initialize their 144 * chips and call this to register their GICs. 145 */ 146int gic_of_init(struct device_node *node, struct device_node *parent); 147 148/* 149 * Initialises and registers a non-root or child GIC chip. Memory for 150 * the gic_chip_data structure is dynamically allocated. 151 */ 152int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); 153 154/* 155 * Legacy platforms not converted to DT yet must use this to init 156 * their GIC 157 */ 158void gic_init(void __iomem *dist , void __iomem *cpu); 159 160void gic_send_sgi(unsigned int cpu_id, unsigned int irq); 161int gic_get_cpu_id(unsigned int cpu); 162void gic_migrate_target(unsigned int new_cpu_id); 163unsigned long gic_get_sgir_physaddr(void); 164 165#endif /* __ASSEMBLY */ 166#endif 167