1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved 4 * 5 * Declarations for Altera Arria10 MAX5 System Resource Chip 6 * 7 * Adapted from DA9052 8 */ 9 10#ifndef __MFD_ALTERA_A10SR_H 11#define __MFD_ALTERA_A10SR_H 12 13#include <linux/completion.h> 14#include <linux/list.h> 15#include <linux/mfd/core.h> 16#include <linux/regmap.h> 17#include <linux/slab.h> 18 19/* Write registers are always on even addresses */ 20#define WRITE_REG_MASK 0xFE 21/* Odd registers are always on odd addresses */ 22#define READ_REG_MASK 0x01 23 24#define ALTR_A10SR_BITS_PER_REGISTER 8 25/* 26 * To find the correct register, we divide the input GPIO by 27 * the number of GPIO in each register. We then need to multiply 28 * by 2 because the reads are at odd addresses. 29 */ 30#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) 31#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) 32#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) 33#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) 34 35/* Arria10 System Controller Register Defines */ 36#define ALTR_A10SR_NOP 0x00 /* No Change */ 37#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ 38 39#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ 40/* LED register Bit Definitions */ 41#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ 42#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT 43#define ALTR_A10SR_OUT_VALID_RANGE_HI 7 44 45#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */ 46#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */ 47/* Pushbutton & DIP Switch Bit Definitions */ 48#define ALTR_A10SR_IN_VALID_RANGE_LO 8 49#define ALTR_A10SR_IN_VALID_RANGE_HI 15 50 51#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */ 52#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */ 53#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */ 54#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */ 55#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */ 56#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */ 57#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */ 58#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */ 59#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */ 60#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */ 61#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */ 62#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */ 63 64/** 65 * struct altr_a10sr - Altera Max5 MFD device private data structure 66 * @dev: : this device 67 * @regmap: the regmap assigned to the parent device. 68 */ 69struct altr_a10sr { 70 struct device *dev; 71 struct regmap *regmap; 72}; 73 74#endif /* __MFD_ALTERA_A10SR_H */ 75