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10#ifndef __MFD_DB8500_PRCMU_H
11#define __MFD_DB8500_PRCMU_H
12
13#include <linux/interrupt.h>
14#include <linux/bitops.h>
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18
19#define DB8500_PRCM_LINE_VALUE 0x170
20#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
21
22#define DB8500_PRCM_DSI_SW_RESET 0x324
23#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
24#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
25#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
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34
35enum state {
36 OFF = 0x0,
37 ON = 0x1,
38};
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44enum ret_state {
45 OFFST = 0,
46 ONST = 1,
47 RETST = 2
48};
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58enum clk_arm {
59 A9_OFF,
60 A9_BOOT,
61 A9_OPPT1,
62 A9_OPPT2,
63 A9_EXTCLK
64};
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72enum clk_gen {
73 GEN_OFF,
74 GEN_BOOT,
75 GEN_OPPT1,
76};
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86enum romcode_write {
87 RDY_2_DS = 0x09,
88 RDY_2_XP70_RST = 0x10
89};
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106enum romcode_read {
107 INIT = 0x00,
108 FS_2_DS = 0x0A,
109 END_DS = 0x0B,
110 DS_TO_FS = 0x0C,
111 END_FS = 0x0D,
112 SWR = 0x0E,
113 END_SWR = 0x0F
114};
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126enum ap_pwrst {
127 NO_PWRST = 0x00,
128 AP_BOOT = 0x01,
129 AP_EXECUTE = 0x02,
130 AP_DEEP_SLEEP = 0x03,
131 AP_SLEEP = 0x04,
132 AP_IDLE = 0x05,
133 AP_RESET = 0x06
134};
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146enum ap_pwrst_trans {
147 PRCMU_AP_NO_CHANGE = 0x00,
148 APEXECUTE_TO_APSLEEP = 0x01,
149 APIDLE_TO_APSLEEP = 0x02,
150 PRCMU_AP_SLEEP = 0x01,
151 APBOOT_TO_APEXECUTE = 0x03,
152 APEXECUTE_TO_APDEEPSLEEP = 0x04,
153 PRCMU_AP_DEEP_SLEEP = 0x04,
154 APEXECUTE_TO_APIDLE = 0x05,
155 PRCMU_AP_IDLE = 0x05,
156 PRCMU_AP_DEEP_IDLE = 0x07,
157};
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170enum hw_acc_state {
171 HW_NO_CHANGE = 0x00,
172 HW_OFF = 0x01,
173 HW_OFF_RAMRET = 0x02,
174 HW_ON = 0x04
175};
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204enum ap_pwrsttr_status {
205 BOOT_TO_EXECUTEOK = 0xFF,
206 DEEPSLEEPOK = 0xFE,
207 SLEEPOK = 0xFD,
208 IDLEOK = 0xFC,
209 SOFTRESETOK = 0xFB,
210 SOFTRESETGO = 0xFA,
211 BOOT_TO_EXECUTE = 0xF9,
212 EXECUTE_TO_DEEPSLEEP = 0xF8,
213 DEEPSLEEP_TO_EXECUTE = 0xF7,
214 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
215 EXECUTE_TO_SLEEP = 0xF5,
216 SLEEP_TO_EXECUTE = 0xF4,
217 SLEEP_TO_EXECUTEOK = 0xF3,
218 EXECUTE_TO_IDLE = 0xF2,
219 IDLE_TO_EXECUTE = 0xF1,
220 IDLE_TO_EXECUTEOK = 0xF0,
221 RDYTODS_RETURNTOEXE = 0xEF,
222 NORDYTODS_RETURNTOEXE = 0xEE,
223 EXETOSLEEP_RETURNTOEXE = 0xED,
224 EXETOIDLE_RETURNTOEXE = 0xEC,
225 INIT_STATUS = 0xEB,
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227
228 INITERROR = 0x00,
229 PLLARMLOCKP_ER = 0x01,
230 PLLDDRLOCKP_ER = 0x02,
231 PLLSOCLOCKP_ER = 0x03,
232 PLLSOCK1LOCKP_ER = 0x04,
233 ARMWFI_ER = 0x05,
234 SYSCLKOK_ER = 0x06,
235 I2C_NACK_DATA_ER = 0x07,
236 BOOT_ER = 0x08,
237 I2C_STATUS_ALWAYS_1 = 0x0A,
238 I2C_NACK_REG_ADDR_ER = 0x0B,
239 I2C_NACK_DATA0123_ER = 0x1B,
240 I2C_NACK_ADDR_ER = 0x1F,
241 CURAPPWRSTISNOT_BOOT = 0x20,
242 CURAPPWRSTISNOT_EXECUTE = 0x21,
243 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
244 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
245 FIFO4500WUISNOT_WUPEVENT = 0x24,
246 PLL32KLOCKP_ER = 0x29,
247 DDRDEEPSLEEPOK_ER = 0x2A,
248 ROMCODEREADY_ER = 0x50,
249 WUPBEFOREDS = 0x51,
250 DDRCONFIG_ER = 0x52,
251 WUPBEFORESLEEP = 0x53,
252 WUPBEFOREIDLE = 0x54
253};
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265enum dvfs_stat {
266 DVFS_GO = 0xFF,
267 DVFS_ARM100OPPOK = 0xFE,
268 DVFS_ARM50OPPOK = 0xFD,
269 DVFS_ARMEXTCLKOK = 0xFC,
270 DVFS_NOCHGTCLKOK = 0xFB,
271 DVFS_INITSTATUS = 0x00
272};
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279enum sva_mmdsp_stat {
280 SVA_MMDSP_GO = 0xFF,
281 SVA_MMDSP_INIT = 0x00
282};
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289enum sia_mmdsp_stat {
290 SIA_MMDSP_GO = 0xFF,
291 SIA_MMDSP_INIT = 0x00
292};
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351enum mbox_to_arm_err {
352 INIT_ERR = 0x00,
353 PLLARMLOCKP_ERR = 0x01,
354 PLLDDRLOCKP_ERR = 0x02,
355 PLLSOC0LOCKP_ERR = 0x03,
356 PLLSOC1LOCKP_ERR = 0x04,
357 ARMWFI_ERR = 0x05,
358 SYSCLKOK_ERR = 0x06,
359 BOOT_ERR = 0x07,
360 ROMCODESAVECONTEXT = 0x08,
361 VARMHIGHSPEEDVALTO_ERR = 0x10,
362 VARMHIGHSPEEDACCESS_ERR = 0x11,
363 VARMLOWSPEEDVALTO_ERR = 0x12,
364 VARMLOWSPEEDACCESS_ERR = 0x13,
365 VARMRETENTIONVALTO_ERR = 0x14,
366 VARMRETENTIONACCESS_ERR = 0x15,
367 VAPEHIGHSPEEDVALTO_ERR = 0x16,
368 VSAFEHPVALTO_ERR = 0x17,
369 VMODSEL1VALTO_ERR = 0x18,
370 VMODSEL2VALTO_ERR = 0x19,
371 VARMOFFACCESS_ERR = 0x1A,
372 VAPEOFFACCESS_ERR = 0x1B,
373 VARMRETACCES_ERR = 0x1C,
374 CURAPPWRSTISNOTBOOT = 0x20,
375 CURAPPWRSTISNOTEXECUTE = 0x21,
376 CURAPPWRSTISNOTSLEEPMODE = 0x22,
377 CURAPPWRSTISNOTCORRECTDBG = 0x23,
378 ARMREGU1VALTO_ERR = 0x24,
379 ARMREGU2VALTO_ERR = 0x25,
380 VAPEREGUVALTO_ERR = 0x26,
381 VSMPS3REGUVALTO_ERR = 0x27,
382 VMODREGUVALTO_ERR = 0x28
383};
384
385enum hw_acc {
386 SVAMMDSP = 0,
387 SVAPIPE = 1,
388 SIAMMDSP = 2,
389 SIAPIPE = 3,
390 SGA = 4,
391 B2R2MCDE = 5,
392 ESRAM12 = 6,
393 ESRAM34 = 7,
394};
395
396enum cs_pwrmgt {
397 PWRDNCS0 = 0,
398 WKUPCS0 = 1,
399 PWRDNCS1 = 2,
400 WKUPCS1 = 3
401};
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414enum sia_sva_pwr_policy {
415 NO_CHGT = 0x0,
416 DSPOFF_HWPOFF = 0x1,
417 DSPOFFRAMRET_HWPOFF = 0x2,
418 DSPCLKOFF_HWPOFF = 0x3,
419 DSPCLKOFF_HWPCLKOFF = 0x4,
420};
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428enum auto_enable {
429 AUTO_OFF = 0x0,
430 AUTO_ON = 0x1,
431};
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445enum prcmu_power_status {
446 PRCMU_SLEEP_OK = 0xf3,
447 PRCMU_DEEP_SLEEP_OK = 0xf6,
448 PRCMU_IDLE_OK = 0xf0,
449 PRCMU_DEEPIDLE_OK = 0xe3,
450 PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
451 PRCMU_ARMPENDINGIT_ER = 0x93,
452};
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458#define PRCMU_AUTO_PM_OFF 0
459#define PRCMU_AUTO_PM_ON 1
460
461#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
462#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
463
464enum prcmu_auto_pm_policy {
465 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
466 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
467 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
468 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
469 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
470};
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481struct prcmu_auto_pm_config {
482 u8 sia_auto_pm_enable;
483 u8 sia_power_on;
484 u8 sia_policy;
485 u8 sva_auto_pm_enable;
486 u8 sva_power_on;
487 u8 sva_policy;
488};
489
490#ifdef CONFIG_MFD_DB8500_PRCMU
491
492void db8500_prcmu_early_init(void);
493int prcmu_set_rc_a2p(enum romcode_write);
494enum romcode_read prcmu_get_rc_p2a(void);
495enum ap_pwrst prcmu_get_xp70_current_state(void);
496bool prcmu_has_arm_maxopp(void);
497struct prcmu_fw_version *prcmu_get_fw_version(void);
498int prcmu_release_usb_wakeup_state(void);
499void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
500 struct prcmu_auto_pm_config *idle);
501bool prcmu_is_auto_pm_enabled(void);
502
503int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
504int prcmu_set_clock_divider(u8 clock, u8 divider);
505int db8500_prcmu_config_hotdog(u8 threshold);
506int db8500_prcmu_config_hotmon(u8 low, u8 high);
507int db8500_prcmu_start_temp_sense(u16 cycles32k);
508int db8500_prcmu_stop_temp_sense(void);
509int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
510int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
511
512int prcmu_ac_wake_req(void);
513void prcmu_ac_sleep_req(void);
514void db8500_prcmu_modem_reset(void);
515
516int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
517int db8500_prcmu_enable_a9wdog(u8 id);
518int db8500_prcmu_disable_a9wdog(u8 id);
519int db8500_prcmu_kick_a9wdog(u8 id);
520int db8500_prcmu_load_a9wdog(u8 id, u32 val);
521
522void db8500_prcmu_system_reset(u16 reset_code);
523int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
524u8 db8500_prcmu_get_power_state_result(void);
525void db8500_prcmu_enable_wakeups(u32 wakeups);
526int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
527int db8500_prcmu_request_clock(u8 clock, bool enable);
528void db8500_prcmu_config_abb_event_readout(u32 abb_events);
529void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
530int db8500_prcmu_config_esram0_deep_sleep(u8 state);
531u16 db8500_prcmu_get_reset_code(void);
532bool db8500_prcmu_is_ac_wake_requested(void);
533int db8500_prcmu_set_arm_opp(u8 opp);
534int db8500_prcmu_get_arm_opp(void);
535int db8500_prcmu_set_ape_opp(u8 opp);
536int db8500_prcmu_get_ape_opp(void);
537int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
538int db8500_prcmu_get_ddr_opp(void);
539
540u32 db8500_prcmu_read(unsigned int reg);
541void db8500_prcmu_write(unsigned int reg, u32 value);
542void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
543
544#else
545
546static inline void db8500_prcmu_early_init(void) {}
547
548static inline int prcmu_set_rc_a2p(enum romcode_write code)
549{
550 return 0;
551}
552
553static inline enum romcode_read prcmu_get_rc_p2a(void)
554{
555 return INIT;
556}
557
558static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
559{
560 return AP_EXECUTE;
561}
562
563static inline bool prcmu_has_arm_maxopp(void)
564{
565 return false;
566}
567
568static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
569{
570 return NULL;
571}
572
573static inline int db8500_prcmu_set_ape_opp(u8 opp)
574{
575 return 0;
576}
577
578static inline int db8500_prcmu_get_ape_opp(void)
579{
580 return APE_100_OPP;
581}
582
583static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
584{
585 return 0;
586}
587
588static inline int prcmu_release_usb_wakeup_state(void)
589{
590 return 0;
591}
592
593static inline int db8500_prcmu_get_ddr_opp(void)
594{
595 return DDR_100_OPP;
596}
597
598static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
599 struct prcmu_auto_pm_config *idle)
600{
601}
602
603static inline bool prcmu_is_auto_pm_enabled(void)
604{
605 return false;
606}
607
608static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
609{
610 return 0;
611}
612
613static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
614{
615 return 0;
616}
617
618static inline int db8500_prcmu_config_hotdog(u8 threshold)
619{
620 return 0;
621}
622
623static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
624{
625 return 0;
626}
627
628static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
629{
630 return 0;
631}
632
633static inline int db8500_prcmu_stop_temp_sense(void)
634{
635 return 0;
636}
637
638static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
639{
640 return -ENOSYS;
641}
642
643static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
644{
645 return -ENOSYS;
646}
647
648static inline int prcmu_ac_wake_req(void)
649{
650 return 0;
651}
652
653static inline void prcmu_ac_sleep_req(void) {}
654
655static inline void db8500_prcmu_modem_reset(void) {}
656
657static inline void db8500_prcmu_system_reset(u16 reset_code) {}
658
659static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
660 bool keep_ap_pll)
661{
662 return 0;
663}
664
665static inline u8 db8500_prcmu_get_power_state_result(void)
666{
667 return 0;
668}
669
670static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
671
672static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
673{
674 return 0;
675}
676
677static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
678{
679 return 0;
680}
681
682static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
683{
684 return 0;
685}
686
687static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
688
689static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
690
691static inline u16 db8500_prcmu_get_reset_code(void)
692{
693 return 0;
694}
695
696static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
697{
698 return 0;
699}
700
701static inline int db8500_prcmu_enable_a9wdog(u8 id)
702{
703 return 0;
704}
705
706static inline int db8500_prcmu_disable_a9wdog(u8 id)
707{
708 return 0;
709}
710
711static inline int db8500_prcmu_kick_a9wdog(u8 id)
712{
713 return 0;
714}
715
716static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
717{
718 return 0;
719}
720
721static inline bool db8500_prcmu_is_ac_wake_requested(void)
722{
723 return false;
724}
725
726static inline int db8500_prcmu_set_arm_opp(u8 opp)
727{
728 return 0;
729}
730
731static inline int db8500_prcmu_get_arm_opp(void)
732{
733 return 0;
734}
735
736static inline u32 db8500_prcmu_read(unsigned int reg)
737{
738 return 0;
739}
740
741static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
742
743static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
744 u32 value) {}
745
746#endif
747
748#endif
749