LXR linux/include/linux/mfd/ti_am335x

   1#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
   2#define __LINUX_TI_AM335X_TSCADC_MFD_H
   3
   4/*
   5 * TI Touch Screen / ADC MFD driver
   6 *
   7 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation version 2.
  12 *
  13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14 * kind, whether express or implied; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19#include <linux/mfd/core.h>
  20
  21#define REG_RAWIRQSTATUS        0x024
  22#define REG_IRQSTATUS           0x028
  23#define REG_IRQENABLE           0x02C
  24#define REG_IRQCLR              0x030
  25#define REG_IRQWAKEUP           0x034
  26#define REG_DMAENABLE_SET       0x038
  27#define REG_DMAENABLE_CLEAR     0x03c
  28#define REG_CTRL                0x040
  29#define REG_ADCFSM              0x044
  30#define REG_CLKDIV              0x04C
  31#define REG_SE                  0x054
  32#define REG_IDLECONFIG          0x058
  33#define REG_CHARGECONFIG        0x05C
  34#define REG_CHARGEDELAY         0x060
  35#define REG_STEPCONFIG(n)       (0x64 + ((n) * 8))
  36#define REG_STEPDELAY(n)        (0x68 + ((n) * 8))
  37#define REG_FIFO0CNT            0xE4
  38#define REG_FIFO0THR            0xE8
  39#define REG_FIFO1CNT            0xF0
  40#define REG_FIFO1THR            0xF4
  41#define REG_DMA1REQ             0xF8
  42#define REG_FIFO0               0x100
  43#define REG_FIFO1               0x200
  44
  45/*      Register Bitfields      */
  46/* IRQ wakeup enable */
  47#define IRQWKUP_ENB             BIT(0)
  48
  49/* Step Enable */
  50#define STEPENB_MASK            (0x1FFFF << 0)
  51#define STEPENB(val)            ((val) << 0)
  52#define ENB(val)                        (1 << (val))
  53#define STPENB_STEPENB          STEPENB(0x1FFFF)
  54#define STPENB_STEPENB_TC       STEPENB(0x1FFF)
  55
  56/* IRQ enable */
  57#define IRQENB_HW_PEN           BIT(0)
  58#define IRQENB_EOS              BIT(1)
  59#define IRQENB_FIFO0THRES       BIT(2)
  60#define IRQENB_FIFO0OVRRUN      BIT(3)
  61#define IRQENB_FIFO0UNDRFLW     BIT(4)
  62#define IRQENB_FIFO1THRES       BIT(5)
  63#define IRQENB_FIFO1OVRRUN      BIT(6)
  64#define IRQENB_FIFO1UNDRFLW     BIT(7)
  65#define IRQENB_PENUP            BIT(9)
  66
  67/* Step Configuration */
  68#define STEPCONFIG_MODE_MASK    (3 << 0)
  69#define STEPCONFIG_MODE(val)    ((val) << 0)
  70#define STEPCONFIG_MODE_SWCNT   STEPCONFIG_MODE(1)
  71#define STEPCONFIG_MODE_HWSYNC  STEPCONFIG_MODE(2)
  72#define STEPCONFIG_AVG_MASK     (7 << 2)
  73#define STEPCONFIG_AVG(val)     ((val) << 2)
  74#define STEPCONFIG_AVG_16       STEPCONFIG_AVG(4)
  75#define STEPCONFIG_XPP          BIT(5)
  76#define STEPCONFIG_XNN          BIT(6)
  77#define STEPCONFIG_YPP          BIT(7)
  78#define STEPCONFIG_YNN          BIT(8)
  79#define STEPCONFIG_XNP          BIT(9)
  80#define STEPCONFIG_YPN          BIT(10)
  81#define STEPCONFIG_RFP(val)     ((val) << 12)
  82#define STEPCONFIG_RFP_VREFP    (0x3 << 12)
  83#define STEPCONFIG_INM_MASK     (0xF << 15)
  84#define STEPCONFIG_INM(val)     ((val) << 15)
  85#define STEPCONFIG_INM_ADCREFM  STEPCONFIG_INM(8)
  86#define STEPCONFIG_INP_MASK     (0xF << 19)
  87#define STEPCONFIG_INP(val)     ((val) << 19)
  88#define STEPCONFIG_INP_AN4      STEPCONFIG_INP(4)
  89#define STEPCONFIG_INP_ADCREFM  STEPCONFIG_INP(8)
  90#define STEPCONFIG_FIFO1        BIT(26)
  91#define STEPCONFIG_RFM(val)     ((val) << 23)
  92#define STEPCONFIG_RFM_VREFN    (0x3 << 23)
  93
  94/* Delay register */
  95#define STEPDELAY_OPEN_MASK     (0x3FFFF << 0)
  96#define STEPDELAY_OPEN(val)     ((val) << 0)
  97#define STEPCONFIG_OPENDLY      STEPDELAY_OPEN(0x098)
  98#define STEPDELAY_SAMPLE_MASK   (0xFF << 24)
  99#define STEPDELAY_SAMPLE(val)   ((val) << 24)
 100#define STEPCONFIG_SAMPLEDLY    STEPDELAY_SAMPLE(0)
 101
 102/* Charge Config */
 103#define STEPCHARGE_RFP_MASK     (7 << 12)
 104#define STEPCHARGE_RFP(val)     ((val) << 12)
 105#define STEPCHARGE_RFP_XPUL     STEPCHARGE_RFP(1)
 106#define STEPCHARGE_INM_MASK     (0xF << 15)
 107#define STEPCHARGE_INM(val)     ((val) << 15)
 108#define STEPCHARGE_INM_AN1      STEPCHARGE_INM(1)
 109#define STEPCHARGE_INP_MASK     (0xF << 19)
 110#define STEPCHARGE_INP(val)     ((val) << 19)
 111#define STEPCHARGE_RFM_MASK     (3 << 23)
 112#define STEPCHARGE_RFM(val)     ((val) << 23)
 113#define STEPCHARGE_RFM_XNUR     STEPCHARGE_RFM(1)
 114
 115/* Charge delay */
 116#define CHARGEDLY_OPEN_MASK     (0x3FFFF << 0)
 117#define CHARGEDLY_OPEN(val)     ((val) << 0)
 118#define CHARGEDLY_OPENDLY       CHARGEDLY_OPEN(0x400)
 119
 120/* Control register */
 121#define CNTRLREG_TSCSSENB       BIT(0)
 122#define CNTRLREG_STEPID         BIT(1)
 123#define CNTRLREG_STEPCONFIGWRT  BIT(2)
 124#define CNTRLREG_POWERDOWN      BIT(4)
 125#define CNTRLREG_AFE_CTRL_MASK  (3 << 5)
 126#define CNTRLREG_AFE_CTRL(val)  ((val) << 5)
 127#define CNTRLREG_4WIRE          CNTRLREG_AFE_CTRL(1)
 128#define CNTRLREG_5WIRE          CNTRLREG_AFE_CTRL(2)
 129#define CNTRLREG_8WIRE          CNTRLREG_AFE_CTRL(3)
 130#define CNTRLREG_TSCENB         BIT(7)
 131
 132/* FIFO READ Register */
 133#define FIFOREAD_DATA_MASK (0xfff << 0)
 134#define FIFOREAD_CHNLID_MASK (0xf << 16)
 135
 136/* DMA ENABLE/CLEAR Register */
 137#define DMA_FIFO0               BIT(0)
 138#define DMA_FIFO1               BIT(1)
 139
 140/* Sequencer Status */
 141#define SEQ_STATUS BIT(5)
 142#define CHARGE_STEP             0x11
 143
 144#define ADC_CLK                 3000000
 145#define TOTAL_STEPS             16
 146#define TOTAL_CHANNELS          8
 147#define FIFO1_THRESHOLD         19
 148
 149/*
 150 * time in us for processing a single channel, calculated as follows:
 151 *
 152 * max num cycles = open delay + (sample delay + conv time) * averaging
 153 *
 154 * max num cycles: 262143 + (255 + 13) * 16 = 266431
 155 *
 156 * clock frequency: 26MHz / 8 = 3.25MHz
 157 * clock period: 1 / 3.25MHz = 308ns
 158 *
 159 * max processing time: 266431 * 308ns = 83ms(approx)
 160 */
 161#define IDLE_TIMEOUT 83 /* milliseconds */
 162
 163#define TSCADC_CELLS            2
 164
 165struct ti_tscadc_dev {
 166        struct device *dev;
 167        struct regmap *regmap;
 168        void __iomem *tscadc_base;
 169        phys_addr_t tscadc_phys_base;
 170        int irq;
 171        int used_cells; /* 1-2 */
 172        int tsc_wires;
 173        int tsc_cell;   /* -1 if not used */
 174        int adc_cell;   /* -1 if not used */
 175        struct mfd_cell cells[TSCADC_CELLS];
 176        u32 reg_se_cache;
 177        bool adc_waiting;
 178        bool adc_in_use;
 179        wait_queue_head_t reg_se_wait;
 180        spinlock_t reg_lock;
 181        unsigned int clk_div;
 182
 183        /* tsc device */
 184        struct titsc *tsc;
 185
 186        /* adc device */
 187        struct adc_device *adc;
 188};
 189
 190static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
 191{
 192        struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
 193
 194        return *tscadc_dev;
 195}
 196
 197void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
 198void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
 199void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
 200void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
 201
 202#endif
 203