LXR linux/include/linux/mlx5/port.h

   1/*
   2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef __MLX5_PORT_H__
  34#define __MLX5_PORT_H__
  35
  36#include <linux/mlx5/driver.h>
  37
  38enum mlx5_beacon_duration {
  39        MLX5_BEACON_DURATION_OFF = 0x0,
  40        MLX5_BEACON_DURATION_INF = 0xffff,
  41};
  42
  43enum mlx5_module_id {
  44        MLX5_MODULE_ID_SFP              = 0x3,
  45        MLX5_MODULE_ID_QSFP             = 0xC,
  46        MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
  47        MLX5_MODULE_ID_QSFP28           = 0x11,
  48        MLX5_MODULE_ID_DSFP             = 0x1B,
  49};
  50
  51enum mlx5_an_status {
  52        MLX5_AN_UNAVAILABLE = 0,
  53        MLX5_AN_COMPLETE    = 1,
  54        MLX5_AN_FAILED      = 2,
  55        MLX5_AN_LINK_UP     = 3,
  56        MLX5_AN_LINK_DOWN   = 4,
  57};
  58
  59#define MLX5_EEPROM_MAX_BYTES                   32
  60#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK        0x000000ff
  61#define MLX5_I2C_ADDR_LOW               0x50
  62#define MLX5_I2C_ADDR_HIGH              0x51
  63#define MLX5_EEPROM_PAGE_LENGTH         256
  64#define MLX5_EEPROM_HIGH_PAGE_LENGTH    128
  65
  66struct mlx5_module_eeprom_query_params {
  67        u16 size;
  68        u16 offset;
  69        u16 i2c_address;
  70        u32 page;
  71        u32 bank;
  72        u32 module_number;
  73};
  74
  75enum mlx5e_link_mode {
  76        MLX5E_1000BASE_CX_SGMII  = 0,
  77        MLX5E_1000BASE_KX        = 1,
  78        MLX5E_10GBASE_CX4        = 2,
  79        MLX5E_10GBASE_KX4        = 3,
  80        MLX5E_10GBASE_KR         = 4,
  81        MLX5E_20GBASE_KR2        = 5,
  82        MLX5E_40GBASE_CR4        = 6,
  83        MLX5E_40GBASE_KR4        = 7,
  84        MLX5E_56GBASE_R4         = 8,
  85        MLX5E_10GBASE_CR         = 12,
  86        MLX5E_10GBASE_SR         = 13,
  87        MLX5E_10GBASE_ER         = 14,
  88        MLX5E_40GBASE_SR4        = 15,
  89        MLX5E_40GBASE_LR4        = 16,
  90        MLX5E_50GBASE_SR2        = 18,
  91        MLX5E_100GBASE_CR4       = 20,
  92        MLX5E_100GBASE_SR4       = 21,
  93        MLX5E_100GBASE_KR4       = 22,
  94        MLX5E_100GBASE_LR4       = 23,
  95        MLX5E_100BASE_TX         = 24,
  96        MLX5E_1000BASE_T         = 25,
  97        MLX5E_10GBASE_T          = 26,
  98        MLX5E_25GBASE_CR         = 27,
  99        MLX5E_25GBASE_KR         = 28,
 100        MLX5E_25GBASE_SR         = 29,
 101        MLX5E_50GBASE_CR2        = 30,
 102        MLX5E_50GBASE_KR2        = 31,
 103        MLX5E_LINK_MODES_NUMBER,
 104};
 105
 106enum mlx5e_ext_link_mode {
 107        MLX5E_SGMII_100M                        = 0,
 108        MLX5E_1000BASE_X_SGMII                  = 1,
 109        MLX5E_5GBASE_R                          = 3,
 110        MLX5E_10GBASE_XFI_XAUI_1                = 4,
 111        MLX5E_40GBASE_XLAUI_4_XLPPI_4           = 5,
 112        MLX5E_25GAUI_1_25GBASE_CR_KR            = 6,
 113        MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2   = 7,
 114        MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR     = 8,
 115        MLX5E_CAUI_4_100GBASE_CR4_KR4           = 9,
 116        MLX5E_100GAUI_2_100GBASE_CR2_KR2        = 10,
 117        MLX5E_100GAUI_1_100GBASE_CR_KR          = 11,
 118        MLX5E_200GAUI_4_200GBASE_CR4_KR4        = 12,
 119        MLX5E_200GAUI_2_200GBASE_CR2_KR2        = 13,
 120        MLX5E_400GAUI_8                         = 15,
 121        MLX5E_400GAUI_4_400GBASE_CR4_KR4        = 16,
 122        MLX5E_EXT_LINK_MODES_NUMBER,
 123};
 124
 125enum mlx5e_connector_type {
 126        MLX5E_PORT_UNKNOWN      = 0,
 127        MLX5E_PORT_NONE                 = 1,
 128        MLX5E_PORT_TP                   = 2,
 129        MLX5E_PORT_AUI                  = 3,
 130        MLX5E_PORT_BNC                  = 4,
 131        MLX5E_PORT_MII                  = 5,
 132        MLX5E_PORT_FIBRE                = 6,
 133        MLX5E_PORT_DA                   = 7,
 134        MLX5E_PORT_OTHER                = 8,
 135        MLX5E_CONNECTOR_TYPE_NUMBER,
 136};
 137
 138enum mlx5_ptys_width {
 139        MLX5_PTYS_WIDTH_1X      = 1 << 0,
 140        MLX5_PTYS_WIDTH_2X      = 1 << 1,
 141        MLX5_PTYS_WIDTH_4X      = 1 << 2,
 142        MLX5_PTYS_WIDTH_8X      = 1 << 3,
 143        MLX5_PTYS_WIDTH_12X     = 1 << 4,
 144};
 145
 146#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
 147#define MLX5_GET_ETH_PROTO(reg, out, ext, field)        \
 148        (ext ? MLX5_GET(reg, out, ext_##field) :        \
 149        MLX5_GET(reg, out, field))
 150
 151int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
 152int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 153                         int ptys_size, int proto_mask, u8 local_port);
 154
 155int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
 156                            u16 *proto_oper, u8 local_port);
 157void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
 158int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 159                               enum mlx5_port_status status);
 160int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 161                                 enum mlx5_port_status *status);
 162int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
 163
 164int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
 165void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
 166void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
 167                              u8 port);
 168
 169int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 170                              u8 *vl_hw_cap, u8 local_port);
 171
 172int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
 173int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 174                          u32 *rx_pause, u32 *tx_pause);
 175
 176int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
 177int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
 178                        u8 *pfc_en_rx);
 179
 180int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
 181                                  u16 stall_critical_watermark,
 182                                  u16 stall_minor_watermark);
 183int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
 184                                    u16 *stall_critical_watermark, u16 *stall_minor_watermark);
 185
 186int mlx5_max_tc(struct mlx5_core_dev *mdev);
 187
 188int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
 189int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
 190                            u8 prio, u8 *tc);
 191int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
 192int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
 193                             u8 tc, u8 *tc_group);
 194int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
 195int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
 196                                u8 tc, u8 *bw_pct);
 197int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 198                                    u8 *max_bw_value,
 199                                    u8 *max_bw_unit);
 200int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 201                                   u8 *max_bw_value,
 202                                   u8 *max_bw_unit);
 203int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
 204int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
 205
 206int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
 207int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
 208int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
 209void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
 210                         bool *enabled);
 211int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
 212                             u16 offset, u16 size, u8 *data);
 213int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
 214                                     struct mlx5_module_eeprom_query_params *params, u8 *data);
 215
 216int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
 217int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
 218
 219int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
 220int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
 221int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
 222int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
 223#endif /* __MLX5_PORT_H__ */
 224