LXR linux/include/linux/mmc/sh

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * include/linux/mmc/sh_mmcif.h
   4 *
   5 * platform data for eMMC driver
   6 *
   7 * Copyright (C) 2010 Renesas Solutions Corp.
   8 */
   9
  10#ifndef LINUX_MMC_SH_MMCIF_H
  11#define LINUX_MMC_SH_MMCIF_H
  12
  13#include <linux/io.h>
  14#include <linux/platform_device.h>
  15
  16/*
  17 * MMCIF : CE_CLK_CTRL [19:16]
  18 * 1000 : Peripheral clock / 512
  19 * 0111 : Peripheral clock / 256
  20 * 0110 : Peripheral clock / 128
  21 * 0101 : Peripheral clock / 64
  22 * 0100 : Peripheral clock / 32
  23 * 0011 : Peripheral clock / 16
  24 * 0010 : Peripheral clock / 8
  25 * 0001 : Peripheral clock / 4
  26 * 0000 : Peripheral clock / 2
  27 * 1111 : Peripheral clock (sup_pclk set '1')
  28 */
  29
  30struct sh_mmcif_plat_data {
  31        unsigned int            slave_id_tx;    /* embedded slave_id_[tr]x */
  32        unsigned int            slave_id_rx;
  33        u8                      sup_pclk;       /* 1 :SH7757, 0: SH7724/SH7372 */
  34        unsigned long           caps;
  35        u32                     ocr;
  36};
  37
  38#define MMCIF_CE_CMD_SET        0x00000000
  39#define MMCIF_CE_ARG            0x00000008
  40#define MMCIF_CE_ARG_CMD12      0x0000000C
  41#define MMCIF_CE_CMD_CTRL       0x00000010
  42#define MMCIF_CE_BLOCK_SET      0x00000014
  43#define MMCIF_CE_CLK_CTRL       0x00000018
  44#define MMCIF_CE_BUF_ACC        0x0000001C
  45#define MMCIF_CE_RESP3          0x00000020
  46#define MMCIF_CE_RESP2          0x00000024
  47#define MMCIF_CE_RESP1          0x00000028
  48#define MMCIF_CE_RESP0          0x0000002C
  49#define MMCIF_CE_RESP_CMD12     0x00000030
  50#define MMCIF_CE_DATA           0x00000034
  51#define MMCIF_CE_INT            0x00000040
  52#define MMCIF_CE_INT_MASK       0x00000044
  53#define MMCIF_CE_HOST_STS1      0x00000048
  54#define MMCIF_CE_HOST_STS2      0x0000004C
  55#define MMCIF_CE_CLK_CTRL2      0x00000070
  56#define MMCIF_CE_VERSION        0x0000007C
  57
  58/* CE_BUF_ACC */
  59#define BUF_ACC_DMAWEN          (1 << 25)
  60#define BUF_ACC_DMAREN          (1 << 24)
  61#define BUF_ACC_BUSW_32         (0 << 17)
  62#define BUF_ACC_BUSW_16         (1 << 17)
  63#define BUF_ACC_ATYP            (1 << 16)
  64
  65/* CE_CLK_CTRL */
  66#define CLK_ENABLE              (1 << 24) /* 1: output mmc clock */
  67#define CLK_CLEAR               (0xf << 16)
  68#define CLK_SUP_PCLK            (0xf << 16)
  69#define CLKDIV_4                (1 << 16) /* mmc clock frequency.
  70                                           * n: bus clock/(2^(n+1)) */
  71#define CLKDIV_256              (7 << 16) /* mmc clock frequency. (see above) */
  72#define SRSPTO_256              (2 << 12) /* resp timeout */
  73#define SRBSYTO_29              (0xf << 8) /* resp busy timeout */
  74#define SRWDTO_29               (0xf << 4) /* read/write timeout */
  75#define SCCSTO_29               (0xf << 0) /* ccs timeout */
  76
  77/* CE_VERSION */
  78#define SOFT_RST_ON             (1 << 31)
  79#define SOFT_RST_OFF            0
  80
  81static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
  82{
  83        return __raw_readl(addr + reg);
  84}
  85
  86static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
  87{
  88        __raw_writel(val, addr + reg);
  89}
  90
  91#define SH_MMCIF_BBS 512 /* boot block size */
  92
  93static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
  94                                          unsigned long cmd, unsigned long arg)
  95{
  96        sh_mmcif_writel(base, MMCIF_CE_INT, 0);
  97        sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
  98        sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
  99}
 100
 101static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
 102{
 103        unsigned long tmp;
 104        int cnt;
 105
 106        for (cnt = 0; cnt < 1000000; cnt++) {
 107                tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
 108                if (tmp & mask) {
 109                        sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
 110                        return 0;
 111                }
 112        }
 113
 114        return -1;
 115}
 116
 117static inline int sh_mmcif_boot_cmd(void __iomem *base,
 118                                    unsigned long cmd, unsigned long arg)
 119{
 120        sh_mmcif_boot_cmd_send(base, cmd, arg);
 121        return sh_mmcif_boot_cmd_poll(base, 0x00010000);
 122}
 123
 124static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
 125                                               unsigned int block_nr,
 126                                               unsigned long *buf)
 127{
 128        int k;
 129
 130        /* CMD13 - Status */
 131        sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
 132
 133        if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
 134                return -1;
 135
 136        /* CMD17 - Read */
 137        sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
 138        if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
 139                return -1;
 140
 141        for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
 142                buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
 143
 144        return 0;
 145}
 146
 147static inline int sh_mmcif_boot_do_read(void __iomem *base,
 148                                        unsigned long first_block,
 149                                        unsigned long nr_blocks,
 150                                        void *buf)
 151{
 152        unsigned long k;
 153        int ret = 0;
 154
 155        /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
 156        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
 157                        CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
 158                        SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 159
 160        /* CMD9 - Get CSD */
 161        sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
 162
 163        /* CMD7 - Select the card */
 164        sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
 165
 166        /* CMD16 - Set the block size */
 167        sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
 168
 169        for (k = 0; !ret && k < nr_blocks; k++)
 170                ret = sh_mmcif_boot_do_read_single(base, first_block + k,
 171                                                   buf + (k * SH_MMCIF_BBS));
 172
 173        return ret;
 174}
 175
 176static inline void sh_mmcif_boot_init(void __iomem *base)
 177{
 178        /* reset */
 179        sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
 180        sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
 181
 182        /* byte swap */
 183        sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 184
 185        /* Set block size in MMCIF hardware */
 186        sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
 187
 188        /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
 189        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
 190                        CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
 191                        SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 192
 193        /* CMD0 */
 194        sh_mmcif_boot_cmd(base, 0x00000040, 0);
 195
 196        /* CMD1 - Get OCR */
 197        do {
 198                sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
 199        } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
 200                 != 0x80000000);
 201
 202        /* CMD2 - Get CID */
 203        sh_mmcif_boot_cmd(base, 0x02806040, 0);
 204
 205        /* CMD3 - Set card relative address */
 206        sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
 207}
 208
 209#endif /* LINUX_MMC_SH_MMCIF_H */
 210