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13#ifndef __LINUX_MTD_RAWNAND_H
14#define __LINUX_MTD_RAWNAND_H
15
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/flashchip.h>
19#include <linux/mtd/bbm.h>
20#include <linux/mtd/jedec.h>
21#include <linux/mtd/onfi.h>
22#include <linux/mutex.h>
23#include <linux/of.h>
24#include <linux/types.h>
25
26struct nand_chip;
27struct gpio_desc;
28
29
30#define NAND_MAX_CHIPS 8
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38
39#define NAND_NCE 0x01
40
41#define NAND_CLE 0x02
42
43#define NAND_ALE 0x04
44
45#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
46#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
47#define NAND_CTRL_CHANGE 0x80
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51
52#define NAND_CMD_READ0 0
53#define NAND_CMD_READ1 1
54#define NAND_CMD_RNDOUT 5
55#define NAND_CMD_PAGEPROG 0x10
56#define NAND_CMD_READOOB 0x50
57#define NAND_CMD_ERASE1 0x60
58#define NAND_CMD_STATUS 0x70
59#define NAND_CMD_SEQIN 0x80
60#define NAND_CMD_RNDIN 0x85
61#define NAND_CMD_READID 0x90
62#define NAND_CMD_ERASE2 0xd0
63#define NAND_CMD_PARAM 0xec
64#define NAND_CMD_GET_FEATURES 0xee
65#define NAND_CMD_SET_FEATURES 0xef
66#define NAND_CMD_RESET 0xff
67
68
69#define NAND_CMD_READSTART 0x30
70#define NAND_CMD_RNDOUTSTART 0xE0
71#define NAND_CMD_CACHEDPROG 0x15
72
73#define NAND_CMD_NONE -1
74
75
76#define NAND_STATUS_FAIL 0x01
77#define NAND_STATUS_FAIL_N1 0x02
78#define NAND_STATUS_TRUE_READY 0x20
79#define NAND_STATUS_READY 0x40
80#define NAND_STATUS_WP 0x80
81
82#define NAND_DATA_IFACE_CHECK_ONLY -1
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88#define NAND_ECC_READ 0
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90#define NAND_ECC_WRITE 1
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92#define NAND_ECC_READSYN 2
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100#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
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108#define NAND_BUSWIDTH_16 BIT(1)
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114#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
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117#define NAND_CACHEPRG BIT(3)
118
119#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
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126#define NAND_NEED_READRDY BIT(8)
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129#define NAND_NO_SUBPAGE_WRITE BIT(9)
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132#define NAND_BROKEN_XD BIT(10)
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135#define NAND_ROM BIT(11)
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138#define NAND_SUBPAGE_READ BIT(12)
139
140#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
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146#define NAND_NEED_SCRAMBLING BIT(13)
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149#define NAND_ROW_ADDR_3 BIT(14)
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153#define NAND_SKIP_BBTSCAN BIT(16)
154
155#define NAND_SCAN_SILENT_NODEV BIT(18)
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163#define NAND_BUSWIDTH_AUTO BIT(19)
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169#define NAND_USES_DMA BIT(20)
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179#define NAND_WAIT_TCCS BIT(21)
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185#define NAND_IS_BOOT_MEDIUM BIT(22)
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192#define NAND_KEEP_TIMINGS BIT(23)
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201#define NAND_BBM_FIRSTPAGE BIT(24)
202#define NAND_BBM_SECONDPAGE BIT(25)
203#define NAND_BBM_LASTPAGE BIT(26)
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211#define NAND_NO_BBM_QUIRK BIT(27)
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214#define NAND_CI_CHIPNR_MSK 0x03
215#define NAND_CI_CELLTYPE_MSK 0x0C
216#define NAND_CI_CELLTYPE_SHIFT 2
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219#define NAND_BBM_POS_SMALL 5
220#define NAND_BBM_POS_LARGE 0
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229
230struct nand_parameters {
231
232 const char *model;
233 bool supports_set_get_features;
234 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
235 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
236
237
238 struct onfi_params *onfi;
239};
240
241
242#define NAND_MAX_ID_LEN 8
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249struct nand_id {
250 u8 data[NAND_MAX_ID_LEN];
251 int len;
252};
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260struct nand_ecc_step_info {
261 int stepsize;
262 const int *strengths;
263 int nstrengths;
264};
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272struct nand_ecc_caps {
273 const struct nand_ecc_step_info *stepinfos;
274 int nstepinfos;
275 int (*calc_ecc_bytes)(int step_size, int strength);
276};
277
278
279#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
280static const int __name##_strengths[] = { __VA_ARGS__ }; \
281static const struct nand_ecc_step_info __name##_stepinfo = { \
282 .stepsize = __step, \
283 .strengths = __name##_strengths, \
284 .nstrengths = ARRAY_SIZE(__name##_strengths), \
285}; \
286static const struct nand_ecc_caps __name = { \
287 .stepinfos = &__name##_stepinfo, \
288 .nstepinfos = 1, \
289 .calc_ecc_bytes = __calc, \
290}
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345struct nand_ecc_ctrl {
346 enum nand_ecc_engine_type engine_type;
347 enum nand_ecc_placement placement;
348 enum nand_ecc_algo algo;
349 int steps;
350 int size;
351 int bytes;
352 int total;
353 int strength;
354 int prepad;
355 int postpad;
356 unsigned int options;
357 u8 *calc_buf;
358 u8 *code_buf;
359 void (*hwctl)(struct nand_chip *chip, int mode);
360 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
361 uint8_t *ecc_code);
362 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
363 uint8_t *calc_ecc);
364 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
365 int oob_required, int page);
366 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
367 int oob_required, int page);
368 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
369 int oob_required, int page);
370 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
371 uint32_t len, uint8_t *buf, int page);
372 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
373 uint32_t data_len, const uint8_t *data_buf,
374 int oob_required, int page);
375 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
376 int oob_required, int page);
377 int (*write_oob_raw)(struct nand_chip *chip, int page);
378 int (*read_oob_raw)(struct nand_chip *chip, int page);
379 int (*read_oob)(struct nand_chip *chip, int page);
380 int (*write_oob)(struct nand_chip *chip, int page);
381};
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434struct nand_sdr_timings {
435 u64 tBERS_max;
436 u32 tCCS_min;
437 u64 tPROG_max;
438 u64 tR_max;
439 u32 tALH_min;
440 u32 tADL_min;
441 u32 tALS_min;
442 u32 tAR_min;
443 u32 tCEA_max;
444 u32 tCEH_min;
445 u32 tCH_min;
446 u32 tCHZ_max;
447 u32 tCLH_min;
448 u32 tCLR_min;
449 u32 tCLS_min;
450 u32 tCOH_min;
451 u32 tCS_min;
452 u32 tDH_min;
453 u32 tDS_min;
454 u32 tFEAT_max;
455 u32 tIR_min;
456 u32 tITC_max;
457 u32 tRC_min;
458 u32 tREA_max;
459 u32 tREH_min;
460 u32 tRHOH_min;
461 u32 tRHW_min;
462 u32 tRHZ_max;
463 u32 tRLOH_min;
464 u32 tRP_min;
465 u32 tRR_min;
466 u64 tRST_max;
467 u32 tWB_max;
468 u32 tWC_min;
469 u32 tWH_min;
470 u32 tWHR_min;
471 u32 tWP_min;
472 u32 tWW_min;
473};
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523struct nand_nvddr_timings {
524 u64 tBERS_max;
525 u32 tCCS_min;
526 u64 tPROG_max;
527 u64 tR_max;
528 u32 tAC_min;
529 u32 tAC_max;
530 u32 tADL_min;
531 u32 tCAD_min;
532 u32 tCAH_min;
533 u32 tCALH_min;
534 u32 tCALS_min;
535 u32 tCAS_min;
536 u32 tCEH_min;
537 u32 tCH_min;
538 u32 tCK_min;
539 u32 tCS_min;
540 u32 tDH_min;
541 u32 tDQSCK_min;
542 u32 tDQSCK_max;
543 u32 tDQSD_min;
544 u32 tDQSD_max;
545 u32 tDQSHZ_max;
546 u32 tDQSQ_max;
547 u32 tDS_min;
548 u32 tDSC_min;
549 u32 tFEAT_max;
550 u32 tITC_max;
551 u32 tQHS_max;
552 u32 tRHW_min;
553 u32 tRR_min;
554 u32 tRST_max;
555 u32 tWB_max;
556 u32 tWHR_min;
557 u32 tWRCK_min;
558 u32 tWW_min;
559};
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578#define NAND_COMMON_TIMING_PS(conf, timing_name) \
579 nand_interface_is_sdr(conf) ? \
580 nand_get_sdr_timings(conf)->timing_name : \
581 nand_get_nvddr_timings(conf)->timing_name
582
583#define NAND_COMMON_TIMING_MS(conf, timing_name) \
584 PSEC_TO_MSEC(NAND_COMMON_TIMING_PS((conf), timing_name))
585
586#define NAND_COMMON_TIMING_NS(conf, timing_name) \
587 PSEC_TO_NSEC(NAND_COMMON_TIMING_PS((conf), timing_name))
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594enum nand_interface_type {
595 NAND_SDR_IFACE,
596 NAND_NVDDR_IFACE,
597};
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607struct nand_interface_config {
608 enum nand_interface_type type;
609 struct nand_timings {
610 unsigned int mode;
611 union {
612 struct nand_sdr_timings sdr;
613 struct nand_nvddr_timings nvddr;
614 };
615 } timings;
616};
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622static bool nand_interface_is_sdr(const struct nand_interface_config *conf)
623{
624 return conf->type == NAND_SDR_IFACE;
625}
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631static bool nand_interface_is_nvddr(const struct nand_interface_config *conf)
632{
633 return conf->type == NAND_NVDDR_IFACE;
634}
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640static inline const struct nand_sdr_timings *
641nand_get_sdr_timings(const struct nand_interface_config *conf)
642{
643 if (!nand_interface_is_sdr(conf))
644 return ERR_PTR(-EINVAL);
645
646 return &conf->timings.sdr;
647}
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653static inline const struct nand_nvddr_timings *
654nand_get_nvddr_timings(const struct nand_interface_config *conf)
655{
656 if (!nand_interface_is_nvddr(conf))
657 return ERR_PTR(-EINVAL);
658
659 return &conf->timings.nvddr;
660}
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666struct nand_op_cmd_instr {
667 u8 opcode;
668};
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675struct nand_op_addr_instr {
676 unsigned int naddrs;
677 const u8 *addrs;
678};
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692struct nand_op_data_instr {
693 unsigned int len;
694 union {
695 void *in;
696 const void *out;
697 } buf;
698 bool force_8bit;
699};
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705struct nand_op_waitrdy_instr {
706 unsigned int timeout_ms;
707};
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717enum nand_op_instr_type {
718 NAND_OP_CMD_INSTR,
719 NAND_OP_ADDR_INSTR,
720 NAND_OP_DATA_IN_INSTR,
721 NAND_OP_DATA_OUT_INSTR,
722 NAND_OP_WAITRDY_INSTR,
723};
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740struct nand_op_instr {
741 enum nand_op_instr_type type;
742 union {
743 struct nand_op_cmd_instr cmd;
744 struct nand_op_addr_instr addr;
745 struct nand_op_data_instr data;
746 struct nand_op_waitrdy_instr waitrdy;
747 } ctx;
748 unsigned int delay_ns;
749};
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764#define __DIVIDE(dividend, divisor) ({ \
765 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
766 DIV_ROUND_UP(dividend, divisor) : \
767 DIV_ROUND_UP_ULL(dividend, divisor)); \
768 })
769#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
770#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
771
772#define NAND_OP_CMD(id, ns) \
773 { \
774 .type = NAND_OP_CMD_INSTR, \
775 .ctx.cmd.opcode = id, \
776 .delay_ns = ns, \
777 }
778
779#define NAND_OP_ADDR(ncycles, cycles, ns) \
780 { \
781 .type = NAND_OP_ADDR_INSTR, \
782 .ctx.addr = { \
783 .naddrs = ncycles, \
784 .addrs = cycles, \
785 }, \
786 .delay_ns = ns, \
787 }
788
789#define NAND_OP_DATA_IN(l, b, ns) \
790 { \
791 .type = NAND_OP_DATA_IN_INSTR, \
792 .ctx.data = { \
793 .len = l, \
794 .buf.in = b, \
795 .force_8bit = false, \
796 }, \
797 .delay_ns = ns, \
798 }
799
800#define NAND_OP_DATA_OUT(l, b, ns) \
801 { \
802 .type = NAND_OP_DATA_OUT_INSTR, \
803 .ctx.data = { \
804 .len = l, \
805 .buf.out = b, \
806 .force_8bit = false, \
807 }, \
808 .delay_ns = ns, \
809 }
810
811#define NAND_OP_8BIT_DATA_IN(l, b, ns) \
812 { \
813 .type = NAND_OP_DATA_IN_INSTR, \
814 .ctx.data = { \
815 .len = l, \
816 .buf.in = b, \
817 .force_8bit = true, \
818 }, \
819 .delay_ns = ns, \
820 }
821
822#define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
823 { \
824 .type = NAND_OP_DATA_OUT_INSTR, \
825 .ctx.data = { \
826 .len = l, \
827 .buf.out = b, \
828 .force_8bit = true, \
829 }, \
830 .delay_ns = ns, \
831 }
832
833#define NAND_OP_WAIT_RDY(tout_ms, ns) \
834 { \
835 .type = NAND_OP_WAITRDY_INSTR, \
836 .ctx.waitrdy.timeout_ms = tout_ms, \
837 .delay_ns = ns, \
838 }
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857struct nand_subop {
858 unsigned int cs;
859 const struct nand_op_instr *instrs;
860 unsigned int ninstrs;
861 unsigned int first_instr_start_off;
862 unsigned int last_instr_end_off;
863};
864
865unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
866 unsigned int op_id);
867unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
868 unsigned int op_id);
869unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
870 unsigned int op_id);
871unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
872 unsigned int op_id);
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879struct nand_op_parser_addr_constraints {
880 unsigned int maxcycles;
881};
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887struct nand_op_parser_data_constraints {
888 unsigned int maxlen;
889};
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899struct nand_op_parser_pattern_elem {
900 enum nand_op_instr_type type;
901 bool optional;
902 union {
903 struct nand_op_parser_addr_constraints addr;
904 struct nand_op_parser_data_constraints data;
905 } ctx;
906};
907
908#define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
909 { \
910 .type = NAND_OP_CMD_INSTR, \
911 .optional = _opt, \
912 }
913
914#define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
915 { \
916 .type = NAND_OP_ADDR_INSTR, \
917 .optional = _opt, \
918 .ctx.addr.maxcycles = _maxcycles, \
919 }
920
921#define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
922 { \
923 .type = NAND_OP_DATA_IN_INSTR, \
924 .optional = _opt, \
925 .ctx.data.maxlen = _maxlen, \
926 }
927
928#define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
929 { \
930 .type = NAND_OP_DATA_OUT_INSTR, \
931 .optional = _opt, \
932 .ctx.data.maxlen = _maxlen, \
933 }
934
935#define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
936 { \
937 .type = NAND_OP_WAITRDY_INSTR, \
938 .optional = _opt, \
939 }
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959struct nand_op_parser_pattern {
960 const struct nand_op_parser_pattern_elem *elems;
961 unsigned int nelems;
962 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
963};
964
965#define NAND_OP_PARSER_PATTERN(_exec, ...) \
966 { \
967 .exec = _exec, \
968 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
969 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
970 sizeof(struct nand_op_parser_pattern_elem), \
971 }
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987struct nand_op_parser {
988 const struct nand_op_parser_pattern *patterns;
989 unsigned int npatterns;
990};
991
992#define NAND_OP_PARSER(...) \
993 { \
994 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
995 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
996 sizeof(struct nand_op_parser_pattern), \
997 }
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1007struct nand_operation {
1008 unsigned int cs;
1009 const struct nand_op_instr *instrs;
1010 unsigned int ninstrs;
1011};
1012
1013#define NAND_OPERATION(_cs, _instrs) \
1014 { \
1015 .cs = _cs, \
1016 .instrs = _instrs, \
1017 .ninstrs = ARRAY_SIZE(_instrs), \
1018 }
1019
1020int nand_op_parser_exec_op(struct nand_chip *chip,
1021 const struct nand_op_parser *parser,
1022 const struct nand_operation *op, bool check_only);
1023
1024static inline void nand_op_trace(const char *prefix,
1025 const struct nand_op_instr *instr)
1026{
1027#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
1028 switch (instr->type) {
1029 case NAND_OP_CMD_INSTR:
1030 pr_debug("%sCMD [0x%02x]\n", prefix,
1031 instr->ctx.cmd.opcode);
1032 break;
1033 case NAND_OP_ADDR_INSTR:
1034 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
1035 instr->ctx.addr.naddrs,
1036 instr->ctx.addr.naddrs < 64 ?
1037 instr->ctx.addr.naddrs : 64,
1038 instr->ctx.addr.addrs);
1039 break;
1040 case NAND_OP_DATA_IN_INSTR:
1041 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
1042 instr->ctx.data.len,
1043 instr->ctx.data.force_8bit ?
1044 ", force 8-bit" : "");
1045 break;
1046 case NAND_OP_DATA_OUT_INSTR:
1047 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
1048 instr->ctx.data.len,
1049 instr->ctx.data.force_8bit ?
1050 ", force 8-bit" : "");
1051 break;
1052 case NAND_OP_WAITRDY_INSTR:
1053 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
1054 instr->ctx.waitrdy.timeout_ms);
1055 break;
1056 }
1057#endif
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
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1079
1080
1081
1082struct nand_controller_ops {
1083 int (*attach_chip)(struct nand_chip *chip);
1084 void (*detach_chip)(struct nand_chip *chip);
1085 int (*exec_op)(struct nand_chip *chip,
1086 const struct nand_operation *op,
1087 bool check_only);
1088 int (*setup_interface)(struct nand_chip *chip, int chipnr,
1089 const struct nand_interface_config *conf);
1090};
1091
1092
1093
1094
1095
1096
1097
1098struct nand_controller {
1099 struct mutex lock;
1100 const struct nand_controller_ops *ops;
1101};
1102
1103static inline void nand_controller_init(struct nand_controller *nfc)
1104{
1105 mutex_init(&nfc->lock);
1106}
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
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1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136struct nand_legacy {
1137 void __iomem *IO_ADDR_R;
1138 void __iomem *IO_ADDR_W;
1139 void (*select_chip)(struct nand_chip *chip, int cs);
1140 u8 (*read_byte)(struct nand_chip *chip);
1141 void (*write_byte)(struct nand_chip *chip, u8 byte);
1142 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1143 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1144 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1145 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1146 int page_addr);
1147 int (*dev_ready)(struct nand_chip *chip);
1148 int (*waitfunc)(struct nand_chip *chip);
1149 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1150 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1151 int (*set_features)(struct nand_chip *chip, int feature_addr,
1152 u8 *subfeature_para);
1153 int (*get_features)(struct nand_chip *chip, int feature_addr,
1154 u8 *subfeature_para);
1155 int chip_delay;
1156 struct nand_controller dummy_controller;
1157};
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168struct nand_chip_ops {
1169 int (*suspend)(struct nand_chip *chip);
1170 void (*resume)(struct nand_chip *chip);
1171 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1172 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1173 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1174 int (*choose_interface_config)(struct nand_chip *chip,
1175 struct nand_interface_config *iface);
1176};
1177
1178
1179
1180
1181
1182
1183struct nand_manufacturer {
1184 const struct nand_manufacturer_desc *desc;
1185 void *priv;
1186};
1187
1188
1189
1190
1191
1192
1193struct nand_secure_region {
1194 u64 offset;
1195 u64 size;
1196};
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
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1234
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1254
1255struct nand_chip {
1256 struct nand_device base;
1257 struct nand_id id;
1258 struct nand_parameters parameters;
1259 struct nand_manufacturer manufacturer;
1260 struct nand_chip_ops ops;
1261 struct nand_legacy legacy;
1262 unsigned int options;
1263
1264
1265 const struct nand_interface_config *current_interface_config;
1266 struct nand_interface_config *best_interface_config;
1267
1268
1269 unsigned int bbt_erase_shift;
1270 unsigned int bbt_options;
1271 unsigned int badblockpos;
1272 unsigned int badblockbits;
1273 struct nand_bbt_descr *bbt_td;
1274 struct nand_bbt_descr *bbt_md;
1275 struct nand_bbt_descr *badblock_pattern;
1276 u8 *bbt;
1277
1278
1279 unsigned int page_shift;
1280 unsigned int phys_erase_shift;
1281 unsigned int chip_shift;
1282 unsigned int pagemask;
1283 unsigned int subpagesize;
1284
1285
1286 u8 *data_buf;
1287 u8 *oob_poi;
1288 struct {
1289 unsigned int bitflips;
1290 int page;
1291 } pagecache;
1292 unsigned long buf_align;
1293
1294
1295 struct mutex lock;
1296 unsigned int suspended : 1;
1297 int cur_cs;
1298 int read_retries;
1299 struct nand_secure_region *secure_regions;
1300 u8 nr_secure_regions;
1301
1302
1303 struct nand_controller *controller;
1304 struct nand_ecc_ctrl ecc;
1305 void *priv;
1306};
1307
1308static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1309{
1310 return container_of(mtd, struct nand_chip, base.mtd);
1311}
1312
1313static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1314{
1315 return &chip->base.mtd;
1316}
1317
1318static inline void *nand_get_controller_data(struct nand_chip *chip)
1319{
1320 return chip->priv;
1321}
1322
1323static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1324{
1325 chip->priv = priv;
1326}
1327
1328static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1329 void *priv)
1330{
1331 chip->manufacturer.priv = priv;
1332}
1333
1334static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1335{
1336 return chip->manufacturer.priv;
1337}
1338
1339static inline void nand_set_flash_node(struct nand_chip *chip,
1340 struct device_node *np)
1341{
1342 mtd_set_of_node(nand_to_mtd(chip), np);
1343}
1344
1345static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1346{
1347 return mtd_get_of_node(nand_to_mtd(chip));
1348}
1349
1350
1351
1352
1353
1354
1355static inline const struct nand_interface_config *
1356nand_get_interface_config(struct nand_chip *chip)
1357{
1358 return chip->current_interface_config;
1359}
1360
1361
1362
1363
1364
1365
1366#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1367 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1368 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1381 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1382 .options = (opts) }
1383
1384#define NAND_ECC_INFO(_strength, _step) \
1385 { .strength_ds = (_strength), .step_ds = (_step) }
1386#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1387#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414struct nand_flash_dev {
1415 char *name;
1416 union {
1417 struct {
1418 uint8_t mfr_id;
1419 uint8_t dev_id;
1420 };
1421 uint8_t id[NAND_MAX_ID_LEN];
1422 };
1423 unsigned int pagesize;
1424 unsigned int chipsize;
1425 unsigned int erasesize;
1426 unsigned int options;
1427 uint16_t id_len;
1428 uint16_t oobsize;
1429 struct {
1430 uint16_t strength_ds;
1431 uint16_t step_ds;
1432 } ecc;
1433};
1434
1435int nand_create_bbt(struct nand_chip *chip);
1436
1437
1438
1439
1440
1441
1442static inline bool nand_is_slc(struct nand_chip *chip)
1443{
1444 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1445 "chip->bits_per_cell is used uninitialized\n");
1446 return nanddev_bits_per_cell(&chip->base) == 1;
1447}
1448
1449
1450
1451
1452
1453
1454static inline int nand_opcode_8bits(unsigned int command)
1455{
1456 switch (command) {
1457 case NAND_CMD_READID:
1458 case NAND_CMD_PARAM:
1459 case NAND_CMD_GET_FEATURES:
1460 case NAND_CMD_SET_FEATURES:
1461 return 1;
1462 default:
1463 break;
1464 }
1465 return 0;
1466}
1467
1468int rawnand_sw_hamming_init(struct nand_chip *chip);
1469int rawnand_sw_hamming_calculate(struct nand_chip *chip,
1470 const unsigned char *buf,
1471 unsigned char *code);
1472int rawnand_sw_hamming_correct(struct nand_chip *chip,
1473 unsigned char *buf,
1474 unsigned char *read_ecc,
1475 unsigned char *calc_ecc);
1476void rawnand_sw_hamming_cleanup(struct nand_chip *chip);
1477int rawnand_sw_bch_init(struct nand_chip *chip);
1478int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
1479 unsigned char *read_ecc, unsigned char *calc_ecc);
1480void rawnand_sw_bch_cleanup(struct nand_chip *chip);
1481
1482int nand_check_erased_ecc_chunk(void *data, int datalen,
1483 void *ecc, int ecclen,
1484 void *extraoob, int extraooblen,
1485 int threshold);
1486
1487int nand_ecc_choose_conf(struct nand_chip *chip,
1488 const struct nand_ecc_caps *caps, int oobavail);
1489
1490
1491int nand_write_oob_std(struct nand_chip *chip, int page);
1492
1493
1494int nand_read_oob_std(struct nand_chip *chip, int page);
1495
1496
1497int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1498 u8 *subfeature_param);
1499
1500
1501int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1502 int page);
1503int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1504 int oob_required, int page);
1505
1506
1507int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1508 int oob_required, int page);
1509int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1510 int oob_required, int page);
1511
1512
1513int nand_reset(struct nand_chip *chip, int chipnr);
1514
1515
1516int nand_reset_op(struct nand_chip *chip);
1517int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1518 unsigned int len);
1519int nand_status_op(struct nand_chip *chip, u8 *status);
1520int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1521int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1522 unsigned int offset_in_page, void *buf, unsigned int len);
1523int nand_change_read_column_op(struct nand_chip *chip,
1524 unsigned int offset_in_page, void *buf,
1525 unsigned int len, bool force_8bit);
1526int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1527 unsigned int offset_in_page, void *buf, unsigned int len);
1528int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1529 unsigned int offset_in_page, const void *buf,
1530 unsigned int len);
1531int nand_prog_page_end_op(struct nand_chip *chip);
1532int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1533 unsigned int offset_in_page, const void *buf,
1534 unsigned int len);
1535int nand_change_write_column_op(struct nand_chip *chip,
1536 unsigned int offset_in_page, const void *buf,
1537 unsigned int len, bool force_8bit);
1538int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1539 bool force_8bit, bool check_only);
1540int nand_write_data_op(struct nand_chip *chip, const void *buf,
1541 unsigned int len, bool force_8bit);
1542
1543
1544int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1545 struct nand_flash_dev *ids);
1546
1547static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1548{
1549 return nand_scan_with_ids(chip, max_chips, NULL);
1550}
1551
1552
1553void nand_wait_ready(struct nand_chip *chip);
1554
1555
1556
1557
1558
1559void nand_cleanup(struct nand_chip *chip);
1560
1561
1562
1563
1564
1565int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1566int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1567 unsigned long timeout_ms);
1568
1569
1570void nand_select_target(struct nand_chip *chip, unsigned int cs);
1571void nand_deselect_target(struct nand_chip *chip);
1572
1573
1574void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1575 unsigned int src_off, unsigned int nbits);
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591static inline void *nand_get_data_buf(struct nand_chip *chip)
1592{
1593 chip->pagecache.page = -1;
1594
1595 return chip->data_buf;
1596}
1597
1598
1599int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array,
1600 unsigned int *ncs_array);
1601
1602#endif
1603