linux/include/linux/mtd/spi-nor.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef __LINUX_MTD_SPI_NOR_H
   7#define __LINUX_MTD_SPI_NOR_H
   8
   9#include <linux/bitops.h>
  10#include <linux/mtd/cfi.h>
  11#include <linux/mtd/mtd.h>
  12#include <linux/spi/spi-mem.h>
  13
  14/*
  15 * Manufacturer IDs
  16 *
  17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  19 */
  20#define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
  21#define SNOR_MFR_GIGADEVICE     0xc8
  22#define SNOR_MFR_INTEL          CFI_MFR_INTEL
  23#define SNOR_MFR_ST             CFI_MFR_ST      /* ST Micro */
  24#define SNOR_MFR_MICRON         CFI_MFR_MICRON  /* Micron */
  25#define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
  26#define SNOR_MFR_SPANSION       CFI_MFR_AMD
  27#define SNOR_MFR_SST            CFI_MFR_SST
  28#define SNOR_MFR_WINBOND        0xef /* Also used by some Spansion */
  29
  30/*
  31 * Note on opcode nomenclature: some opcodes have a format like
  32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  33 * of I/O lines used for the opcode, address, and data (respectively). The
  34 * FUNCTION has an optional suffix of '4', to represent an opcode which
  35 * requires a 4-byte (32-bit) address.
  36 */
  37
  38/* Flash opcodes. */
  39#define SPINOR_OP_WREN          0x06    /* Write enable */
  40#define SPINOR_OP_RDSR          0x05    /* Read status register */
  41#define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
  42#define SPINOR_OP_RDSR2         0x3f    /* Read status register 2 */
  43#define SPINOR_OP_WRSR2         0x3e    /* Write status register 2 */
  44#define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
  45#define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
  46#define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
  47#define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
  48#define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
  49#define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
  50#define SPINOR_OP_READ_1_1_8    0x8b    /* Read data bytes (Octal Output SPI) */
  51#define SPINOR_OP_READ_1_8_8    0xcb    /* Read data bytes (Octal I/O SPI) */
  52#define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
  53#define SPINOR_OP_PP_1_1_4      0x32    /* Quad page program */
  54#define SPINOR_OP_PP_1_4_4      0x38    /* Quad page program */
  55#define SPINOR_OP_PP_1_1_8      0x82    /* Octal page program */
  56#define SPINOR_OP_PP_1_8_8      0xc2    /* Octal page program */
  57#define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
  58#define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
  59#define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
  60#define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
  61#define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
  62#define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
  63#define SPINOR_OP_RDSFDP        0x5a    /* Read SFDP */
  64#define SPINOR_OP_RDCR          0x35    /* Read configuration register */
  65#define SPINOR_OP_RDFSR         0x70    /* Read flag status register */
  66#define SPINOR_OP_CLFSR         0x50    /* Clear flag status register */
  67#define SPINOR_OP_RDEAR         0xc8    /* Read Extended Address Register */
  68#define SPINOR_OP_WREAR         0xc5    /* Write Extended Address Register */
  69
  70/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  71#define SPINOR_OP_READ_4B       0x13    /* Read data bytes (low frequency) */
  72#define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
  73#define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
  74#define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
  75#define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
  76#define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
  77#define SPINOR_OP_READ_1_1_8_4B 0x7c    /* Read data bytes (Octal Output SPI) */
  78#define SPINOR_OP_READ_1_8_8_4B 0xcc    /* Read data bytes (Octal I/O SPI) */
  79#define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
  80#define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
  81#define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
  82#define SPINOR_OP_PP_1_1_8_4B   0x84    /* Octal page program */
  83#define SPINOR_OP_PP_1_8_8_4B   0x8e    /* Octal page program */
  84#define SPINOR_OP_BE_4K_4B      0x21    /* Erase 4KiB block */
  85#define SPINOR_OP_BE_32K_4B     0x5c    /* Erase 32KiB block */
  86#define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
  87
  88/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  89#define SPINOR_OP_READ_1_1_1_DTR        0x0d
  90#define SPINOR_OP_READ_1_2_2_DTR        0xbd
  91#define SPINOR_OP_READ_1_4_4_DTR        0xed
  92
  93#define SPINOR_OP_READ_1_1_1_DTR_4B     0x0e
  94#define SPINOR_OP_READ_1_2_2_DTR_4B     0xbe
  95#define SPINOR_OP_READ_1_4_4_DTR_4B     0xee
  96
  97/* Used for SST flashes only. */
  98#define SPINOR_OP_BP            0x02    /* Byte program */
  99#define SPINOR_OP_WRDI          0x04    /* Write disable */
 100#define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
 101
 102/* Used for S3AN flashes only */
 103#define SPINOR_OP_XSE           0x50    /* Sector erase */
 104#define SPINOR_OP_XPP           0x82    /* Page program */
 105#define SPINOR_OP_XRDSR         0xd7    /* Read status register */
 106
 107#define XSR_PAGESIZE            BIT(0)  /* Page size in Po2 or Linear */
 108#define XSR_RDY                 BIT(7)  /* Ready */
 109
 110
 111/* Used for Macronix and Winbond flashes. */
 112#define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
 113#define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
 114
 115/* Used for Spansion flashes only. */
 116#define SPINOR_OP_BRWR          0x17    /* Bank register write */
 117#define SPINOR_OP_CLSR          0x30    /* Clear status register 1 */
 118
 119/* Used for Micron flashes only. */
 120#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 121#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 122
 123/* Status Register bits. */
 124#define SR_WIP                  BIT(0)  /* Write in progress */
 125#define SR_WEL                  BIT(1)  /* Write enable latch */
 126/* meaning of other SR_* bits may differ between vendors */
 127#define SR_BP0                  BIT(2)  /* Block protect 0 */
 128#define SR_BP1                  BIT(3)  /* Block protect 1 */
 129#define SR_BP2                  BIT(4)  /* Block protect 2 */
 130#define SR_TB                   BIT(5)  /* Top/Bottom protect */
 131#define SR_SRWD                 BIT(7)  /* SR write protect */
 132/* Spansion/Cypress specific status bits */
 133#define SR_E_ERR                BIT(5)
 134#define SR_P_ERR                BIT(6)
 135
 136#define SR_QUAD_EN_MX           BIT(6)  /* Macronix Quad I/O */
 137
 138/* Enhanced Volatile Configuration Register bits */
 139#define EVCR_QUAD_EN_MICRON     BIT(7)  /* Micron Quad I/O */
 140
 141/* Flag Status Register bits */
 142#define FSR_READY               BIT(7)  /* Device status, 0 = Busy, 1 = Ready */
 143#define FSR_E_ERR               BIT(5)  /* Erase operation status */
 144#define FSR_P_ERR               BIT(4)  /* Program operation status */
 145#define FSR_PT_ERR              BIT(1)  /* Protection error bit */
 146
 147/* Configuration Register bits. */
 148#define CR_QUAD_EN_SPAN         BIT(1)  /* Spansion Quad I/O */
 149
 150/* Status Register 2 bits. */
 151#define SR2_QUAD_EN_BIT7        BIT(7)
 152
 153/* Supported SPI protocols */
 154#define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
 155#define SNOR_PROTO_INST_SHIFT   16
 156#define SNOR_PROTO_INST(_nbits) \
 157        ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
 158         SNOR_PROTO_INST_MASK)
 159
 160#define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
 161#define SNOR_PROTO_ADDR_SHIFT   8
 162#define SNOR_PROTO_ADDR(_nbits) \
 163        ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
 164         SNOR_PROTO_ADDR_MASK)
 165
 166#define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
 167#define SNOR_PROTO_DATA_SHIFT   0
 168#define SNOR_PROTO_DATA(_nbits) \
 169        ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
 170         SNOR_PROTO_DATA_MASK)
 171
 172#define SNOR_PROTO_IS_DTR       BIT(24) /* Double Transfer Rate */
 173
 174#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
 175        (SNOR_PROTO_INST(_inst_nbits) |                         \
 176         SNOR_PROTO_ADDR(_addr_nbits) |                         \
 177         SNOR_PROTO_DATA(_data_nbits))
 178#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
 179        (SNOR_PROTO_IS_DTR |                                    \
 180         SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
 181
 182enum spi_nor_protocol {
 183        SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
 184        SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
 185        SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
 186        SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
 187        SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
 188        SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
 189        SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
 190        SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
 191        SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
 192        SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
 193
 194        SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
 195        SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
 196        SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
 197        SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
 198};
 199
 200static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
 201{
 202        return !!(proto & SNOR_PROTO_IS_DTR);
 203}
 204
 205static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
 206{
 207        return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
 208                SNOR_PROTO_INST_SHIFT;
 209}
 210
 211static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
 212{
 213        return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
 214                SNOR_PROTO_ADDR_SHIFT;
 215}
 216
 217static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
 218{
 219        return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
 220                SNOR_PROTO_DATA_SHIFT;
 221}
 222
 223static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
 224{
 225        return spi_nor_get_protocol_data_nbits(proto);
 226}
 227
 228enum spi_nor_ops {
 229        SPI_NOR_OPS_READ = 0,
 230        SPI_NOR_OPS_WRITE,
 231        SPI_NOR_OPS_ERASE,
 232        SPI_NOR_OPS_LOCK,
 233        SPI_NOR_OPS_UNLOCK,
 234};
 235
 236enum spi_nor_option_flags {
 237        SNOR_F_USE_FSR          = BIT(0),
 238        SNOR_F_HAS_SR_TB        = BIT(1),
 239        SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
 240        SNOR_F_READY_XSR_RDY    = BIT(3),
 241        SNOR_F_USE_CLSR         = BIT(4),
 242        SNOR_F_BROKEN_RESET     = BIT(5),
 243        SNOR_F_4B_OPCODES       = BIT(6),
 244        SNOR_F_HAS_4BAIT        = BIT(7),
 245        SNOR_F_HAS_LOCK         = BIT(8),
 246};
 247
 248/**
 249 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
 250 * @size:               the size of the sector/block erased by the erase type.
 251 *                      JEDEC JESD216B imposes erase sizes to be a power of 2.
 252 * @size_shift:         @size is a power of 2, the shift is stored in
 253 *                      @size_shift.
 254 * @size_mask:          the size mask based on @size_shift.
 255 * @opcode:             the SPI command op code to erase the sector/block.
 256 * @idx:                Erase Type index as sorted in the Basic Flash Parameter
 257 *                      Table. It will be used to synchronize the supported
 258 *                      Erase Types with the ones identified in the SFDP
 259 *                      optional tables.
 260 */
 261struct spi_nor_erase_type {
 262        u32     size;
 263        u32     size_shift;
 264        u32     size_mask;
 265        u8      opcode;
 266        u8      idx;
 267};
 268
 269/**
 270 * struct spi_nor_erase_command - Used for non-uniform erases
 271 * The structure is used to describe a list of erase commands to be executed
 272 * once we validate that the erase can be performed. The elements in the list
 273 * are run-length encoded.
 274 * @list:               for inclusion into the list of erase commands.
 275 * @count:              how many times the same erase command should be
 276 *                      consecutively used.
 277 * @size:               the size of the sector/block erased by the command.
 278 * @opcode:             the SPI command op code to erase the sector/block.
 279 */
 280struct spi_nor_erase_command {
 281        struct list_head        list;
 282        u32                     count;
 283        u32                     size;
 284        u8                      opcode;
 285};
 286
 287/**
 288 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
 289 * @offset:             the offset in the data array of erase region start.
 290 *                      LSB bits are used as a bitmask encoding flags to
 291 *                      determine if this region is overlaid, if this region is
 292 *                      the last in the SPI NOR flash memory and to indicate
 293 *                      all the supported erase commands inside this region.
 294 *                      The erase types are sorted in ascending order with the
 295 *                      smallest Erase Type size being at BIT(0).
 296 * @size:               the size of the region in bytes.
 297 */
 298struct spi_nor_erase_region {
 299        u64             offset;
 300        u64             size;
 301};
 302
 303#define SNOR_ERASE_TYPE_MAX     4
 304#define SNOR_ERASE_TYPE_MASK    GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
 305
 306#define SNOR_LAST_REGION        BIT(4)
 307#define SNOR_OVERLAID_REGION    BIT(5)
 308
 309#define SNOR_ERASE_FLAGS_MAX    6
 310#define SNOR_ERASE_FLAGS_MASK   GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
 311
 312/**
 313 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
 314 * @regions:            array of erase regions. The regions are consecutive in
 315 *                      address space. Walking through the regions is done
 316 *                      incrementally.
 317 * @uniform_region:     a pre-allocated erase region for SPI NOR with a uniform
 318 *                      sector size (legacy implementation).
 319 * @erase_type:         an array of erase types shared by all the regions.
 320 *                      The erase types are sorted in ascending order, with the
 321 *                      smallest Erase Type size being the first member in the
 322 *                      erase_type array.
 323 * @uniform_erase_type: bitmask encoding erase types that can erase the
 324 *                      entire memory. This member is completed at init by
 325 *                      uniform and non-uniform SPI NOR flash memories if they
 326 *                      support at least one erase type that can erase the
 327 *                      entire memory.
 328 */
 329struct spi_nor_erase_map {
 330        struct spi_nor_erase_region     *regions;
 331        struct spi_nor_erase_region     uniform_region;
 332        struct spi_nor_erase_type       erase_type[SNOR_ERASE_TYPE_MAX];
 333        u8                              uniform_erase_type;
 334};
 335
 336/**
 337 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 338 * supported by the SPI controller (bus master).
 339 * @mask:               the bitmask listing all the supported hw capabilies
 340 */
 341struct spi_nor_hwcaps {
 342        u32     mask;
 343};
 344
 345/*
 346 *(Fast) Read capabilities.
 347 * MUST be ordered by priority: the higher bit position, the higher priority.
 348 * As a matter of performances, it is relevant to use Octal SPI protocols first,
 349 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 350 * (Slow) Read.
 351 */
 352#define SNOR_HWCAPS_READ_MASK           GENMASK(14, 0)
 353#define SNOR_HWCAPS_READ                BIT(0)
 354#define SNOR_HWCAPS_READ_FAST           BIT(1)
 355#define SNOR_HWCAPS_READ_1_1_1_DTR      BIT(2)
 356
 357#define SNOR_HWCAPS_READ_DUAL           GENMASK(6, 3)
 358#define SNOR_HWCAPS_READ_1_1_2          BIT(3)
 359#define SNOR_HWCAPS_READ_1_2_2          BIT(4)
 360#define SNOR_HWCAPS_READ_2_2_2          BIT(5)
 361#define SNOR_HWCAPS_READ_1_2_2_DTR      BIT(6)
 362
 363#define SNOR_HWCAPS_READ_QUAD           GENMASK(10, 7)
 364#define SNOR_HWCAPS_READ_1_1_4          BIT(7)
 365#define SNOR_HWCAPS_READ_1_4_4          BIT(8)
 366#define SNOR_HWCAPS_READ_4_4_4          BIT(9)
 367#define SNOR_HWCAPS_READ_1_4_4_DTR      BIT(10)
 368
 369#define SNOR_HWCAPS_READ_OCTAL          GENMASK(14, 11)
 370#define SNOR_HWCAPS_READ_1_1_8          BIT(11)
 371#define SNOR_HWCAPS_READ_1_8_8          BIT(12)
 372#define SNOR_HWCAPS_READ_8_8_8          BIT(13)
 373#define SNOR_HWCAPS_READ_1_8_8_DTR      BIT(14)
 374
 375/*
 376 * Page Program capabilities.
 377 * MUST be ordered by priority: the higher bit position, the higher priority.
 378 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
 379 * legacy SPI 1-1-1 protocol.
 380 * Note that Dual Page Programs are not supported because there is no existing
 381 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 382 * implements such commands.
 383 */
 384#define SNOR_HWCAPS_PP_MASK     GENMASK(22, 16)
 385#define SNOR_HWCAPS_PP          BIT(16)
 386
 387#define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
 388#define SNOR_HWCAPS_PP_1_1_4    BIT(17)
 389#define SNOR_HWCAPS_PP_1_4_4    BIT(18)
 390#define SNOR_HWCAPS_PP_4_4_4    BIT(19)
 391
 392#define SNOR_HWCAPS_PP_OCTAL    GENMASK(22, 20)
 393#define SNOR_HWCAPS_PP_1_1_8    BIT(20)
 394#define SNOR_HWCAPS_PP_1_8_8    BIT(21)
 395#define SNOR_HWCAPS_PP_8_8_8    BIT(22)
 396
 397#define SNOR_HWCAPS_X_X_X       (SNOR_HWCAPS_READ_2_2_2 |       \
 398                                 SNOR_HWCAPS_READ_4_4_4 |       \
 399                                 SNOR_HWCAPS_READ_8_8_8 |       \
 400                                 SNOR_HWCAPS_PP_4_4_4 |         \
 401                                 SNOR_HWCAPS_PP_8_8_8)
 402
 403#define SNOR_HWCAPS_DTR         (SNOR_HWCAPS_READ_1_1_1_DTR |   \
 404                                 SNOR_HWCAPS_READ_1_2_2_DTR |   \
 405                                 SNOR_HWCAPS_READ_1_4_4_DTR |   \
 406                                 SNOR_HWCAPS_READ_1_8_8_DTR)
 407
 408#define SNOR_HWCAPS_ALL         (SNOR_HWCAPS_READ_MASK |        \
 409                                 SNOR_HWCAPS_PP_MASK)
 410
 411struct spi_nor_read_command {
 412        u8                      num_mode_clocks;
 413        u8                      num_wait_states;
 414        u8                      opcode;
 415        enum spi_nor_protocol   proto;
 416};
 417
 418struct spi_nor_pp_command {
 419        u8                      opcode;
 420        enum spi_nor_protocol   proto;
 421};
 422
 423enum spi_nor_read_command_index {
 424        SNOR_CMD_READ,
 425        SNOR_CMD_READ_FAST,
 426        SNOR_CMD_READ_1_1_1_DTR,
 427
 428        /* Dual SPI */
 429        SNOR_CMD_READ_1_1_2,
 430        SNOR_CMD_READ_1_2_2,
 431        SNOR_CMD_READ_2_2_2,
 432        SNOR_CMD_READ_1_2_2_DTR,
 433
 434        /* Quad SPI */
 435        SNOR_CMD_READ_1_1_4,
 436        SNOR_CMD_READ_1_4_4,
 437        SNOR_CMD_READ_4_4_4,
 438        SNOR_CMD_READ_1_4_4_DTR,
 439
 440        /* Octal SPI */
 441        SNOR_CMD_READ_1_1_8,
 442        SNOR_CMD_READ_1_8_8,
 443        SNOR_CMD_READ_8_8_8,
 444        SNOR_CMD_READ_1_8_8_DTR,
 445
 446        SNOR_CMD_READ_MAX
 447};
 448
 449enum spi_nor_pp_command_index {
 450        SNOR_CMD_PP,
 451
 452        /* Quad SPI */
 453        SNOR_CMD_PP_1_1_4,
 454        SNOR_CMD_PP_1_4_4,
 455        SNOR_CMD_PP_4_4_4,
 456
 457        /* Octal SPI */
 458        SNOR_CMD_PP_1_1_8,
 459        SNOR_CMD_PP_1_8_8,
 460        SNOR_CMD_PP_8_8_8,
 461
 462        SNOR_CMD_PP_MAX
 463};
 464
 465/* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */
 466struct spi_nor;
 467
 468/**
 469 * struct spi_nor_locking_ops - SPI NOR locking methods
 470 * @lock:       lock a region of the SPI NOR.
 471 * @unlock:     unlock a region of the SPI NOR.
 472 * @is_locked:  check if a region of the SPI NOR is completely locked
 473 */
 474struct spi_nor_locking_ops {
 475        int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 476        int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 477        int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 478};
 479
 480/**
 481 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
 482 * Includes legacy flash parameters and settings that can be overwritten
 483 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
 484 * Serial Flash Discoverable Parameters (SFDP) tables.
 485 *
 486 * @size:               the flash memory density in bytes.
 487 * @page_size:          the page size of the SPI NOR flash memory.
 488 * @hwcaps:             describes the read and page program hardware
 489 *                      capabilities.
 490 * @reads:              read capabilities ordered by priority: the higher index
 491 *                      in the array, the higher priority.
 492 * @page_programs:      page program capabilities ordered by priority: the
 493 *                      higher index in the array, the higher priority.
 494 * @erase_map:          the erase map parsed from the SFDP Sector Map Parameter
 495 *                      Table.
 496 * @quad_enable:        enables SPI NOR quad mode.
 497 * @set_4byte:          puts the SPI NOR in 4 byte addressing mode.
 498 * @convert_addr:       converts an absolute address into something the flash
 499 *                      will understand. Particularly useful when pagesize is
 500 *                      not a power-of-2.
 501 * @setup:              configures the SPI NOR memory. Useful for SPI NOR
 502 *                      flashes that have peculiarities to the SPI NOR standard
 503 *                      e.g. different opcodes, specific address calculation,
 504 *                      page size, etc.
 505 * @locking_ops:        SPI NOR locking methods.
 506 */
 507struct spi_nor_flash_parameter {
 508        u64                             size;
 509        u32                             page_size;
 510
 511        struct spi_nor_hwcaps           hwcaps;
 512        struct spi_nor_read_command     reads[SNOR_CMD_READ_MAX];
 513        struct spi_nor_pp_command       page_programs[SNOR_CMD_PP_MAX];
 514
 515        struct spi_nor_erase_map        erase_map;
 516
 517        int (*quad_enable)(struct spi_nor *nor);
 518        int (*set_4byte)(struct spi_nor *nor, bool enable);
 519        u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
 520        int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
 521
 522        const struct spi_nor_locking_ops *locking_ops;
 523};
 524
 525/**
 526 * struct flash_info - Forward declaration of a structure used internally by
 527 *                     spi_nor_scan()
 528 */
 529struct flash_info;
 530
 531/**
 532 * struct spi_nor - Structure for defining a the SPI NOR layer
 533 * @mtd:                point to a mtd_info structure
 534 * @lock:               the lock for the read/write/erase/lock/unlock operations
 535 * @dev:                point to a spi device, or a spi nor controller device.
 536 * @spimem:             point to the spi mem device
 537 * @bouncebuf:          bounce buffer used when the buffer passed by the MTD
 538 *                      layer is not DMA-able
 539 * @bouncebuf_size:     size of the bounce buffer
 540 * @info:               spi-nor part JDEC MFR id and other info
 541 * @page_size:          the page size of the SPI NOR
 542 * @addr_width:         number of address bytes
 543 * @erase_opcode:       the opcode for erasing a sector
 544 * @read_opcode:        the read opcode
 545 * @read_dummy:         the dummy needed by the read operation
 546 * @program_opcode:     the program opcode
 547 * @sst_write_second:   used by the SST write operation
 548 * @flags:              flag options for the current SPI-NOR (SNOR_F_*)
 549 * @read_proto:         the SPI protocol for read operations
 550 * @write_proto:        the SPI protocol for write operations
 551 * @reg_proto           the SPI protocol for read_reg/write_reg/erase operations
 552 * @prepare:            [OPTIONAL] do some preparations for the
 553 *                      read/write/erase/lock/unlock operations
 554 * @unprepare:          [OPTIONAL] do some post work after the
 555 *                      read/write/erase/lock/unlock operations
 556 * @read_reg:           [DRIVER-SPECIFIC] read out the register
 557 * @write_reg:          [DRIVER-SPECIFIC] write data to the register
 558 * @read:               [DRIVER-SPECIFIC] read data from the SPI NOR
 559 * @write:              [DRIVER-SPECIFIC] write data to the SPI NOR
 560 * @erase:              [DRIVER-SPECIFIC] erase a sector of the SPI NOR
 561 *                      at the offset @offs; if not provided by the driver,
 562 *                      spi-nor will send the erase opcode via write_reg()
 563 * @clear_sr_bp:        [FLASH-SPECIFIC] clears the Block Protection Bits from
 564 *                      the SPI NOR Status Register.
 565 * @params:             [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
 566 *                      The structure includes legacy flash parameters and
 567 *                      settings that can be overwritten by the spi_nor_fixups
 568 *                      hooks, or dynamically when parsing the SFDP tables.
 569 * @priv:               the private data
 570 */
 571struct spi_nor {
 572        struct mtd_info         mtd;
 573        struct mutex            lock;
 574        struct device           *dev;
 575        struct spi_mem          *spimem;
 576        u8                      *bouncebuf;
 577        size_t                  bouncebuf_size;
 578        const struct flash_info *info;
 579        u32                     page_size;
 580        u8                      addr_width;
 581        u8                      erase_opcode;
 582        u8                      read_opcode;
 583        u8                      read_dummy;
 584        u8                      program_opcode;
 585        enum spi_nor_protocol   read_proto;
 586        enum spi_nor_protocol   write_proto;
 587        enum spi_nor_protocol   reg_proto;
 588        bool                    sst_write_second;
 589        u32                     flags;
 590
 591        int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 592        void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 593        int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 594        int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 595
 596        ssize_t (*read)(struct spi_nor *nor, loff_t from,
 597                        size_t len, u_char *read_buf);
 598        ssize_t (*write)(struct spi_nor *nor, loff_t to,
 599                        size_t len, const u_char *write_buf);
 600        int (*erase)(struct spi_nor *nor, loff_t offs);
 601
 602        int (*clear_sr_bp)(struct spi_nor *nor);
 603        struct spi_nor_flash_parameter params;
 604
 605        void *priv;
 606};
 607
 608static u64 __maybe_unused
 609spi_nor_region_is_last(const struct spi_nor_erase_region *region)
 610{
 611        return region->offset & SNOR_LAST_REGION;
 612}
 613
 614static u64 __maybe_unused
 615spi_nor_region_end(const struct spi_nor_erase_region *region)
 616{
 617        return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
 618}
 619
 620static void __maybe_unused
 621spi_nor_region_mark_end(struct spi_nor_erase_region *region)
 622{
 623        region->offset |= SNOR_LAST_REGION;
 624}
 625
 626static void __maybe_unused
 627spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
 628{
 629        region->offset |= SNOR_OVERLAID_REGION;
 630}
 631
 632static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
 633{
 634        return !!nor->params.erase_map.uniform_erase_type;
 635}
 636
 637static inline void spi_nor_set_flash_node(struct spi_nor *nor,
 638                                          struct device_node *np)
 639{
 640        mtd_set_of_node(&nor->mtd, np);
 641}
 642
 643static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
 644{
 645        return mtd_get_of_node(&nor->mtd);
 646}
 647
 648/**
 649 * spi_nor_scan() - scan the SPI NOR
 650 * @nor:        the spi_nor structure
 651 * @name:       the chip type name
 652 * @hwcaps:     the hardware capabilities supported by the controller driver
 653 *
 654 * The drivers can use this fuction to scan the SPI NOR.
 655 * In the scanning, it will try to get all the necessary information to
 656 * fill the mtd_info{} and the spi_nor{}.
 657 *
 658 * The chip type name can be provided through the @name parameter.
 659 *
 660 * Return: 0 for success, others for failure.
 661 */
 662int spi_nor_scan(struct spi_nor *nor, const char *name,
 663                 const struct spi_nor_hwcaps *hwcaps);
 664
 665/**
 666 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
 667 * @nor:        the spi_nor structure
 668 */
 669void spi_nor_restore(struct spi_nor *nor);
 670
 671#endif
 672