LXR linux/include/linux/platform

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Driver for the Synopsys DesignWare DMA Controller
   4 *
   5 * Copyright (C) 2007 Atmel Corporation
   6 * Copyright (C) 2010-2011 ST Microelectronics
   7 */
   8#ifndef _PLATFORM_DATA_DMA_DW_H
   9#define _PLATFORM_DATA_DMA_DW_H
  10
  11#include <linux/bits.h>
  12#include <linux/types.h>
  13
  14#define DW_DMA_MAX_NR_MASTERS   4
  15#define DW_DMA_MAX_NR_CHANNELS  8
  16#define DW_DMA_MIN_BURST        1
  17#define DW_DMA_MAX_BURST        256
  18
  19struct device;
  20
  21/**
  22 * struct dw_dma_slave - Controller-specific information about a slave
  23 *
  24 * @dma_dev:    required DMA master device
  25 * @src_id:     src request line
  26 * @dst_id:     dst request line
  27 * @m_master:   memory master for transfers on allocated channel
  28 * @p_master:   peripheral master for transfers on allocated channel
  29 * @channels:   mask of the channels permitted for allocation (zero value means any)
  30 * @hs_polarity:set active low polarity of handshake interface
  31 */
  32struct dw_dma_slave {
  33        struct device           *dma_dev;
  34        u8                      src_id;
  35        u8                      dst_id;
  36        u8                      m_master;
  37        u8                      p_master;
  38        u8                      channels;
  39        bool                    hs_polarity;
  40};
  41
  42/**
  43 * struct dw_dma_platform_data - Controller configuration parameters
  44 * @nr_masters: Number of AHB masters supported by the controller
  45 * @nr_channels: Number of channels supported by hardware (max 8)
  46 * @chan_allocation_order: Allocate channels starting from 0 or 7
  47 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  48 * @block_size: Maximum block size supported by the controller
  49 * @data_width: Maximum data width supported by hardware per AHB master
  50 *              (in bytes, power of 2)
  51 * @multi_block: Multi block transfers supported by hardware per channel.
  52 * @max_burst: Maximum value of burst transaction size supported by hardware
  53 *             per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
  54 * @protctl: Protection control signals setting per channel.
  55 * @quirks: Optional platform quirks.
  56 */
  57struct dw_dma_platform_data {
  58        u32             nr_masters;
  59        u32             nr_channels;
  60#define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
  61#define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
  62        u32             chan_allocation_order;
  63#define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
  64#define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
  65        u32             chan_priority;
  66        u32             block_size;
  67        u32             data_width[DW_DMA_MAX_NR_MASTERS];
  68        u32             multi_block[DW_DMA_MAX_NR_CHANNELS];
  69        u32             max_burst[DW_DMA_MAX_NR_CHANNELS];
  70#define CHAN_PROTCTL_PRIVILEGED         BIT(0)
  71#define CHAN_PROTCTL_BUFFERABLE         BIT(1)
  72#define CHAN_PROTCTL_CACHEABLE          BIT(2)
  73#define CHAN_PROTCTL_MASK               GENMASK(2, 0)
  74        u32             protctl;
  75#define DW_DMA_QUIRK_XBAR_PRESENT       BIT(0)
  76        u32             quirks;
  77};
  78
  79#endif /* _PLATFORM_DATA_DMA_DW_H */
  80