LXR linux/include/linux/platform

   1/*
   2 * usb-omap.h - Platform data for the various OMAP USB IPs
   3 *
   4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com
   5 *
   6 * This software is distributed under the terms of the GNU General Public
   7 * License ("GPL") version 2, as published by the Free Software Foundation.
   8 *
   9 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  10 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  11 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  12 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  13 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  14 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  15 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  16 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  17 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  18 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  19 * POSSIBILITY OF SUCH DAMAGE.
  20 */
  21
  22#define OMAP3_HS_USB_PORTS      3
  23
  24enum usbhs_omap_port_mode {
  25        OMAP_USBHS_PORT_MODE_UNUSED,
  26        OMAP_EHCI_PORT_MODE_PHY,
  27        OMAP_EHCI_PORT_MODE_TLL,
  28        OMAP_EHCI_PORT_MODE_HSIC,
  29        OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
  30        OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
  31        OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
  32        OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
  33        OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
  34        OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
  35        OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
  36        OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
  37        OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
  38        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
  39};
  40
  41struct usbtll_omap_platform_data {
  42        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
  43};
  44
  45struct ehci_hcd_omap_platform_data {
  46        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  47        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
  48        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
  49        unsigned                        phy_reset:1;
  50};
  51
  52struct ohci_hcd_omap_platform_data {
  53        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  54        unsigned                        es2_compatibility:1;
  55};
  56
  57struct usbhs_omap_platform_data {
  58        int                             nports;
  59        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  60        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
  61        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
  62
  63        struct ehci_hcd_omap_platform_data      *ehci_data;
  64        struct ohci_hcd_omap_platform_data      *ohci_data;
  65
  66        /* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
  67        unsigned single_ulpi_bypass:1;
  68        unsigned es2_compatibility:1;
  69        unsigned phy_reset:1;
  70};
  71
  72/*-------------------------------------------------------------------------*/
  73
  74struct omap_musb_board_data {
  75        u8      interface_type;
  76        u8      mode;
  77        u16     power;
  78        unsigned extvbus:1;
  79        void    (*set_phy_power)(u8 on);
  80        void    (*clear_irq)(void);
  81        void    (*set_mode)(u8 mode);
  82        void    (*reset)(void);
  83};
  84
  85enum musb_interface {
  86        MUSB_INTERFACE_ULPI,
  87        MUSB_INTERFACE_UTMI
  88};
  89