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6#ifndef _LINUX_QCOM_GENI_SE
7#define _LINUX_QCOM_GENI_SE
8
9#include <linux/interconnect.h>
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23
24enum geni_se_xfer_mode {
25 GENI_SE_INVALID,
26 GENI_SE_FIFO,
27 GENI_SE_DMA,
28 GENI_GPI_DMA,
29};
30
31
32enum geni_se_protocol_type {
33 GENI_SE_NONE,
34 GENI_SE_SPI,
35 GENI_SE_UART,
36 GENI_SE_I2C,
37 GENI_SE_I3C,
38};
39
40struct geni_wrapper;
41struct clk;
42
43enum geni_icc_path_index {
44 GENI_TO_CORE,
45 CPU_TO_GENI,
46 GENI_TO_DDR
47};
48
49struct geni_icc_path {
50 struct icc_path *path;
51 unsigned int avg_bw;
52};
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63
64struct geni_se {
65 void __iomem *base;
66 struct device *dev;
67 struct geni_wrapper *wrapper;
68 struct clk *clk;
69 unsigned int num_clk_levels;
70 unsigned long *clk_perf_tbl;
71 struct geni_icc_path icc_paths[3];
72};
73
74
75#define GENI_FORCE_DEFAULT_REG 0x20
76#define SE_GENI_STATUS 0x40
77#define GENI_SER_M_CLK_CFG 0x48
78#define GENI_SER_S_CLK_CFG 0x4c
79#define GENI_IF_DISABLE_RO 0x64
80#define GENI_FW_REVISION_RO 0x68
81#define SE_GENI_CLK_SEL 0x7c
82#define SE_GENI_DMA_MODE_EN 0x258
83#define SE_GENI_M_CMD0 0x600
84#define SE_GENI_M_CMD_CTRL_REG 0x604
85#define SE_GENI_M_IRQ_STATUS 0x610
86#define SE_GENI_M_IRQ_EN 0x614
87#define SE_GENI_M_IRQ_CLEAR 0x618
88#define SE_GENI_S_CMD0 0x630
89#define SE_GENI_S_CMD_CTRL_REG 0x634
90#define SE_GENI_S_IRQ_STATUS 0x640
91#define SE_GENI_S_IRQ_EN 0x644
92#define SE_GENI_S_IRQ_CLEAR 0x648
93#define SE_GENI_TX_FIFOn 0x700
94#define SE_GENI_RX_FIFOn 0x780
95#define SE_GENI_TX_FIFO_STATUS 0x800
96#define SE_GENI_RX_FIFO_STATUS 0x804
97#define SE_GENI_TX_WATERMARK_REG 0x80c
98#define SE_GENI_RX_WATERMARK_REG 0x810
99#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
100#define SE_GENI_IOS 0x908
101#define SE_DMA_TX_IRQ_STAT 0xc40
102#define SE_DMA_TX_IRQ_CLR 0xc44
103#define SE_DMA_TX_FSM_RST 0xc58
104#define SE_DMA_RX_IRQ_STAT 0xd40
105#define SE_DMA_RX_IRQ_CLR 0xd44
106#define SE_DMA_RX_FSM_RST 0xd58
107#define SE_HW_PARAM_0 0xe24
108#define SE_HW_PARAM_1 0xe28
109
110
111#define FORCE_DEFAULT BIT(0)
112
113
114#define M_GENI_CMD_ACTIVE BIT(0)
115#define S_GENI_CMD_ACTIVE BIT(12)
116
117
118#define SER_CLK_EN BIT(0)
119#define CLK_DIV_MSK GENMASK(15, 4)
120#define CLK_DIV_SHFT 4
121
122
123#define FIFO_IF_DISABLE (BIT(0))
124
125
126#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
127#define FW_REV_PROTOCOL_SHFT 8
128
129
130#define CLK_SEL_MSK GENMASK(2, 0)
131
132
133#define GENI_DMA_MODE_EN BIT(0)
134
135
136#define M_OPCODE_MSK GENMASK(31, 27)
137#define M_OPCODE_SHFT 27
138#define M_PARAMS_MSK GENMASK(26, 0)
139
140
141#define M_GENI_CMD_CANCEL BIT(2)
142#define M_GENI_CMD_ABORT BIT(1)
143#define M_GENI_DISABLE BIT(0)
144
145
146#define S_OPCODE_MSK GENMASK(31, 27)
147#define S_OPCODE_SHFT 27
148#define S_PARAMS_MSK GENMASK(26, 0)
149
150
151#define S_GENI_CMD_CANCEL BIT(2)
152#define S_GENI_CMD_ABORT BIT(1)
153#define S_GENI_DISABLE BIT(0)
154
155
156#define M_CMD_DONE_EN BIT(0)
157#define M_CMD_OVERRUN_EN BIT(1)
158#define M_ILLEGAL_CMD_EN BIT(2)
159#define M_CMD_FAILURE_EN BIT(3)
160#define M_CMD_CANCEL_EN BIT(4)
161#define M_CMD_ABORT_EN BIT(5)
162#define M_TIMESTAMP_EN BIT(6)
163#define M_RX_IRQ_EN BIT(7)
164#define M_GP_SYNC_IRQ_0_EN BIT(8)
165#define M_GP_IRQ_0_EN BIT(9)
166#define M_GP_IRQ_1_EN BIT(10)
167#define M_GP_IRQ_2_EN BIT(11)
168#define M_GP_IRQ_3_EN BIT(12)
169#define M_GP_IRQ_4_EN BIT(13)
170#define M_GP_IRQ_5_EN BIT(14)
171#define M_IO_DATA_DEASSERT_EN BIT(22)
172#define M_IO_DATA_ASSERT_EN BIT(23)
173#define M_RX_FIFO_RD_ERR_EN BIT(24)
174#define M_RX_FIFO_WR_ERR_EN BIT(25)
175#define M_RX_FIFO_WATERMARK_EN BIT(26)
176#define M_RX_FIFO_LAST_EN BIT(27)
177#define M_TX_FIFO_RD_ERR_EN BIT(28)
178#define M_TX_FIFO_WR_ERR_EN BIT(29)
179#define M_TX_FIFO_WATERMARK_EN BIT(30)
180#define M_SEC_IRQ_EN BIT(31)
181#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
182 M_IO_DATA_DEASSERT_EN | \
183 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
184 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
185 M_TX_FIFO_WR_ERR_EN)
186
187
188#define S_CMD_DONE_EN BIT(0)
189#define S_CMD_OVERRUN_EN BIT(1)
190#define S_ILLEGAL_CMD_EN BIT(2)
191#define S_CMD_FAILURE_EN BIT(3)
192#define S_CMD_CANCEL_EN BIT(4)
193#define S_CMD_ABORT_EN BIT(5)
194#define S_GP_SYNC_IRQ_0_EN BIT(8)
195#define S_GP_IRQ_0_EN BIT(9)
196#define S_GP_IRQ_1_EN BIT(10)
197#define S_GP_IRQ_2_EN BIT(11)
198#define S_GP_IRQ_3_EN BIT(12)
199#define S_GP_IRQ_4_EN BIT(13)
200#define S_GP_IRQ_5_EN BIT(14)
201#define S_IO_DATA_DEASSERT_EN BIT(22)
202#define S_IO_DATA_ASSERT_EN BIT(23)
203#define S_RX_FIFO_RD_ERR_EN BIT(24)
204#define S_RX_FIFO_WR_ERR_EN BIT(25)
205#define S_RX_FIFO_WATERMARK_EN BIT(26)
206#define S_RX_FIFO_LAST_EN BIT(27)
207#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
208 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
209
210
211#define WATERMARK_MSK GENMASK(5, 0)
212
213
214#define TX_FIFO_WC GENMASK(27, 0)
215
216
217#define RX_LAST BIT(31)
218#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
219#define RX_LAST_BYTE_VALID_SHFT 28
220#define RX_FIFO_WC_MSK GENMASK(24, 0)
221
222
223#define IO2_DATA_IN BIT(1)
224#define RX_DATA_IN BIT(0)
225
226
227#define TX_DMA_DONE BIT(0)
228#define TX_EOT BIT(1)
229#define TX_SBE BIT(2)
230#define TX_RESET_DONE BIT(3)
231
232
233#define RX_DMA_DONE BIT(0)
234#define RX_EOT BIT(1)
235#define RX_SBE BIT(2)
236#define RX_RESET_DONE BIT(3)
237#define RX_FLUSH_DONE BIT(4)
238#define RX_GENI_GP_IRQ GENMASK(10, 5)
239#define RX_GENI_CANCEL_IRQ BIT(11)
240#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
241
242
243#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
244#define TX_FIFO_WIDTH_SHFT 24
245#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
246#define TX_FIFO_DEPTH_SHFT 16
247
248
249#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
250#define RX_FIFO_WIDTH_SHFT 24
251#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
252#define RX_FIFO_DEPTH_SHFT 16
253
254#define HW_VER_MAJOR_MASK GENMASK(31, 28)
255#define HW_VER_MAJOR_SHFT 28
256#define HW_VER_MINOR_MASK GENMASK(27, 16)
257#define HW_VER_MINOR_SHFT 16
258#define HW_VER_STEP_MASK GENMASK(15, 0)
259
260#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
261#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
262#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
263
264
265#define QUP_SE_VERSION_2_5 0x20050000
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273#define CORE_2X_19_2_MHZ 960
274#define CORE_2X_50_MHZ 2500
275#define CORE_2X_100_MHZ 5000
276#define CORE_2X_150_MHZ 7500
277#define CORE_2X_200_MHZ 10000
278#define CORE_2X_236_MHZ 16383
279
280#define GENI_DEFAULT_BW Bps_to_icc(1000)
281
282#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
283
284u32 geni_se_get_qup_hw_version(struct geni_se *se);
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292static inline u32 geni_se_read_proto(struct geni_se *se)
293{
294 u32 val;
295
296 val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
297
298 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
299}
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310static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
311{
312 u32 m_cmd;
313
314 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
315 writel(m_cmd, se->base + SE_GENI_M_CMD0);
316}
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327static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
328{
329 u32 s_cmd;
330
331 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
332 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
333 s_cmd |= (cmd << S_OPCODE_SHFT);
334 s_cmd |= (params & S_PARAMS_MSK);
335 writel(s_cmd, se->base + SE_GENI_S_CMD0);
336}
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346static inline void geni_se_cancel_m_cmd(struct geni_se *se)
347{
348 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
349}
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359static inline void geni_se_cancel_s_cmd(struct geni_se *se)
360{
361 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
362}
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371static inline void geni_se_abort_m_cmd(struct geni_se *se)
372{
373 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
374}
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384static inline void geni_se_abort_s_cmd(struct geni_se *se)
385{
386 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
387}
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398static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
399{
400 u32 val;
401
402 val = readl_relaxed(se->base + SE_HW_PARAM_0);
403
404 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
405}
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416static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
417{
418 u32 val;
419
420 val = readl_relaxed(se->base + SE_HW_PARAM_0);
421
422 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
423}
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433
434static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
435{
436 u32 val;
437
438 val = readl_relaxed(se->base + SE_HW_PARAM_1);
439
440 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
441}
442
443void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
444
445void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
446
447void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
448 bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
449
450int geni_se_resources_off(struct geni_se *se);
451
452int geni_se_resources_on(struct geni_se *se);
453
454int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
455
456int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
457 unsigned int *index, unsigned long *res_freq,
458 bool exact);
459
460int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
461 dma_addr_t *iova);
462
463int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
464 dma_addr_t *iova);
465
466void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
467
468void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
469
470int geni_icc_get(struct geni_se *se, const char *icc_ddr);
471
472int geni_icc_set_bw(struct geni_se *se);
473void geni_icc_set_tag(struct geni_se *se, u32 tag);
474
475int geni_icc_enable(struct geni_se *se);
476
477int geni_icc_disable(struct geni_se *se);
478#endif
479#endif
480