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7#ifndef _COMMON_HSI_H
8#define _COMMON_HSI_H
9
10#include <linux/types.h>
11#include <asm/byteorder.h>
12#include <linux/bitops.h>
13#include <linux/slab.h>
14
15
16#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
17#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
18#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
19#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
20#define DMA_REGPAIR_LE(x, val) do { \
21 (x).hi = DMA_HI_LE((val)); \
22 (x).lo = DMA_LO_LE((val)); \
23 } while (0)
24
25#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
26#define HILO_64(hi, lo) \
27 HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
28#define HILO_64_REGPAIR(regpair) ({ \
29 typeof(regpair) __regpair = (regpair); \
30 HILO_64(__regpair.hi, __regpair.lo); })
31#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
32
33#ifndef __COMMON_HSI__
34#define __COMMON_HSI__
35
36
37
38
39
40#define X_FINAL_CLEANUP_AGG_INT 1
41
42#define EVENT_RING_PAGE_SIZE_BYTES 4096
43
44#define NUM_OF_GLOBAL_QUEUES 128
45#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
46
47#define ISCSI_CDU_TASK_SEG_TYPE 0
48#define FCOE_CDU_TASK_SEG_TYPE 0
49#define RDMA_CDU_TASK_SEG_TYPE 1
50
51#define FW_ASSERT_GENERAL_ATTN_IDX 32
52
53
54
55#define TSTORM_QZONE_SIZE 8
56#define MSTORM_QZONE_SIZE 16
57#define USTORM_QZONE_SIZE 8
58#define XSTORM_QZONE_SIZE 8
59#define YSTORM_QZONE_SIZE 0
60#define PSTORM_QZONE_SIZE 0
61
62#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
63#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
64#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
65#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
66
67
68
69
70
71#define CORE_LL2_MAX_RAMROD_PER_CON 8
72#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
73#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
74#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
75#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
76
77#define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
78
79#define CORE_SPQE_PAGE_SIZE_BYTES 4096
80
81
82#define MAX_NUM_LL2_RX_RAM_QUEUES 32
83
84
85#define MAX_NUM_LL2_RX_CTX_QUEUES 208
86#define MAX_NUM_LL2_RX_QUEUES \
87 (MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES)
88
89#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
90
91#define FW_MAJOR_VERSION 8
92#define FW_MINOR_VERSION 42
93#define FW_REVISION_VERSION 2
94#define FW_ENGINEERING_VERSION 0
95
96
97
98
99
100
101#define MAX_NUM_PORTS_K2 (4)
102#define MAX_NUM_PORTS_BB (2)
103#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
104
105#define MAX_NUM_PFS_K2 (16)
106#define MAX_NUM_PFS_BB (8)
107#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
108#define MAX_NUM_OF_PFS_IN_CHIP (16)
109
110#define MAX_NUM_VFS_K2 (192)
111#define MAX_NUM_VFS_BB (120)
112#define MAX_NUM_VFS (MAX_NUM_VFS_K2)
113
114#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
115
116#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
117#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
118#define MAX_NUM_FUNCTIONS (MAX_FUNCTION_NUMBER_K2)
119
120#define MAX_NUM_VPORTS_K2 (208)
121#define MAX_NUM_VPORTS_BB (160)
122#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
123
124#define MAX_NUM_L2_QUEUES_K2 (320)
125#define MAX_NUM_L2_QUEUES_BB (256)
126#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
127
128
129#define NUM_PHYS_TCS_4PORT_K2 (4)
130#define NUM_OF_PHYS_TCS (8)
131#define PURE_LB_TC NUM_OF_PHYS_TCS
132#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
133#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
134
135
136#define NUM_OF_CONNECTION_TYPES_E4 (8)
137#define NUM_OF_LCIDS (320)
138#define NUM_OF_LTIDS (320)
139
140
141#define NUM_OF_GTT 19
142#define GTT_DWORD_SIZE_BITS 10
143#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
144#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
145
146
147#define TOOLS_VERSION 10
148
149
150
151
152
153#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
154#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
155
156#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
157#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
158
159#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
160#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
161#define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2)
162#define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3)
163#define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4)
164#define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5)
165
166
167
168
169
170
171#define DQ_DEMS_LEGACY 0
172#define DQ_DEMS_TOE_MORE_TO_SEND 3
173#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
174#define DQ_DEMS_ROCE_CQ_CONS 7
175
176
177#define DQ_XCM_AGG_VAL_SEL_WORD2 0
178#define DQ_XCM_AGG_VAL_SEL_WORD3 1
179#define DQ_XCM_AGG_VAL_SEL_WORD4 2
180#define DQ_XCM_AGG_VAL_SEL_WORD5 3
181#define DQ_XCM_AGG_VAL_SEL_REG3 4
182#define DQ_XCM_AGG_VAL_SEL_REG4 5
183#define DQ_XCM_AGG_VAL_SEL_REG5 6
184#define DQ_XCM_AGG_VAL_SEL_REG6 7
185
186
187#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
188#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
189#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
190#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
191#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
192#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
193#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
194#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
195#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
196#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
197#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
198#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
199#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
200#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
201#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
202#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
203#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
204#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
205#define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD DQ_XCM_AGG_VAL_SEL_WORD5
206
207
208#define DQ_UCM_AGG_VAL_SEL_WORD0 0
209#define DQ_UCM_AGG_VAL_SEL_WORD1 1
210#define DQ_UCM_AGG_VAL_SEL_WORD2 2
211#define DQ_UCM_AGG_VAL_SEL_WORD3 3
212#define DQ_UCM_AGG_VAL_SEL_REG0 4
213#define DQ_UCM_AGG_VAL_SEL_REG1 5
214#define DQ_UCM_AGG_VAL_SEL_REG2 6
215#define DQ_UCM_AGG_VAL_SEL_REG3 7
216
217
218#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
219#define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3
220#define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0
221#define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2
222
223
224#define DQ_TCM_AGG_VAL_SEL_WORD0 0
225#define DQ_TCM_AGG_VAL_SEL_WORD1 1
226#define DQ_TCM_AGG_VAL_SEL_WORD2 2
227#define DQ_TCM_AGG_VAL_SEL_WORD3 3
228#define DQ_TCM_AGG_VAL_SEL_REG1 4
229#define DQ_TCM_AGG_VAL_SEL_REG2 5
230#define DQ_TCM_AGG_VAL_SEL_REG6 6
231#define DQ_TCM_AGG_VAL_SEL_REG9 7
232
233
234#define DQ_TCM_L2B_BD_PROD_CMD \
235 DQ_TCM_AGG_VAL_SEL_WORD1
236#define DQ_TCM_ROCE_RQ_PROD_CMD \
237 DQ_TCM_AGG_VAL_SEL_WORD0
238
239
240#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
241#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
242#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
243#define DQ_XCM_AGG_FLG_SHIFT_CF13 3
244#define DQ_XCM_AGG_FLG_SHIFT_CF18 4
245#define DQ_XCM_AGG_FLG_SHIFT_CF19 5
246#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
247#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
248
249
250#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
251#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
252#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
253#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
254#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
255#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
256#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
257#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
258#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
259#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
260#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
261#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
262#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
263
264
265#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
266#define DQ_UCM_AGG_FLG_SHIFT_CF1 1
267#define DQ_UCM_AGG_FLG_SHIFT_CF3 2
268#define DQ_UCM_AGG_FLG_SHIFT_CF4 3
269#define DQ_UCM_AGG_FLG_SHIFT_CF5 4
270#define DQ_UCM_AGG_FLG_SHIFT_CF6 5
271#define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6
272#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
273
274
275#define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
276#define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
277#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
278#define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
279#define DQ_UCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF3)
280#define DQ_UCM_TOE_SLOW_PATH_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
281#define DQ_UCM_TOE_DQ_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
282
283
284#define DQ_TCM_AGG_FLG_SHIFT_CF0 0
285#define DQ_TCM_AGG_FLG_SHIFT_CF1 1
286#define DQ_TCM_AGG_FLG_SHIFT_CF2 2
287#define DQ_TCM_AGG_FLG_SHIFT_CF3 3
288#define DQ_TCM_AGG_FLG_SHIFT_CF4 4
289#define DQ_TCM_AGG_FLG_SHIFT_CF5 5
290#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
291#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
292
293#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
294#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
295#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
296#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
297#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
298#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
299#define DQ_TCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
300#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
301
302
303#define DQ_PWM_OFFSET_DPM_BASE 0x0
304#define DQ_PWM_OFFSET_DPM_END 0x27
305#define DQ_PWM_OFFSET_XCM16_BASE 0x40
306#define DQ_PWM_OFFSET_XCM32_BASE 0x44
307#define DQ_PWM_OFFSET_UCM16_BASE 0x48
308#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
309#define DQ_PWM_OFFSET_UCM16_4 0x50
310#define DQ_PWM_OFFSET_TCM16_BASE 0x58
311#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
312#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
313#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
314#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
315
316#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
317#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
318#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
319#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
320#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
321#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
322#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
323
324
325#define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \
326 (DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
327
328#define DQ_REGION_SHIFT (12)
329
330
331#define DQ_DPM_WQE_BUFF_SIZE (320)
332
333
334#define DQ_CONN_TYPE_RANGE_SHIFT (4)
335
336
337
338
339
340
341#define MAX_QM_TX_QUEUES_K2 512
342#define MAX_QM_TX_QUEUES_BB 448
343#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
344
345
346#define MAX_QM_OTHER_QUEUES_BB 64
347#define MAX_QM_OTHER_QUEUES_K2 128
348#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
349
350
351#define QM_PF_QUEUE_GROUP_SIZE 8
352
353
354#define QM_PQ_ELEMENT_SIZE 4
355
356
357
358
359#define CM_TX_PQ_BASE 0x200
360
361
362#define MAX_QM_GLOBAL_RLS 256
363
364
365#define QM_LINE_CRD_REG_WIDTH 16
366#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
367#define QM_BYTE_CRD_REG_WIDTH 24
368#define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1))
369#define QM_WFQ_CRD_REG_WIDTH 32
370#define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1))
371#define QM_RL_CRD_REG_WIDTH 32
372#define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1))
373
374
375
376
377
378#define CAU_FSM_ETH_RX 0
379#define CAU_FSM_ETH_TX 1
380
381
382#define PIS_PER_SB_E4 12
383#define MAX_PIS_PER_SB PIS_PER_SB
384
385#define CAU_HC_STOPPED_STATE 3
386#define CAU_HC_DISABLE_STATE 4
387#define CAU_HC_ENABLE_STATE 0
388
389
390
391
392
393#define MAX_SB_PER_PATH_K2 (368)
394#define MAX_SB_PER_PATH_BB (288)
395#define MAX_TOT_SB_PER_PATH \
396 MAX_SB_PER_PATH_K2
397
398#define MAX_SB_PER_PF_MIMD 129
399#define MAX_SB_PER_PF_SIMD 64
400#define MAX_SB_PER_VF 64
401
402
403#define IGU_MEM_BASE 0x0000
404
405#define IGU_MEM_MSIX_BASE 0x0000
406#define IGU_MEM_MSIX_UPPER 0x0101
407#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
408
409#define IGU_MEM_PBA_MSIX_BASE 0x0200
410#define IGU_MEM_PBA_MSIX_UPPER 0x0202
411#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
412
413#define IGU_CMD_INT_ACK_BASE 0x0400
414#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
415
416#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
417#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
418#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
419
420#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
421#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
422#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
423#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
424
425#define IGU_CMD_PROD_UPD_BASE 0x0600
426#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
427
428
429
430
431
432
433#define PXP_BAR_GRC 0
434#define PXP_BAR_TSDM 0
435#define PXP_BAR_USDM 0
436#define PXP_BAR_XSDM 0
437#define PXP_BAR_MSDM 0
438#define PXP_BAR_YSDM 0
439#define PXP_BAR_PSDM 0
440#define PXP_BAR_IGU 0
441#define PXP_BAR_DQ 1
442
443
444#define PXP_PER_PF_ENTRY_SIZE 8
445#define PXP_NUM_GLOBAL_WINDOWS 243
446#define PXP_GLOBAL_ENTRY_SIZE 4
447#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
448#define PXP_PF_WINDOW_ADMIN_START 0
449#define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
450#define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
451 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
452#define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
453#define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
454 PXP_PER_PF_ENTRY_SIZE)
455#define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
456 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
457#define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
458#define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
459 PXP_GLOBAL_ENTRY_SIZE)
460#define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
461 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
462 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
463#define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
464#define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
465#define PXP_PF_ME_OPAQUE_ADDR 0x1f8
466#define PXP_PF_ME_CONCRETE_ADDR 0x1fc
467
468#define PXP_NUM_PF_WINDOWS 12
469#define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
470#define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
471#define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
472#define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
473 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
474 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
475#define PXP_EXTERNAL_BAR_PF_WINDOW_END \
476 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
477 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
478
479#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
480 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
481#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
482#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
483#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
484 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
485 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
486#define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
487 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
488 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
489
490
491#define PXP_BAR0_START_GRC 0x0000
492#define PXP_BAR0_GRC_LENGTH 0x1C00000
493#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
494 PXP_BAR0_GRC_LENGTH - 1)
495
496#define PXP_BAR0_START_IGU 0x1C00000
497#define PXP_BAR0_IGU_LENGTH 0x10000
498#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
499 PXP_BAR0_IGU_LENGTH - 1)
500
501#define PXP_BAR0_START_TSDM 0x1C80000
502#define PXP_BAR0_SDM_LENGTH 0x40000
503#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
504#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
505 PXP_BAR0_SDM_LENGTH - 1)
506
507#define PXP_BAR0_START_MSDM 0x1D00000
508#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
509 PXP_BAR0_SDM_LENGTH - 1)
510
511#define PXP_BAR0_START_USDM 0x1D80000
512#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
513 PXP_BAR0_SDM_LENGTH - 1)
514
515#define PXP_BAR0_START_XSDM 0x1E00000
516#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
517 PXP_BAR0_SDM_LENGTH - 1)
518
519#define PXP_BAR0_START_YSDM 0x1E80000
520#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
521 PXP_BAR0_SDM_LENGTH - 1)
522
523#define PXP_BAR0_START_PSDM 0x1F00000
524#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
525 PXP_BAR0_SDM_LENGTH - 1)
526
527#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
528
529
530#define PXP_VF_BAR0 0
531
532#define PXP_VF_BAR0_START_IGU 0
533#define PXP_VF_BAR0_IGU_LENGTH 0x3000
534#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
535 PXP_VF_BAR0_IGU_LENGTH - 1)
536
537#define PXP_VF_BAR0_START_DQ 0x3000
538#define PXP_VF_BAR0_DQ_LENGTH 0x200
539#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
540#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
541 PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
542#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
543 + 4)
544#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
545 PXP_VF_BAR0_DQ_LENGTH - 1)
546
547#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
548#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
549#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
550 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
551
552#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
553#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
554 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
555
556#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
557#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
558 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
559
560#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
561#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
562 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
563
564#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
565#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
566 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
567
568#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
569#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
570 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
571
572#define PXP_VF_BAR0_START_GRC 0x3E00
573#define PXP_VF_BAR0_GRC_LENGTH 0x200
574#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
575 PXP_VF_BAR0_GRC_LENGTH - 1)
576
577#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
578#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
579
580#define PXP_VF_BAR0_START_IGU2 0x10000
581#define PXP_VF_BAR0_IGU2_LENGTH 0xD000
582#define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + \
583 PXP_VF_BAR0_IGU2_LENGTH - 1)
584
585#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
586
587#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
588#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
589
590
591#define PXP_NUM_ILT_RECORDS_BB 7600
592#define PXP_NUM_ILT_RECORDS_K2 11000
593#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
594
595
596#define PXP_QUEUES_ZONE_MAX_NUM 320
597
598
599
600
601#define PRM_DMA_PAD_BYTES_NUM 2
602
603
604
605
606
607#define SDM_OP_GEN_TRIG_NONE 0
608#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
609#define SDM_OP_GEN_TRIG_AGG_INT 2
610#define SDM_OP_GEN_TRIG_LOADER 4
611#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
612#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
613
614
615
616
617
618#define SDM_COMP_TYPE_NONE 0
619#define SDM_COMP_TYPE_WAKE_THREAD 1
620#define SDM_COMP_TYPE_AGG_INT 2
621#define SDM_COMP_TYPE_CM 3
622#define SDM_COMP_TYPE_LOADER 4
623#define SDM_COMP_TYPE_PXP 5
624#define SDM_COMP_TYPE_INDICATE_ERROR 6
625#define SDM_COMP_TYPE_RELEASE_THREAD 7
626#define SDM_COMP_TYPE_RAM 8
627#define SDM_COMP_TYPE_INC_ORDER_CNT 9
628
629
630
631
632
633
634#define PBF_MAX_CMD_LINES 3328
635
636
637#define BTB_MAX_BLOCKS_BB 1440
638#define BTB_MAX_BLOCKS_K2 1840
639
640
641
642
643#define PRS_GFT_CAM_LINES_NO_MATCH 31
644
645
646struct coalescing_timeset {
647 u8 value;
648#define COALESCING_TIMESET_TIMESET_MASK 0x7F
649#define COALESCING_TIMESET_TIMESET_SHIFT 0
650#define COALESCING_TIMESET_VALID_MASK 0x1
651#define COALESCING_TIMESET_VALID_SHIFT 7
652};
653
654struct common_queue_zone {
655 __le16 ring_drv_data_consumer;
656 __le16 reserved;
657};
658
659
660struct eth_rx_prod_data {
661 __le16 bd_prod;
662 __le16 cqe_prod;
663};
664
665struct tcp_ulp_connect_done_params {
666 __le16 mss;
667 u8 snd_wnd_scale;
668 u8 flags;
669#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
670#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
671#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
672#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
673};
674
675struct iscsi_connect_done_results {
676 __le16 icid;
677 __le16 conn_id;
678 struct tcp_ulp_connect_done_params params;
679};
680
681struct iscsi_eqe_data {
682 __le16 icid;
683 __le16 conn_id;
684 __le16 reserved;
685 u8 error_code;
686 u8 error_pdu_opcode_reserved;
687#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
688#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
689#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
690#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
691#define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
692#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
693};
694
695
696enum mf_mode {
697 ERROR_MODE ,
698 MF_OVLAN,
699 MF_NPAR,
700 MAX_MF_MODE
701};
702
703
704enum protocol_type {
705 PROTOCOLID_TCP_ULP,
706 PROTOCOLID_FCOE,
707 PROTOCOLID_ROCE,
708 PROTOCOLID_CORE,
709 PROTOCOLID_ETH,
710 PROTOCOLID_IWARP,
711 PROTOCOLID_RESERVED0,
712 PROTOCOLID_PREROCE,
713 PROTOCOLID_COMMON,
714 PROTOCOLID_RESERVED1,
715 PROTOCOLID_RDMA,
716 PROTOCOLID_SCSI,
717 MAX_PROTOCOL_TYPE
718};
719
720struct regpair {
721 __le32 lo;
722 __le32 hi;
723};
724
725
726struct rdma_eqe_destroy_qp {
727 __le32 cid;
728 u8 reserved[4];
729};
730
731
732union rdma_eqe_data {
733 struct regpair async_handle;
734 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
735};
736
737struct tstorm_queue_zone {
738 __le32 reserved[2];
739};
740
741
742struct ustorm_eth_queue_zone {
743 struct coalescing_timeset int_coalescing_timeset;
744 u8 reserved[3];
745};
746
747struct ustorm_queue_zone {
748 struct ustorm_eth_queue_zone eth;
749 struct common_queue_zone common;
750};
751
752
753struct cau_pi_entry {
754 __le32 prod;
755#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
756#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
757#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
758#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
759#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
760#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
761#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
762#define CAU_PI_ENTRY_RESERVED_SHIFT 24
763};
764
765
766struct cau_sb_entry {
767 __le32 data;
768#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
769#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
770#define CAU_SB_ENTRY_STATE0_MASK 0xF
771#define CAU_SB_ENTRY_STATE0_SHIFT 24
772#define CAU_SB_ENTRY_STATE1_MASK 0xF
773#define CAU_SB_ENTRY_STATE1_SHIFT 28
774 __le32 params;
775#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
776#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
777#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
778#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
779#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
780#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
781#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
782#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
783#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
784#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
785#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
786#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
787#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
788#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
789#define CAU_SB_ENTRY_TPH_MASK 0x1
790#define CAU_SB_ENTRY_TPH_SHIFT 31
791};
792
793
794
795
796enum command_type_bit {
797 IGU_COMMAND_TYPE_NOP = 0,
798 IGU_COMMAND_TYPE_SET = 1,
799 MAX_COMMAND_TYPE_BIT
800};
801
802
803struct core_db_data {
804 u8 params;
805#define CORE_DB_DATA_DEST_MASK 0x3
806#define CORE_DB_DATA_DEST_SHIFT 0
807#define CORE_DB_DATA_AGG_CMD_MASK 0x3
808#define CORE_DB_DATA_AGG_CMD_SHIFT 2
809#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
810#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
811#define CORE_DB_DATA_RESERVED_MASK 0x1
812#define CORE_DB_DATA_RESERVED_SHIFT 5
813#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
814#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
815 u8 agg_flags;
816 __le16 spq_prod;
817};
818
819
820enum db_agg_cmd_sel {
821 DB_AGG_CMD_NOP,
822 DB_AGG_CMD_SET,
823 DB_AGG_CMD_ADD,
824 DB_AGG_CMD_MAX,
825 MAX_DB_AGG_CMD_SEL
826};
827
828
829enum db_dest {
830 DB_DEST_XCM,
831 DB_DEST_UCM,
832 DB_DEST_TCM,
833 DB_NUM_DESTINATIONS,
834 MAX_DB_DEST
835};
836
837
838enum db_dpm_type {
839 DPM_LEGACY,
840 DPM_RDMA,
841 DPM_L2_INLINE,
842 DPM_L2_BD,
843 MAX_DB_DPM_TYPE
844};
845
846
847struct db_l2_dpm_data {
848 __le16 icid;
849 __le16 bd_prod;
850 __le32 params;
851#define DB_L2_DPM_DATA_SIZE_MASK 0x3F
852#define DB_L2_DPM_DATA_SIZE_SHIFT 0
853#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
854#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
855#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
856#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
857#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
858#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
859#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
860#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
861#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
862#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
863#define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK 0x1
864#define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31
865};
866
867
868struct db_l2_dpm_sge {
869 struct regpair addr;
870 __le16 nbytes;
871 __le16 bitfields;
872#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
873#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
874#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
875#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
876#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
877#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
878#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
879#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
880 __le32 reserved2;
881};
882
883
884struct db_legacy_addr {
885 __le32 addr;
886#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
887#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
888#define DB_LEGACY_ADDR_DEMS_MASK 0x7
889#define DB_LEGACY_ADDR_DEMS_SHIFT 2
890#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
891#define DB_LEGACY_ADDR_ICID_SHIFT 5
892};
893
894
895struct db_pwm_addr {
896 __le32 addr;
897#define DB_PWM_ADDR_RESERVED0_MASK 0x7
898#define DB_PWM_ADDR_RESERVED0_SHIFT 0
899#define DB_PWM_ADDR_OFFSET_MASK 0x7F
900#define DB_PWM_ADDR_OFFSET_SHIFT 3
901#define DB_PWM_ADDR_WID_MASK 0x3
902#define DB_PWM_ADDR_WID_SHIFT 10
903#define DB_PWM_ADDR_DPI_MASK 0xFFFF
904#define DB_PWM_ADDR_DPI_SHIFT 12
905#define DB_PWM_ADDR_RESERVED1_MASK 0xF
906#define DB_PWM_ADDR_RESERVED1_SHIFT 28
907};
908
909
910struct db_rdma_dpm_params {
911 __le32 params;
912#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
913#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
914#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
915#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
916#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
917#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
918#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
919#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
920#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
921#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
922#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1
923#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28
924#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
925#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
926#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
927#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30
928#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
929#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
930};
931
932
933
934
935struct db_rdma_dpm_data {
936 __le16 icid;
937 __le16 prod_val;
938 struct db_rdma_dpm_params params;
939};
940
941
942enum igu_int_cmd {
943 IGU_INT_ENABLE = 0,
944 IGU_INT_DISABLE = 1,
945 IGU_INT_NOP = 2,
946 IGU_INT_NOP2 = 3,
947 MAX_IGU_INT_CMD
948};
949
950
951struct igu_prod_cons_update {
952 __le32 sb_id_and_flags;
953#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
954#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
955#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
956#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
957#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
958#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
959#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
960#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
961#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
962#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
963#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
964#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
965#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
966#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
967 __le32 reserved1;
968};
969
970
971enum igu_seg_access {
972 IGU_SEG_ACCESS_REG = 0,
973 IGU_SEG_ACCESS_ATTN = 1,
974 MAX_IGU_SEG_ACCESS
975};
976
977
978
979
980
981enum l3_type {
982 e_l3_type_unknown,
983 e_l3_type_ipv4,
984 e_l3_type_ipv6,
985 MAX_L3_TYPE
986};
987
988
989
990
991
992
993enum l4_protocol {
994 e_l4_protocol_none,
995 e_l4_protocol_tcp,
996 e_l4_protocol_udp,
997 MAX_L4_PROTOCOL
998};
999
1000
1001struct parsing_and_err_flags {
1002 __le16 flags;
1003#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1004#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1005#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1006#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1007#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1008#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1009#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1010#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1011#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1012#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1013#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1014#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1015#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1016#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1017#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1018#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1019#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1020#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1021#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1022#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1023#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1024#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1025#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1026#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1027#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1028#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1029#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1030#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1031};
1032
1033
1034struct parsing_err_flags {
1035 __le16 flags;
1036#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
1037#define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1038#define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
1039#define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1
1040#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
1041#define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2
1042#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
1043#define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3
1044#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
1045#define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4
1046#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
1047#define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5
1048#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
1049#define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6
1050#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
1051#define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7
1052#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
1053#define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8
1054#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
1055#define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9
1056#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
1057#define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10
1058#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
1059#define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11
1060#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
1061#define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12
1062#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
1063#define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13
1064#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
1065#define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14
1066#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
1067#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
1068};
1069
1070
1071struct pb_context {
1072 __le32 crc[4];
1073};
1074
1075
1076struct pxp_concrete_fid {
1077 __le16 fid;
1078#define PXP_CONCRETE_FID_PFID_MASK 0xF
1079#define PXP_CONCRETE_FID_PFID_SHIFT 0
1080#define PXP_CONCRETE_FID_PORT_MASK 0x3
1081#define PXP_CONCRETE_FID_PORT_SHIFT 4
1082#define PXP_CONCRETE_FID_PATH_MASK 0x1
1083#define PXP_CONCRETE_FID_PATH_SHIFT 6
1084#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1085#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1086#define PXP_CONCRETE_FID_VFID_MASK 0xFF
1087#define PXP_CONCRETE_FID_VFID_SHIFT 8
1088};
1089
1090
1091struct pxp_pretend_concrete_fid {
1092 __le16 fid;
1093#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1094#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1095#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1096#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1097#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1098#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1099#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1100#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1101};
1102
1103
1104union pxp_pretend_fid {
1105 struct pxp_pretend_concrete_fid concrete_fid;
1106 __le16 opaque_fid;
1107};
1108
1109
1110struct pxp_pretend_cmd {
1111 union pxp_pretend_fid fid;
1112 __le16 control;
1113#define PXP_PRETEND_CMD_PATH_MASK 0x1
1114#define PXP_PRETEND_CMD_PATH_SHIFT 0
1115#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1116#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1117#define PXP_PRETEND_CMD_PORT_MASK 0x3
1118#define PXP_PRETEND_CMD_PORT_SHIFT 2
1119#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1120#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1121#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1122#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1123#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1124#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1125#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1126#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1127#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1128#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1129#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1130#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1131};
1132
1133
1134struct pxp_ptt_entry {
1135 __le32 offset;
1136#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1137#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1138#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1139#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1140 struct pxp_pretend_cmd pretend;
1141};
1142
1143
1144struct pxp_vf_zone_a_permission {
1145 __le32 control;
1146#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1147#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1148#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1149#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1150#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1151#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1152#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1153#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1154};
1155
1156
1157struct rdif_task_context {
1158 __le32 initial_ref_tag;
1159 __le16 app_tag_value;
1160 __le16 app_tag_mask;
1161 u8 flags0;
1162#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1163#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1164#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1165#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1166#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1167#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1168#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1169#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1170#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1171#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1172#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1173#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1174#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1175#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
1176 u8 partial_dif_data[7];
1177 __le16 partial_crc_value;
1178 __le16 partial_checksum_value;
1179 __le32 offset_in_io;
1180 __le16 flags1;
1181#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1182#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1183#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1184#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1185#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1186#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1187#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1188#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1189#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1190#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1191#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1192#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1193#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1194#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1195#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1196#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1197#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1198#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1199#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1200#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1201#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1202#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1203#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1204#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
1205#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1206#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
1207 __le16 state;
1208#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1209#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1210#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1211#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
1212#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1213#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
1214#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1215#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
1216#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1217#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
1218#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1219#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1220 __le32 reserved2;
1221};
1222
1223
1224struct status_block_e4 {
1225 __le16 pi_array[PIS_PER_SB_E4];
1226 __le32 sb_num;
1227#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
1228#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
1229#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
1230#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
1231#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
1232#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
1233 __le32 prod_index;
1234#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
1235#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
1236#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
1237#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
1238};
1239
1240
1241struct tdif_task_context {
1242 __le32 initial_ref_tag;
1243 __le16 app_tag_value;
1244 __le16 app_tag_mask;
1245 __le16 partial_crc_value_b;
1246 __le16 partial_checksum_value_b;
1247 __le16 stateB;
1248#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1249#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1250#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1251#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
1252#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1253#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
1254#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1255#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
1256#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1257#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1258 u8 reserved1;
1259 u8 flags0;
1260#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1261#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1262#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1263#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1264#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1265#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1266#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1267#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1268#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1269#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1270#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1271#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1272#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1273#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1274 __le32 flags1;
1275#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1276#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1277#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1278#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1279#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1280#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1281#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1282#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1283#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1284#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1285#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1286#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1287#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1288#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1289#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1290#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1291#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1292#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1293#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1294#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1295#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1296#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1297#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1298#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
1299#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1300#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
1301#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1302#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
1303#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1304#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
1305#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1306#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
1307#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1308#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
1309#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1310#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
1311#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1312#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
1313#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1314#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1315 __le32 offset_in_io_b;
1316 __le16 partial_crc_value_a;
1317 __le16 partial_checksum_value_a;
1318 __le32 offset_in_io_a;
1319 u8 partial_dif_data_a[8];
1320 u8 partial_dif_data_b[8];
1321};
1322
1323
1324struct timers_context {
1325 __le32 logical_client_0;
1326#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
1327#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1328#define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1329#define TIMERS_CONTEXT_RESERVED0_SHIFT 27
1330#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1331#define TIMERS_CONTEXT_VALIDLC0_SHIFT 28
1332#define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1333#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
1334#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1335#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
1336 __le32 logical_client_1;
1337#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
1338#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1339#define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1340#define TIMERS_CONTEXT_RESERVED2_SHIFT 27
1341#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1342#define TIMERS_CONTEXT_VALIDLC1_SHIFT 28
1343#define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1344#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
1345#define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1346#define TIMERS_CONTEXT_RESERVED3_SHIFT 30
1347 __le32 logical_client_2;
1348#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
1349#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1350#define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1351#define TIMERS_CONTEXT_RESERVED4_SHIFT 27
1352#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1353#define TIMERS_CONTEXT_VALIDLC2_SHIFT 28
1354#define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1355#define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29
1356#define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1357#define TIMERS_CONTEXT_RESERVED5_SHIFT 30
1358 __le32 host_expiration_fields;
1359#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
1360#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1361#define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1362#define TIMERS_CONTEXT_RESERVED6_SHIFT 27
1363#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1364#define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28
1365#define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1366#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
1367};
1368
1369
1370enum tunnel_next_protocol {
1371 e_unknown = 0,
1372 e_l2 = 1,
1373 e_ipv4 = 2,
1374 e_ipv6 = 3,
1375 MAX_TUNNEL_NEXT_PROTOCOL
1376};
1377
1378#endif
1379#endif
1380