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9#ifndef __TISCI_PROTOCOL_H
10#define __TISCI_PROTOCOL_H
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21struct ti_sci_version_info {
22 u8 abi_major;
23 u8 abi_minor;
24 u16 firmware_revision;
25 char firmware_description[32];
26};
27
28struct ti_sci_handle;
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36struct ti_sci_core_ops {
37 int (*reboot_device)(const struct ti_sci_handle *handle);
38};
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98struct ti_sci_dev_ops {
99 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
100 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
101 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
102 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
103 u32 id);
104 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
105 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
106 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
107 u32 id, u32 *count);
108 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
109 bool *requested_state);
110 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
111 bool *req_state, bool *current_state);
112 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
113 bool *req_state, bool *current_state);
114 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
115 bool *current_state);
116 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
117 u32 reset_state);
118 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
119 u32 *reset_state);
120};
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171struct ti_sci_clk_ops {
172 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
173 bool needs_ssc, bool can_change_freq,
174 bool enable_input_term);
175 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
176 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
177 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
178 bool *req_state);
179 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
180 bool *req_state, bool *current_state);
181 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
182 bool *req_state, bool *current_state);
183 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
184 u32 parent_id);
185 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
186 u32 *parent_id);
187 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
188 u32 cid, u32 *num_parents);
189 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
190 u32 cid, u64 min_freq, u64 target_freq,
191 u64 max_freq, u64 *match_freq);
192 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
193 u64 min_freq, u64 target_freq, u64 max_freq);
194 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
195 u64 *current_freq);
196};
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206struct ti_sci_resource_desc {
207 u16 start;
208 u16 num;
209 u16 start_sec;
210 u16 num_sec;
211 unsigned long *res_map;
212};
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231struct ti_sci_rm_core_ops {
232 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
233 u8 subtype, struct ti_sci_resource_desc *desc);
234 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
235 u32 dev_id, u8 subtype, u8 s_host,
236 struct ti_sci_resource_desc *desc);
237};
238
239#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
240#define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
241#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
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253struct ti_sci_rm_irq_ops {
254 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
255 u16 src_index, u16 dst_id, u16 dst_host_irq);
256 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
257 u16 src_index, u16 ia_id, u16 vint,
258 u16 global_event, u8 vint_status_bit);
259 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
260 u16 src_index, u16 dst_id, u16 dst_host_irq);
261 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
262 u16 src_index, u16 ia_id, u16 vint,
263 u16 global_event, u8 vint_status_bit);
264};
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266
267#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
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269#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
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271#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
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273#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
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275#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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277#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
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279#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6)
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281#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
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283#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
284 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
285 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
286 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
287 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
288 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
289 TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
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297struct ti_sci_msg_rm_ring_cfg {
298 u32 valid_params;
299 u16 nav_id;
300 u16 index;
301 u32 addr_lo;
302 u32 addr_hi;
303 u32 count;
304 u8 mode;
305 u8 size;
306 u8 order_id;
307 u16 virtid;
308 u8 asel;
309};
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315struct ti_sci_rm_ringacc_ops {
316 int (*set_cfg)(const struct ti_sci_handle *handle,
317 const struct ti_sci_msg_rm_ring_cfg *params);
318};
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333struct ti_sci_rm_psil_ops {
334 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
335 u32 src_thread, u32 dst_thread);
336 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
337 u32 src_thread, u32 dst_thread);
338};
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341#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
342#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3
343#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
344#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
345#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
346#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
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348#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
349#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
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351#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
352#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
353#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
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355#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
356#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
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359#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
360#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
361#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
362#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
363#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
364#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
365#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
366#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
367#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
368#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
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376struct ti_sci_msg_rm_udmap_tx_ch_cfg {
377 u32 valid_params;
378#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
379#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
380#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
381#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
382#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
383#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
384#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
385 u16 nav_id;
386 u16 index;
387 u8 tx_pause_on_err;
388 u8 tx_filt_einfo;
389 u8 tx_filt_pswords;
390 u8 tx_atype;
391 u8 tx_chan_type;
392 u8 tx_supr_tdpkt;
393 u16 tx_fetch_size;
394 u8 tx_credit_count;
395 u16 txcq_qnum;
396 u8 tx_priority;
397 u8 tx_qos;
398 u8 tx_orderid;
399 u16 fdepth;
400 u8 tx_sched_priority;
401 u8 tx_burst_size;
402 u8 tx_tdtype;
403 u8 extended_ch_type;
404};
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412struct ti_sci_msg_rm_udmap_rx_ch_cfg {
413 u32 valid_params;
414#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
415#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
416#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
417#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
418 u16 nav_id;
419 u16 index;
420 u16 rx_fetch_size;
421 u16 rxcq_qnum;
422 u8 rx_priority;
423 u8 rx_qos;
424 u8 rx_orderid;
425 u8 rx_sched_priority;
426 u16 flowid_start;
427 u16 flowid_cnt;
428 u8 rx_pause_on_err;
429 u8 rx_atype;
430 u8 rx_chan_type;
431 u8 rx_ignore_short;
432 u8 rx_ignore_long;
433 u8 rx_burst_size;
434};
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442struct ti_sci_msg_rm_udmap_flow_cfg {
443 u32 valid_params;
444#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
445#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
446#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
447#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
448#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
449#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
450#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
451#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
452#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
453#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
454#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
455#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
456#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
457#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
458#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
459#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
460#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
461#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
462#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
463 u16 nav_id;
464 u16 flow_index;
465 u8 rx_einfo_present;
466 u8 rx_psinfo_present;
467 u8 rx_error_handling;
468 u8 rx_desc_type;
469 u16 rx_sop_offset;
470 u16 rx_dest_qnum;
471 u8 rx_src_tag_hi;
472 u8 rx_src_tag_lo;
473 u8 rx_dest_tag_hi;
474 u8 rx_dest_tag_lo;
475 u8 rx_src_tag_hi_sel;
476 u8 rx_src_tag_lo_sel;
477 u8 rx_dest_tag_hi_sel;
478 u8 rx_dest_tag_lo_sel;
479 u16 rx_fdq0_sz0_qnum;
480 u16 rx_fdq1_qnum;
481 u16 rx_fdq2_qnum;
482 u16 rx_fdq3_qnum;
483 u8 rx_ps_location;
484};
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492struct ti_sci_rm_udmap_ops {
493 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
494 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
495 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
496 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
497 int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
498 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
499};
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517struct ti_sci_proc_ops {
518 int (*request)(const struct ti_sci_handle *handle, u8 pid);
519 int (*release)(const struct ti_sci_handle *handle, u8 pid);
520 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
521 int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
522 u64 boot_vector, u32 cfg_set, u32 cfg_clr);
523 int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
524 u32 ctrl_set, u32 ctrl_clr);
525 int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
526 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
527 u32 *status_flags);
528};
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538struct ti_sci_ops {
539 struct ti_sci_core_ops core_ops;
540 struct ti_sci_dev_ops dev_ops;
541 struct ti_sci_clk_ops clk_ops;
542 struct ti_sci_rm_core_ops rm_core_ops;
543 struct ti_sci_rm_irq_ops rm_irq_ops;
544 struct ti_sci_rm_ringacc_ops rm_ring_ops;
545 struct ti_sci_rm_psil_ops rm_psil_ops;
546 struct ti_sci_rm_udmap_ops rm_udmap_ops;
547 struct ti_sci_proc_ops proc_ops;
548};
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555struct ti_sci_handle {
556 struct ti_sci_version_info version;
557 struct ti_sci_ops ops;
558};
559
560#define TI_SCI_RESOURCE_NULL 0xffff
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569struct ti_sci_resource {
570 u16 sets;
571 raw_spinlock_t lock;
572 struct ti_sci_resource_desc *desc;
573};
574
575#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
576const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
577int ti_sci_put_handle(const struct ti_sci_handle *handle);
578const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
579const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
580 const char *property);
581const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
582 const char *property);
583u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
584void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
585u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
586struct ti_sci_resource *
587devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
588 struct device *dev, u32 dev_id, char *of_prop);
589struct ti_sci_resource *
590devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
591 u32 dev_id, u32 sub_type);
592
593#else
594
595static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
596{
597 return ERR_PTR(-EINVAL);
598}
599
600static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
601{
602 return -EINVAL;
603}
604
605static inline
606const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
607{
608 return ERR_PTR(-EINVAL);
609}
610
611static inline
612const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
613 const char *property)
614{
615 return ERR_PTR(-EINVAL);
616}
617
618static inline
619const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
620 const char *property)
621{
622 return ERR_PTR(-EINVAL);
623}
624
625static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
626{
627 return TI_SCI_RESOURCE_NULL;
628}
629
630static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
631{
632}
633
634static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
635{
636 return 0;
637}
638
639static inline struct ti_sci_resource *
640devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
641 struct device *dev, u32 dev_id, char *of_prop)
642{
643 return ERR_PTR(-EINVAL);
644}
645
646static inline struct ti_sci_resource *
647devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
648 u32 dev_id, u32 sub_type);
649{
650 return ERR_PTR(-EINVAL);
651}
652#endif
653
654#endif
655