LXR linux/include/linux/ssb/ssb.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef LINUX_SSB_H_
   3#define LINUX_SSB_H_
   4
   5#include <linux/device.h>
   6#include <linux/list.h>
   7#include <linux/types.h>
   8#include <linux/spinlock.h>
   9#include <linux/pci.h>
  10#include <linux/gpio/driver.h>
  11#include <linux/mod_devicetable.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/platform_device.h>
  14
  15#include <linux/ssb/ssb_regs.h>
  16
  17
  18struct pcmcia_device;
  19struct ssb_bus;
  20struct ssb_driver;
  21
  22struct ssb_sprom_core_pwr_info {
  23        u8 itssi_2g, itssi_5g;
  24        u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
  25        u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
  26};
  27
  28struct ssb_sprom {
  29        u8 revision;
  30        u8 il0mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11b/g */
  31        u8 et0mac[6] __aligned(sizeof(u16));    /* MAC address for Ethernet */
  32        u8 et1mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11a */
  33        u8 et2mac[6] __aligned(sizeof(u16));    /* MAC address for extra Ethernet */
  34        u8 et0phyaddr;          /* MII address for enet0 */
  35        u8 et1phyaddr;          /* MII address for enet1 */
  36        u8 et2phyaddr;          /* MII address for enet2 */
  37        u8 et0mdcport;          /* MDIO for enet0 */
  38        u8 et1mdcport;          /* MDIO for enet1 */
  39        u8 et2mdcport;          /* MDIO for enet2 */
  40        u16 dev_id;             /* Device ID overriding e.g. PCI ID */
  41        u16 board_rev;          /* Board revision number from SPROM. */
  42        u16 board_num;          /* Board number from SPROM. */
  43        u16 board_type;         /* Board type from SPROM. */
  44        u8 country_code;        /* Country Code */
  45        char alpha2[2];         /* Country Code as two chars like EU or US */
  46        u8 leddc_on_time;       /* LED Powersave Duty Cycle On Count */
  47        u8 leddc_off_time;      /* LED Powersave Duty Cycle Off Count */
  48        u8 ant_available_a;     /* 2GHz antenna available bits (up to 4) */
  49        u8 ant_available_bg;    /* 5GHz antenna available bits (up to 4) */
  50        u16 pa0b0;
  51        u16 pa0b1;
  52        u16 pa0b2;
  53        u16 pa1b0;
  54        u16 pa1b1;
  55        u16 pa1b2;
  56        u16 pa1lob0;
  57        u16 pa1lob1;
  58        u16 pa1lob2;
  59        u16 pa1hib0;
  60        u16 pa1hib1;
  61        u16 pa1hib2;
  62        u8 gpio0;               /* GPIO pin 0 */
  63        u8 gpio1;               /* GPIO pin 1 */
  64        u8 gpio2;               /* GPIO pin 2 */
  65        u8 gpio3;               /* GPIO pin 3 */
  66        u8 maxpwr_bg;           /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
  67        u8 maxpwr_al;           /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
  68        u8 maxpwr_a;            /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
  69        u8 maxpwr_ah;           /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
  70        u8 itssi_a;             /* Idle TSSI Target for A-PHY */
  71        u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
  72        u8 tri2g;               /* 2.4GHz TX isolation */
  73        u8 tri5gl;              /* 5.2GHz TX isolation */
  74        u8 tri5g;               /* 5.3GHz TX isolation */
  75        u8 tri5gh;              /* 5.8GHz TX isolation */
  76        u8 txpid2g[4];          /* 2GHz TX power index */
  77        u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
  78        u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
  79        u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
  80        s8 rxpo2g;              /* 2GHz RX power offset */
  81        s8 rxpo5g;              /* 5GHz RX power offset */
  82        u8 rssisav2g;           /* 2GHz RSSI params */
  83        u8 rssismc2g;
  84        u8 rssismf2g;
  85        u8 bxa2g;               /* 2GHz BX arch */
  86        u8 rssisav5g;           /* 5GHz RSSI params */
  87        u8 rssismc5g;
  88        u8 rssismf5g;
  89        u8 bxa5g;               /* 5GHz BX arch */
  90        u16 cck2gpo;            /* CCK power offset */
  91        u32 ofdm2gpo;           /* 2.4GHz OFDM power offset */
  92        u32 ofdm5glpo;          /* 5.2GHz OFDM power offset */
  93        u32 ofdm5gpo;           /* 5.3GHz OFDM power offset */
  94        u32 ofdm5ghpo;          /* 5.8GHz OFDM power offset */
  95        u32 boardflags;
  96        u32 boardflags2;
  97        u32 boardflags3;
  98        /* TODO: Switch all drivers to new u32 fields and drop below ones */
  99        u16 boardflags_lo;      /* Board flags (bits 0-15) */
 100        u16 boardflags_hi;      /* Board flags (bits 16-31) */
 101        u16 boardflags2_lo;     /* Board flags (bits 32-47) */
 102        u16 boardflags2_hi;     /* Board flags (bits 48-63) */
 103
 104        struct ssb_sprom_core_pwr_info core_pwr_info[4];
 105
 106        /* Antenna gain values for up to 4 antennas
 107         * on each band. Values in dBm/4 (Q5.2). Negative gain means the
 108         * loss in the connectors is bigger than the gain. */
 109        struct {
 110                s8 a0, a1, a2, a3;
 111        } antenna_gain;
 112
 113        struct {
 114                struct {
 115                        u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 116                } ghz2;
 117                struct {
 118                        u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 119                } ghz5;
 120        } fem;
 121
 122        u16 mcs2gpo[8];
 123        u16 mcs5gpo[8];
 124        u16 mcs5glpo[8];
 125        u16 mcs5ghpo[8];
 126        u8 opo;
 127
 128        u8 rxgainerr2ga[3];
 129        u8 rxgainerr5gla[3];
 130        u8 rxgainerr5gma[3];
 131        u8 rxgainerr5gha[3];
 132        u8 rxgainerr5gua[3];
 133
 134        u8 noiselvl2ga[3];
 135        u8 noiselvl5gla[3];
 136        u8 noiselvl5gma[3];
 137        u8 noiselvl5gha[3];
 138        u8 noiselvl5gua[3];
 139
 140        u8 regrev;
 141        u8 txchain;
 142        u8 rxchain;
 143        u8 antswitch;
 144        u16 cddpo;
 145        u16 stbcpo;
 146        u16 bw40po;
 147        u16 bwduppo;
 148
 149        u8 tempthresh;
 150        u8 tempoffset;
 151        u16 rawtempsense;
 152        u8 measpower;
 153        u8 tempsense_slope;
 154        u8 tempcorrx;
 155        u8 tempsense_option;
 156        u8 freqoffset_corr;
 157        u8 iqcal_swp_dis;
 158        u8 hw_iqcal_en;
 159        u8 elna2g;
 160        u8 elna5g;
 161        u8 phycal_tempdelta;
 162        u8 temps_period;
 163        u8 temps_hysteresis;
 164        u8 measpower1;
 165        u8 measpower2;
 166        u8 pcieingress_war;
 167
 168        /* power per rate from sromrev 9 */
 169        u16 cckbw202gpo;
 170        u16 cckbw20ul2gpo;
 171        u32 legofdmbw202gpo;
 172        u32 legofdmbw20ul2gpo;
 173        u32 legofdmbw205glpo;
 174        u32 legofdmbw20ul5glpo;
 175        u32 legofdmbw205gmpo;
 176        u32 legofdmbw20ul5gmpo;
 177        u32 legofdmbw205ghpo;
 178        u32 legofdmbw20ul5ghpo;
 179        u32 mcsbw202gpo;
 180        u32 mcsbw20ul2gpo;
 181        u32 mcsbw402gpo;
 182        u32 mcsbw205glpo;
 183        u32 mcsbw20ul5glpo;
 184        u32 mcsbw405glpo;
 185        u32 mcsbw205gmpo;
 186        u32 mcsbw20ul5gmpo;
 187        u32 mcsbw405gmpo;
 188        u32 mcsbw205ghpo;
 189        u32 mcsbw20ul5ghpo;
 190        u32 mcsbw405ghpo;
 191        u16 mcs32po;
 192        u16 legofdm40duppo;
 193        u8 sar2g;
 194        u8 sar5g;
 195};
 196
 197/* Information about the PCB the circuitry is soldered on. */
 198struct ssb_boardinfo {
 199        u16 vendor;
 200        u16 type;
 201};
 202
 203
 204struct ssb_device;
 205/* Lowlevel read/write operations on the device MMIO.
 206 * Internal, don't use that outside of ssb. */
 207struct ssb_bus_ops {
 208        u8 (*read8)(struct ssb_device *dev, u16 offset);
 209        u16 (*read16)(struct ssb_device *dev, u16 offset);
 210        u32 (*read32)(struct ssb_device *dev, u16 offset);
 211        void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
 212        void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
 213        void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
 214#ifdef CONFIG_SSB_BLOCKIO
 215        void (*block_read)(struct ssb_device *dev, void *buffer,
 216                           size_t count, u16 offset, u8 reg_width);
 217        void (*block_write)(struct ssb_device *dev, const void *buffer,
 218                            size_t count, u16 offset, u8 reg_width);
 219#endif
 220};
 221
 222
 223/* Core-ID values. */
 224#define SSB_DEV_CHIPCOMMON      0x800
 225#define SSB_DEV_ILINE20         0x801
 226#define SSB_DEV_SDRAM           0x803
 227#define SSB_DEV_PCI             0x804
 228#define SSB_DEV_MIPS            0x805
 229#define SSB_DEV_ETHERNET        0x806
 230#define SSB_DEV_V90             0x807
 231#define SSB_DEV_USB11_HOSTDEV   0x808
 232#define SSB_DEV_ADSL            0x809
 233#define SSB_DEV_ILINE100        0x80A
 234#define SSB_DEV_IPSEC           0x80B
 235#define SSB_DEV_PCMCIA          0x80D
 236#define SSB_DEV_INTERNAL_MEM    0x80E
 237#define SSB_DEV_MEMC_SDRAM      0x80F
 238#define SSB_DEV_EXTIF           0x811
 239#define SSB_DEV_80211           0x812
 240#define SSB_DEV_MIPS_3302       0x816
 241#define SSB_DEV_USB11_HOST      0x817
 242#define SSB_DEV_USB11_DEV       0x818
 243#define SSB_DEV_USB20_HOST      0x819
 244#define SSB_DEV_USB20_DEV       0x81A
 245#define SSB_DEV_SDIO_HOST       0x81B
 246#define SSB_DEV_ROBOSWITCH      0x81C
 247#define SSB_DEV_PARA_ATA        0x81D
 248#define SSB_DEV_SATA_XORDMA     0x81E
 249#define SSB_DEV_ETHERNET_GBIT   0x81F
 250#define SSB_DEV_PCIE            0x820
 251#define SSB_DEV_MIMO_PHY        0x821
 252#define SSB_DEV_SRAM_CTRLR      0x822
 253#define SSB_DEV_MINI_MACPHY     0x823
 254#define SSB_DEV_ARM_1176        0x824
 255#define SSB_DEV_ARM_7TDMI       0x825
 256#define SSB_DEV_ARM_CM3         0x82A
 257
 258/* Vendor-ID values */
 259#define SSB_VENDOR_BROADCOM     0x4243
 260
 261/* Some kernel subsystems poke with dev->drvdata, so we must use the
 262 * following ugly workaround to get from struct device to struct ssb_device */
 263struct __ssb_dev_wrapper {
 264        struct device dev;
 265        struct ssb_device *sdev;
 266};
 267
 268struct ssb_device {
 269        /* Having a copy of the ops pointer in each dev struct
 270         * is an optimization. */
 271        const struct ssb_bus_ops *ops;
 272
 273        struct device *dev, *dma_dev;
 274
 275        struct ssb_bus *bus;
 276        struct ssb_device_id id;
 277
 278        u8 core_index;
 279        unsigned int irq;
 280
 281        /* Internal-only stuff follows. */
 282        void *drvdata;          /* Per-device data */
 283        void *devtypedata;      /* Per-devicetype (eg 802.11) data */
 284};
 285
 286/* Go from struct device to struct ssb_device. */
 287static inline
 288struct ssb_device * dev_to_ssb_dev(struct device *dev)
 289{
 290        struct __ssb_dev_wrapper *wrap;
 291        wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
 292        return wrap->sdev;
 293}
 294
 295/* Device specific user data */
 296static inline
 297void ssb_set_drvdata(struct ssb_device *dev, void *data)
 298{
 299        dev->drvdata = data;
 300}
 301static inline
 302void * ssb_get_drvdata(struct ssb_device *dev)
 303{
 304        return dev->drvdata;
 305}
 306
 307/* Devicetype specific user data. This is per device-type (not per device) */
 308void ssb_set_devtypedata(struct ssb_device *dev, void *data);
 309static inline
 310void * ssb_get_devtypedata(struct ssb_device *dev)
 311{
 312        return dev->devtypedata;
 313}
 314
 315
 316struct ssb_driver {
 317        const char *name;
 318        const struct ssb_device_id *id_table;
 319
 320        int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
 321        void (*remove)(struct ssb_device *dev);
 322        int (*suspend)(struct ssb_device *dev, pm_message_t state);
 323        int (*resume)(struct ssb_device *dev);
 324        void (*shutdown)(struct ssb_device *dev);
 325
 326        struct device_driver drv;
 327};
 328#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
 329
 330extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
 331#define ssb_driver_register(drv) \
 332        __ssb_driver_register(drv, THIS_MODULE)
 333
 334extern void ssb_driver_unregister(struct ssb_driver *drv);
 335
 336
 337
 338
 339enum ssb_bustype {
 340        SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
 341        SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
 342        SSB_BUSTYPE_PCMCIA,     /* SSB is connected to PCMCIA bus */
 343        SSB_BUSTYPE_SDIO,       /* SSB is connected to SDIO bus */
 344};
 345
 346/* board_vendor */
 347#define SSB_BOARDVENDOR_BCM     0x14E4  /* Broadcom */
 348#define SSB_BOARDVENDOR_DELL    0x1028  /* Dell */
 349#define SSB_BOARDVENDOR_HP      0x0E11  /* HP */
 350/* board_type */
 351#define SSB_BOARD_BCM94301CB    0x0406
 352#define SSB_BOARD_BCM94301MP    0x0407
 353#define SSB_BOARD_BU4309        0x040A
 354#define SSB_BOARD_BCM94309CB    0x040B
 355#define SSB_BOARD_BCM4309MP     0x040C
 356#define SSB_BOARD_BU4306        0x0416
 357#define SSB_BOARD_BCM94306MP    0x0418
 358#define SSB_BOARD_BCM4309G      0x0421
 359#define SSB_BOARD_BCM4306CB     0x0417
 360#define SSB_BOARD_BCM94306PC    0x0425  /* pcmcia 3.3v 4306 card */
 361#define SSB_BOARD_BCM94306CBSG  0x042B  /* with SiGe PA */
 362#define SSB_BOARD_PCSG94306     0x042D  /* with SiGe PA */
 363#define SSB_BOARD_BU4704SD      0x042E  /* with sdram */
 364#define SSB_BOARD_BCM94704AGR   0x042F  /* dual 11a/11g Router */
 365#define SSB_BOARD_BCM94308MP    0x0430  /* 11a-only minipci */
 366#define SSB_BOARD_BU4318        0x0447
 367#define SSB_BOARD_CB4318        0x0448
 368#define SSB_BOARD_MPG4318       0x0449
 369#define SSB_BOARD_MP4318        0x044A
 370#define SSB_BOARD_SD4318        0x044B
 371#define SSB_BOARD_BCM94306P     0x044C  /* with SiGe */
 372#define SSB_BOARD_BCM94303MP    0x044E
 373#define SSB_BOARD_BCM94306MPM   0x0450
 374#define SSB_BOARD_BCM94306MPL   0x0453
 375#define SSB_BOARD_PC4303        0x0454  /* pcmcia */
 376#define SSB_BOARD_BCM94306MPLNA 0x0457
 377#define SSB_BOARD_BCM94306MPH   0x045B
 378#define SSB_BOARD_BCM94306PCIV  0x045C
 379#define SSB_BOARD_BCM94318MPGH  0x0463
 380#define SSB_BOARD_BU4311        0x0464
 381#define SSB_BOARD_BCM94311MC    0x0465
 382#define SSB_BOARD_BCM94311MCAG  0x0466
 383/* 4321 boards */
 384#define SSB_BOARD_BU4321        0x046B
 385#define SSB_BOARD_BU4321E       0x047C
 386#define SSB_BOARD_MP4321        0x046C
 387#define SSB_BOARD_CB2_4321      0x046D
 388#define SSB_BOARD_CB2_4321_AG   0x0066
 389#define SSB_BOARD_MC4321        0x046E
 390/* 4325 boards */
 391#define SSB_BOARD_BCM94325DEVBU 0x0490
 392#define SSB_BOARD_BCM94325BGABU 0x0491
 393#define SSB_BOARD_BCM94325SDGWB 0x0492
 394#define SSB_BOARD_BCM94325SDGMDL        0x04AA
 395#define SSB_BOARD_BCM94325SDGMDL2       0x04C6
 396#define SSB_BOARD_BCM94325SDGMDL3       0x04C9
 397#define SSB_BOARD_BCM94325SDABGWBA      0x04E1
 398/* 4322 boards */
 399#define SSB_BOARD_BCM94322MC    0x04A4
 400#define SSB_BOARD_BCM94322USB   0x04A8  /* dualband */
 401#define SSB_BOARD_BCM94322HM    0x04B0
 402#define SSB_BOARD_BCM94322USB2D 0x04Bf  /* single band discrete front end */
 403/* 4312 boards */
 404#define SSB_BOARD_BU4312        0x048A
 405#define SSB_BOARD_BCM4312MCGSG  0x04B5
 406/* chip_package */
 407#define SSB_CHIPPACK_BCM4712S   1       /* Small 200pin 4712 */
 408#define SSB_CHIPPACK_BCM4712M   2       /* Medium 225pin 4712 */
 409#define SSB_CHIPPACK_BCM4712L   0       /* Large 340pin 4712 */
 410
 411#include <linux/ssb/ssb_driver_chipcommon.h>
 412#include <linux/ssb/ssb_driver_mips.h>
 413#include <linux/ssb/ssb_driver_extif.h>
 414#include <linux/ssb/ssb_driver_pci.h>
 415
 416struct ssb_bus {
 417        /* The MMIO area. */
 418        void __iomem *mmio;
 419
 420        const struct ssb_bus_ops *ops;
 421
 422        /* The core currently mapped into the MMIO window.
 423         * Not valid on all host-buses. So don't use outside of SSB. */
 424        struct ssb_device *mapped_device;
 425        union {
 426                /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
 427                u8 mapped_pcmcia_seg;
 428                /* Current SSB base address window for SDIO. */
 429                u32 sdio_sbaddr;
 430        };
 431        /* Lock for core and segment switching.
 432         * On PCMCIA-host busses this is used to protect the whole MMIO access. */
 433        spinlock_t bar_lock;
 434
 435        /* The host-bus this backplane is running on. */
 436        enum ssb_bustype bustype;
 437        /* Pointers to the host-bus. Check bustype before using any of these pointers. */
 438        union {
 439                /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
 440                struct pci_dev *host_pci;
 441                /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
 442                struct pcmcia_device *host_pcmcia;
 443                /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
 444                struct sdio_func *host_sdio;
 445        };
 446
 447        /* See enum ssb_quirks */
 448        unsigned int quirks;
 449
 450#ifdef CONFIG_SSB_SPROM
 451        /* Mutex to protect the SPROM writing. */
 452        struct mutex sprom_mutex;
 453#endif
 454
 455        /* ID information about the Chip. */
 456        u16 chip_id;
 457        u8 chip_rev;
 458        u16 sprom_offset;
 459        u16 sprom_size;         /* number of words in sprom */
 460        u8 chip_package;
 461
 462        /* List of devices (cores) on the backplane. */
 463        struct ssb_device devices[SSB_MAX_NR_CORES];
 464        u8 nr_devices;
 465
 466        /* Software ID number for this bus. */
 467        unsigned int busnumber;
 468
 469        /* The ChipCommon device (if available). */
 470        struct ssb_chipcommon chipco;
 471        /* The PCI-core device (if available). */
 472        struct ssb_pcicore pcicore;
 473        /* The MIPS-core device (if available). */
 474        struct ssb_mipscore mipscore;
 475        /* The EXTif-core device (if available). */
 476        struct ssb_extif extif;
 477
 478        /* The following structure elements are not available in early
 479         * SSB initialization. Though, they are available for regular
 480         * registered drivers at any stage. So be careful when
 481         * using them in the ssb core code. */
 482
 483        /* ID information about the PCB. */
 484        struct ssb_boardinfo boardinfo;
 485        /* Contents of the SPROM. */
 486        struct ssb_sprom sprom;
 487        /* If the board has a cardbus slot, this is set to true. */
 488        bool has_cardbus_slot;
 489
 490#ifdef CONFIG_SSB_EMBEDDED
 491        /* Lock for GPIO register access. */
 492        spinlock_t gpio_lock;
 493        struct platform_device *watchdog;
 494#endif /* EMBEDDED */
 495#ifdef CONFIG_SSB_DRIVER_GPIO
 496        struct gpio_chip gpio;
 497        struct irq_domain *irq_domain;
 498#endif /* DRIVER_GPIO */
 499
 500        /* Internal-only stuff follows. Do not touch. */
 501        struct list_head list;
 502        /* Is the bus already powered up? */
 503        bool powered_up;
 504        int power_warn_count;
 505};
 506
 507enum ssb_quirks {
 508        /* SDIO connected card requires performing a read after writing a 32-bit value */
 509        SSB_QUIRK_SDIO_READ_AFTER_WRITE32       = (1 << 0),
 510};
 511
 512/* The initialization-invariants. */
 513struct ssb_init_invariants {
 514        /* Versioning information about the PCB. */
 515        struct ssb_boardinfo boardinfo;
 516        /* The SPROM information. That's either stored in an
 517         * EEPROM or NVRAM on the board. */
 518        struct ssb_sprom sprom;
 519        /* If the board has a cardbus slot, this is set to true. */
 520        bool has_cardbus_slot;
 521};
 522/* Type of function to fetch the invariants. */
 523typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
 524                                     struct ssb_init_invariants *iv);
 525
 526/* Register SoC bus. */
 527extern int ssb_bus_host_soc_register(struct ssb_bus *bus,
 528                                     unsigned long baseaddr);
 529#ifdef CONFIG_SSB_PCIHOST
 530extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
 531                                   struct pci_dev *host_pci);
 532#endif /* CONFIG_SSB_PCIHOST */
 533#ifdef CONFIG_SSB_PCMCIAHOST
 534extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
 535                                      struct pcmcia_device *pcmcia_dev,
 536                                      unsigned long baseaddr);
 537#endif /* CONFIG_SSB_PCMCIAHOST */
 538#ifdef CONFIG_SSB_SDIOHOST
 539extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
 540                                    struct sdio_func *sdio_func,
 541                                    unsigned int quirks);
 542#endif /* CONFIG_SSB_SDIOHOST */
 543
 544
 545extern void ssb_bus_unregister(struct ssb_bus *bus);
 546
 547/* Does the device have an SPROM? */
 548extern bool ssb_is_sprom_available(struct ssb_bus *bus);
 549
 550/* Set a fallback SPROM.
 551 * See kdoc at the function definition for complete documentation. */
 552extern int ssb_arch_register_fallback_sprom(
 553                int (*sprom_callback)(struct ssb_bus *bus,
 554                struct ssb_sprom *out));
 555
 556/* Suspend a SSB bus.
 557 * Call this from the parent bus suspend routine. */
 558extern int ssb_bus_suspend(struct ssb_bus *bus);
 559/* Resume a SSB bus.
 560 * Call this from the parent bus resume routine. */
 561extern int ssb_bus_resume(struct ssb_bus *bus);
 562
 563extern u32 ssb_clockspeed(struct ssb_bus *bus);
 564
 565/* Is the device enabled in hardware? */
 566int ssb_device_is_enabled(struct ssb_device *dev);
 567/* Enable a device and pass device-specific SSB_TMSLOW flags.
 568 * If no device-specific flags are available, use 0. */
 569void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
 570/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
 571void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
 572
 573
 574/* Device MMIO register read/write functions. */
 575static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
 576{
 577        return dev->ops->read8(dev, offset);
 578}
 579static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
 580{
 581        return dev->ops->read16(dev, offset);
 582}
 583static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
 584{
 585        return dev->ops->read32(dev, offset);
 586}
 587static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
 588{
 589        dev->ops->write8(dev, offset, value);
 590}
 591static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
 592{
 593        dev->ops->write16(dev, offset, value);
 594}
 595static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
 596{
 597        dev->ops->write32(dev, offset, value);
 598}
 599#ifdef CONFIG_SSB_BLOCKIO
 600static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
 601                                  size_t count, u16 offset, u8 reg_width)
 602{
 603        dev->ops->block_read(dev, buffer, count, offset, reg_width);
 604}
 605
 606static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
 607                                   size_t count, u16 offset, u8 reg_width)
 608{
 609        dev->ops->block_write(dev, buffer, count, offset, reg_width);
 610}
 611#endif /* CONFIG_SSB_BLOCKIO */
 612
 613
 614/* The SSB DMA API. Use this API for any DMA operation on the device.
 615 * This API basically is a wrapper that calls the correct DMA API for
 616 * the host device type the SSB device is attached to. */
 617
 618/* Translation (routing) bits that need to be ORed to DMA
 619 * addresses before they are given to a device. */
 620extern u32 ssb_dma_translation(struct ssb_device *dev);
 621#define SSB_DMA_TRANSLATION_MASK        0xC0000000
 622#define SSB_DMA_TRANSLATION_SHIFT       30
 623
 624static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
 625{
 626#ifdef CONFIG_SSB_DEBUG
 627        printk(KERN_ERR "SSB: BUG! Calling DMA API for "
 628               "unsupported bustype %d\n", dev->bus->bustype);
 629#endif /* DEBUG */
 630}
 631
 632#ifdef CONFIG_SSB_PCIHOST
 633/* PCI-host wrapper driver */
 634extern int ssb_pcihost_register(struct pci_driver *driver);
 635static inline void ssb_pcihost_unregister(struct pci_driver *driver)
 636{
 637        pci_unregister_driver(driver);
 638}
 639
 640static inline
 641void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
 642{
 643        if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
 644                pci_set_power_state(sdev->bus->host_pci, state);
 645}
 646#else
 647static inline void ssb_pcihost_unregister(struct pci_driver *driver)
 648{
 649}
 650
 651static inline
 652void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
 653{
 654}
 655#endif /* CONFIG_SSB_PCIHOST */
 656
 657
 658/* If a driver is shutdown or suspended, call this to signal
 659 * that the bus may be completely powered down. SSB will decide,
 660 * if it's really time to power down the bus, based on if there
 661 * are other devices that want to run. */
 662extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
 663/* Before initializing and enabling a device, call this to power-up the bus.
 664 * If you want to allow use of dynamic-power-control, pass the flag.
 665 * Otherwise static always-on powercontrol will be used. */
 666extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
 667
 668extern void ssb_commit_settings(struct ssb_bus *bus);
 669
 670/* Various helper functions */
 671extern u32 ssb_admatch_base(u32 adm);
 672extern u32 ssb_admatch_size(u32 adm);
 673
 674/* PCI device mapping and fixup routines.
 675 * Called from the architecture pcibios init code.
 676 * These are only available on SSB_EMBEDDED configurations. */
 677#ifdef CONFIG_SSB_EMBEDDED
 678int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
 679int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 680#endif /* CONFIG_SSB_EMBEDDED */
 681
 682#endif /* LINUX_SSB_H_ */
 683