1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * USB 338x super/high/full speed USB device controller. 4 * Unlike many such controllers, this one talks PCI. 5 * 6 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 7 * Copyright (C) 2003 David Brownell 8 * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#ifndef __LINUX_USB_USB338X_H 23#define __LINUX_USB_USB338X_H 24 25#include <linux/usb/net2280.h> 26 27/* 28 * Extra defined bits for net2280 registers 29 */ 30#define SCRATCH 0x0b 31 32#define DEFECT7374_FSM_FIELD 28 33#define SUPER_SPEED 8 34#define DMA_REQUEST_OUTSTANDING 5 35#define DMA_PAUSE_DONE_INTERRUPT 26 36#define SET_ISOCHRONOUS_DELAY 24 37#define SET_SEL 22 38#define SUPER_SPEED_MODE 8 39 40/*ep_cfg*/ 41#define MAX_BURST_SIZE 24 42#define EP_FIFO_BYTE_COUNT 16 43#define IN_ENDPOINT_ENABLE 14 44#define IN_ENDPOINT_TYPE 12 45#define OUT_ENDPOINT_ENABLE 10 46#define OUT_ENDPOINT_TYPE 8 47#define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \ 48 BIT(IN_ENDPOINT_ENABLE)) 49#define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \ 50 BIT(OUT_ENDPOINT_ENABLE)) 51 52struct usb338x_usb_ext_regs { 53 u32 usbclass; 54#define DEVICE_PROTOCOL 16 55#define DEVICE_SUB_CLASS 8 56#define DEVICE_CLASS 0 57 u32 ss_sel; 58#define U2_SYSTEM_EXIT_LATENCY 8 59#define U1_SYSTEM_EXIT_LATENCY 0 60 u32 ss_del; 61#define U2_DEVICE_EXIT_LATENCY 8 62#define U1_DEVICE_EXIT_LATENCY 0 63 u32 usb2lpm; 64#define USB_L1_LPM_HIRD 2 65#define USB_L1_LPM_REMOTE_WAKE 1 66#define USB_L1_LPM_SUPPORT 0 67 u32 usb3belt; 68#define BELT_MULTIPLIER 10 69#define BEST_EFFORT_LATENCY_TOLERANCE 0 70 u32 usbctl2; 71#define LTM_ENABLE 7 72#define U2_ENABLE 6 73#define U1_ENABLE 5 74#define FUNCTION_SUSPEND 4 75#define USB3_CORE_ENABLE 3 76#define USB2_CORE_ENABLE 2 77#define SERIAL_NUMBER_STRING_ENABLE 0 78 u32 in_timeout; 79#define GPEP3_TIMEOUT 19 80#define GPEP2_TIMEOUT 18 81#define GPEP1_TIMEOUT 17 82#define GPEP0_TIMEOUT 16 83#define GPEP3_TIMEOUT_VALUE 13 84#define GPEP3_TIMEOUT_ENABLE 12 85#define GPEP2_TIMEOUT_VALUE 9 86#define GPEP2_TIMEOUT_ENABLE 8 87#define GPEP1_TIMEOUT_VALUE 5 88#define GPEP1_TIMEOUT_ENABLE 4 89#define GPEP0_TIMEOUT_VALUE 1 90#define GPEP0_TIMEOUT_ENABLE 0 91 u32 isodelay; 92#define ISOCHRONOUS_DELAY 0 93} __packed; 94 95struct usb338x_fifo_regs { 96 /* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */ 97 u32 ep_fifo_size_base; 98#define IN_FIFO_BASE_ADDRESS 22 99#define IN_FIFO_SIZE 16 100#define OUT_FIFO_BASE_ADDRESS 6 101#define OUT_FIFO_SIZE 0 102 u32 ep_fifo_out_wrptr; 103 u32 ep_fifo_out_rdptr; 104 u32 ep_fifo_in_wrptr; 105 u32 ep_fifo_in_rdptr; 106 u32 unused[3]; 107} __packed; 108 109 110/* Link layer */ 111struct usb338x_ll_regs { 112 /* offset 0x700 */ 113 u32 ll_ltssm_ctrl1; 114 u32 ll_ltssm_ctrl2; 115 u32 ll_ltssm_ctrl3; 116 u32 unused1; 117 118 /* 0x710 */ 119 u32 unused2; 120 u32 ll_general_ctrl0; 121 u32 ll_general_ctrl1; 122#define PM_U3_AUTO_EXIT 29 123#define PM_U2_AUTO_EXIT 28 124#define PM_U1_AUTO_EXIT 27 125#define PM_FORCE_U2_ENTRY 26 126#define PM_FORCE_U1_ENTRY 25 127#define PM_LGO_COLLISION_SEND_LAU 24 128#define PM_DIR_LINK_REJECT 23 129#define PM_FORCE_LINK_ACCEPT 22 130#define PM_DIR_ENTRY_U3 20 131#define PM_DIR_ENTRY_U2 19 132#define PM_DIR_ENTRY_U1 18 133#define PM_U2_ENABLE 17 134#define PM_U1_ENABLE 16 135#define SKP_THRESHOLD_ADJUST_FMW 8 136#define RESEND_DPP_ON_LRTY_FMW 7 137#define DL_BIT_VALUE_FMW 6 138#define FORCE_DL_BIT 5 139 u32 ll_general_ctrl2; 140#define SELECT_INVERT_LANE_POLARITY 7 141#define FORCE_INVERT_LANE_POLARITY 6 142 143 /* 0x720 */ 144 u32 ll_general_ctrl3; 145 u32 ll_general_ctrl4; 146 u32 ll_error_gen; 147 u32 unused3; 148 149 /* 0x730 */ 150 u32 unused4[4]; 151 152 /* 0x740 */ 153 u32 unused5[2]; 154 u32 ll_lfps_5; 155#define TIMER_LFPS_6US 16 156 u32 ll_lfps_6; 157#define TIMER_LFPS_80US 0 158 159 /* 0x750 */ 160 u32 unused6[8]; 161 162 /* 0x770 */ 163 u32 unused7[3]; 164 u32 ll_tsn_counters_2; 165#define HOT_TX_NORESET_TS2 24 166 167 /* 0x780 */ 168 u32 ll_tsn_counters_3; 169#define HOT_RX_RESET_TS2 0 170 u32 unused8[3]; 171 172 /* 0x790 */ 173 u32 unused9; 174 u32 ll_lfps_timers_2; 175#define LFPS_TIMERS_2_WORKAROUND_VALUE 0x084d 176 u32 unused10; 177 u32 ll_tsn_chicken_bit; 178#define RECOVERY_IDLE_TO_RECOVER_FMW 3 179} __packed; 180 181/* protocol layer */ 182struct usb338x_pl_regs { 183 /* offset 0x800 */ 184 u32 pl_reg_1; 185 u32 pl_reg_2; 186 u32 pl_reg_3; 187 u32 pl_reg_4; 188 u32 pl_ep_ctrl; 189 /* Protocol Layer Endpoint Control*/ 190#define PL_EP_CTRL 0x810 191#define ENDPOINT_SELECT 0 192 /* [4:0] */ 193#define EP_INITIALIZED 16 194#define SEQUENCE_NUMBER_RESET 17 195#define CLEAR_ACK_ERROR_CODE 20 196 u32 pl_reg_6; 197 u32 pl_reg_7; 198 u32 pl_reg_8; 199 u32 pl_ep_status_1; 200 /* Protocol Layer Endpoint Status 1*/ 201#define PL_EP_STATUS_1 0x820 202#define STATE 16 203#define ACK_GOOD_NORMAL 0x11 204#define ACK_GOOD_MORE_ACKS_TO_COME 0x16 205 u32 pl_ep_status_2; 206 u32 pl_ep_status_3; 207 /* Protocol Layer Endpoint Status 3*/ 208#define PL_EP_STATUS_3 0x828 209#define SEQUENCE_NUMBER 0 210 u32 pl_ep_status_4; 211 /* Protocol Layer Endpoint Status 4*/ 212#define PL_EP_STATUS_4 0x82c 213 u32 pl_ep_cfg_4; 214 /* Protocol Layer Endpoint Configuration 4*/ 215#define PL_EP_CFG_4 0x830 216#define NON_CTRL_IN_TOLERATE_BAD_DIR 6 217} __packed; 218 219#endif /* __LINUX_USB_USB338X_H */ 220