LXR linux/include/soc/fsl/qe/ucc

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
   4 *
   5 * Authors:     Shlomi Gridish <gridish@freescale.com>
   6 *              Li Yang <leoli@freescale.com>
   7 *
   8 * Description:
   9 * Internal header file for UCC SLOW unit routines.
  10 */
  11#ifndef __UCC_SLOW_H__
  12#define __UCC_SLOW_H__
  13
  14#include <linux/kernel.h>
  15
  16#include <soc/fsl/qe/immap_qe.h>
  17#include <soc/fsl/qe/qe.h>
  18
  19#include <soc/fsl/qe/ucc.h>
  20
  21/* transmit BD's status */
  22#define T_R     0x80000000      /* ready bit */
  23#define T_PAD   0x40000000      /* add pads to short frames */
  24#define T_W     0x20000000      /* wrap bit */
  25#define T_I     0x10000000      /* interrupt on completion */
  26#define T_L     0x08000000      /* last */
  27
  28#define T_A     0x04000000      /* Address - the data transmitted as address
  29                                   chars */
  30#define T_TC    0x04000000      /* transmit CRC */
  31#define T_CM    0x02000000      /* continuous mode */
  32#define T_DEF   0x02000000      /* collision on previous attempt to transmit */
  33#define T_P     0x01000000      /* Preamble - send Preamble sequence before
  34                                   data */
  35#define T_HB    0x01000000      /* heartbeat */
  36#define T_NS    0x00800000      /* No Stop */
  37#define T_LC    0x00800000      /* late collision */
  38#define T_RL    0x00400000      /* retransmission limit */
  39#define T_UN    0x00020000      /* underrun */
  40#define T_CT    0x00010000      /* CTS lost */
  41#define T_CSL   0x00010000      /* carrier sense lost */
  42#define T_RC    0x003c0000      /* retry count */
  43
  44/* Receive BD's status */
  45#define R_E     0x80000000      /* buffer empty */
  46#define R_W     0x20000000      /* wrap bit */
  47#define R_I     0x10000000      /* interrupt on reception */
  48#define R_L     0x08000000      /* last */
  49#define R_C     0x08000000      /* the last byte in this buffer is a cntl
  50                                   char */
  51#define R_F     0x04000000      /* first */
  52#define R_A     0x04000000      /* the first byte in this buffer is address
  53                                   byte */
  54#define R_CM    0x02000000      /* continuous mode */
  55#define R_ID    0x01000000      /* buffer close on reception of idles */
  56#define R_M     0x01000000      /* Frame received because of promiscuous
  57                                   mode */
  58#define R_AM    0x00800000      /* Address match */
  59#define R_DE    0x00800000      /* Address match */
  60#define R_LG    0x00200000      /* Break received */
  61#define R_BR    0x00200000      /* Frame length violation */
  62#define R_NO    0x00100000      /* Rx Non Octet Aligned Packet */
  63#define R_FR    0x00100000      /* Framing Error (no stop bit) character
  64                                   received */
  65#define R_PR    0x00080000      /* Parity Error character received */
  66#define R_AB    0x00080000      /* Frame Aborted */
  67#define R_SH    0x00080000      /* frame is too short */
  68#define R_CR    0x00040000      /* CRC Error */
  69#define R_OV    0x00020000      /* Overrun */
  70#define R_CD    0x00010000      /* CD lost */
  71#define R_CL    0x00010000      /* this frame is closed because of a
  72                                   collision */
  73
  74/* Rx Data buffer must be 4 bytes aligned in most cases.*/
  75#define UCC_SLOW_RX_ALIGN               4
  76#define UCC_SLOW_MRBLR_ALIGNMENT        4
  77#define UCC_SLOW_PRAM_SIZE              0x100
  78#define ALIGNMENT_OF_UCC_SLOW_PRAM      64
  79
  80/* UCC Slow Channel Protocol Mode */
  81enum ucc_slow_channel_protocol_mode {
  82        UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
  83        UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
  84        UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
  85};
  86
  87/* UCC Slow Transparent Transmit CRC (TCRC) */
  88enum ucc_slow_transparent_tcrc {
  89        /* 16-bit CCITT CRC (HDLC).  (X16 + X12 + X5 + 1) */
  90        UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
  91        /* CRC16 (BISYNC).  (X16 + X15 + X2 + 1) */
  92        UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
  93        /* 32-bit CCITT CRC (Ethernet and HDLC) */
  94        UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
  95};
  96
  97/* UCC Slow oversampling rate for transmitter (TDCR) */
  98enum ucc_slow_tx_oversampling_rate {
  99        /* 1x clock mode */
 100        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
 101        /* 8x clock mode */
 102        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
 103        /* 16x clock mode */
 104        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
 105        /* 32x clock mode */
 106        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
 107};
 108
 109/* UCC Slow Oversampling rate for receiver (RDCR)
 110*/
 111enum ucc_slow_rx_oversampling_rate {
 112        /* 1x clock mode */
 113        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
 114        /* 8x clock mode */
 115        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
 116        /* 16x clock mode */
 117        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
 118        /* 32x clock mode */
 119        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
 120};
 121
 122/* UCC Slow Transmitter encoding method (TENC)
 123*/
 124enum ucc_slow_tx_encoding_method {
 125        UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
 126        UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
 127};
 128
 129/* UCC Slow Receiver decoding method (RENC)
 130*/
 131enum ucc_slow_rx_decoding_method {
 132        UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
 133        UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
 134};
 135
 136/* UCC Slow Diagnostic mode (DIAG)
 137*/
 138enum ucc_slow_diag_mode {
 139        UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
 140        UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
 141        UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
 142        UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
 143};
 144
 145struct ucc_slow_info {
 146        int ucc_num;
 147        int protocol;                   /* QE_CR_PROTOCOL_xxx */
 148        enum qe_clock rx_clock;
 149        enum qe_clock tx_clock;
 150        phys_addr_t regs;
 151        int irq;
 152        u16 uccm_mask;
 153        int data_mem_part;
 154        int init_tx;
 155        int init_rx;
 156        u32 tx_bd_ring_len;
 157        u32 rx_bd_ring_len;
 158        int rx_interrupts;
 159        int brkpt_support;
 160        int grant_support;
 161        int tsa;
 162        int cdp;
 163        int cds;
 164        int ctsp;
 165        int ctss;
 166        int rinv;
 167        int tinv;
 168        int rtsm;
 169        int rfw;
 170        int tci;
 171        int tend;
 172        int tfl;
 173        int txsy;
 174        u16 max_rx_buf_length;
 175        enum ucc_slow_transparent_tcrc tcrc;
 176        enum ucc_slow_channel_protocol_mode mode;
 177        enum ucc_slow_diag_mode diag;
 178        enum ucc_slow_tx_oversampling_rate tdcr;
 179        enum ucc_slow_rx_oversampling_rate rdcr;
 180        enum ucc_slow_tx_encoding_method tenc;
 181        enum ucc_slow_rx_decoding_method renc;
 182};
 183
 184struct ucc_slow_private {
 185        struct ucc_slow_info *us_info;
 186        struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
 187        struct ucc_slow_pram __iomem *us_pram;  /* a pointer to the parameter RAM */
 188        s32 us_pram_offset;
 189        int enabled_tx;         /* Whether channel is enabled for Tx (ENT) */
 190        int enabled_rx;         /* Whether channel is enabled for Rx (ENR) */
 191        int stopped_tx;         /* Whether channel has been stopped for Tx
 192                                   (STOP_TX, etc.) */
 193        int stopped_rx;         /* Whether channel has been stopped for Rx */
 194        struct list_head confQ; /* frames passed to chip waiting for tx */
 195        u32 first_tx_bd_mask;   /* mask is used in Tx routine to save status
 196                                   and length for first BD in a frame */
 197        s32 tx_base_offset;     /* first BD in Tx BD table offset (In MURAM) */
 198        s32 rx_base_offset;     /* first BD in Rx BD table offset (In MURAM) */
 199        struct qe_bd __iomem *confBd;   /* next BD for confirm after Tx */
 200        struct qe_bd __iomem *tx_bd;    /* next BD for new Tx request */
 201        struct qe_bd __iomem *rx_bd;    /* next BD to collect after Rx */
 202        void *p_rx_frame;       /* accumulating receive frame */
 203        __be16 __iomem *p_ucce; /* a pointer to the event register in memory */
 204        __be16 __iomem *p_uccm; /* a pointer to the mask register in memory */
 205        u16 saved_uccm;         /* a saved mask for the RX Interrupt bits */
 206#ifdef STATISTICS
 207        u32 tx_frames;          /* Transmitted frames counters */
 208        u32 rx_frames;          /* Received frames counters (only frames
 209                                   passed to application) */
 210        u32 rx_discarded;       /* Discarded frames counters (frames that
 211                                   were discarded by the driver due to
 212                                   errors) */
 213#endif                          /* STATISTICS */
 214};
 215
 216/* ucc_slow_init
 217 * Initializes Slow UCC according to provided parameters.
 218 *
 219 * us_info  - (In) pointer to the slow UCC info structure.
 220 * uccs_ret - (Out) pointer to the slow UCC structure.
 221 */
 222int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
 223
 224/* ucc_slow_free
 225 * Frees all resources for slow UCC.
 226 *
 227 * uccs - (In) pointer to the slow UCC structure.
 228 */
 229void ucc_slow_free(struct ucc_slow_private * uccs);
 230
 231/* ucc_slow_enable
 232 * Enables a fast UCC port.
 233 * This routine enables Tx and/or Rx through the General UCC Mode Register.
 234 *
 235 * uccs - (In) pointer to the slow UCC structure.
 236 * mode - (In) TX, RX, or both.
 237 */
 238void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
 239
 240/* ucc_slow_disable
 241 * Disables a fast UCC port.
 242 * This routine disables Tx and/or Rx through the General UCC Mode Register.
 243 *
 244 * uccs - (In) pointer to the slow UCC structure.
 245 * mode - (In) TX, RX, or both.
 246 */
 247void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
 248
 249/* ucc_slow_graceful_stop_tx
 250 * Smoothly stops transmission on a specified slow UCC.
 251 *
 252 * uccs - (In) pointer to the slow UCC structure.
 253 */
 254void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
 255
 256/* ucc_slow_stop_tx
 257 * Stops transmission on a specified slow UCC.
 258 *
 259 * uccs - (In) pointer to the slow UCC structure.
 260 */
 261void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
 262
 263/* ucc_slow_restart_tx
 264 * Restarts transmitting on a specified slow UCC.
 265 *
 266 * uccs - (In) pointer to the slow UCC structure.
 267 */
 268void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
 269
 270u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
 271
 272#endif                          /* __UCC_SLOW_H__ */
 273