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6#ifndef _OCELOT_VCAP_H_
7#define _OCELOT_VCAP_H_
8
9#include <soc/mscc/ocelot.h>
10
11
12
13
14
15
16enum {
17 VCAP_ES0,
18 VCAP_IS1,
19 VCAP_IS2,
20 __VCAP_COUNT,
21};
22
23#define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT
24
25struct vcap_props {
26 u16 tg_width;
27 u16 sw_count;
28 u16 entry_count;
29 u16 entry_words;
30 u16 entry_width;
31 u16 action_count;
32 u16 action_words;
33 u16 action_width;
34 u16 action_type_width;
35 struct {
36 u16 width;
37 u16 count;
38 } action_table[2];
39 u16 counter_words;
40 u16 counter_width;
41
42 enum ocelot_target target;
43
44 const struct vcap_field *keys;
45 const struct vcap_field *actions;
46};
47
48
49#define VCAP_TG_NONE 0
50#define VCAP_TG_FULL 1
51#define VCAP_TG_HALF 2
52#define VCAP_TG_QUARTER 3
53
54#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
55#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
56#define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
57#define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
58#define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
59#define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
60#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
61#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
62#define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
63#define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
64#define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
65#define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
66
67#define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
68#define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
69#define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
70#define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
71#define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
72
73#define VCAP_CACHE_ENTRY_DAT_RSZ 0x4
74
75#define VCAP_CACHE_MASK_DAT_RSZ 0x4
76
77#define VCAP_CACHE_ACTION_DAT_RSZ 0x4
78
79#define VCAP_CACHE_CNT_DAT_RSZ 0x4
80
81#define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
82
83#define TCAM_BIST_CTRL_TCAM_BIST BIT(1)
84#define TCAM_BIST_CTRL_TCAM_INIT BIT(0)
85
86#define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
87#define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7)
88#define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6)
89#define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
90#define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
91
92#define TCAM_BIST_STAT_BIST_RT_ERR BIT(15)
93#define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14)
94#define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13)
95#define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12)
96#define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11)
97#define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10)
98#define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9)
99#define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8)
100#define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7)
101#define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6)
102#define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5)
103#define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4)
104#define TCAM_BIST_STAT_BIST_RUN BIT(3)
105#define TCAM_BIST_STAT_BIST_ERR BIT(2)
106#define TCAM_BIST_STAT_BIST_BUSY BIT(1)
107#define TCAM_BIST_STAT_TCAM_RDY BIT(0)
108
109
110
111
112
113
114
115#define IS2_TYPE_ETYPE 0
116#define IS2_TYPE_LLC 1
117#define IS2_TYPE_SNAP 2
118#define IS2_TYPE_ARP 3
119#define IS2_TYPE_IP_UDP_TCP 4
120#define IS2_TYPE_IP_OTHER 5
121#define IS2_TYPE_IPV6 6
122#define IS2_TYPE_OAM 7
123#define IS2_TYPE_SMAC_SIP6 8
124#define IS2_TYPE_ANY 100
125
126
127#define IS2_TYPE_MASK_IP_ANY 0xe
128
129enum {
130 IS2_ACTION_TYPE_NORMAL,
131 IS2_ACTION_TYPE_SMAC_SIP,
132 IS2_ACTION_TYPE_MAX,
133};
134
135
136#define IS2_ACT_MASK_MODE_NONE 0
137#define IS2_ACT_MASK_MODE_FILTER 1
138#define IS2_ACT_MASK_MODE_POLICY 2
139#define IS2_ACT_MASK_MODE_REDIR 3
140
141
142#define IS2_ACT_REW_OP_NONE 0
143#define IS2_ACT_REW_OP_PTP_ONE 2
144#define IS2_ACT_REW_OP_PTP_TWO 3
145#define IS2_ACT_REW_OP_SPECIAL 8
146#define IS2_ACT_REW_OP_PTP_ORG 9
147#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
148#define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
149#define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
150#define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
151
152#define VCAP_PORT_WIDTH 4
153
154
155#define IS2_QKO_IGR_PORT 0
156#define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
157#define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
158#define IS2_QKL_L2_SMAC 48
159#define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
160#define IS2_QKL_L3_IP4_SIP 32
161
162enum vcap_is2_half_key_field {
163
164 VCAP_IS2_TYPE,
165 VCAP_IS2_HK_FIRST,
166 VCAP_IS2_HK_PAG,
167 VCAP_IS2_HK_RSV1,
168 VCAP_IS2_HK_IGR_PORT_MASK,
169 VCAP_IS2_HK_RSV2,
170 VCAP_IS2_HK_HOST_MATCH,
171 VCAP_IS2_HK_L2_MC,
172 VCAP_IS2_HK_L2_BC,
173 VCAP_IS2_HK_VLAN_TAGGED,
174 VCAP_IS2_HK_VID,
175 VCAP_IS2_HK_DEI,
176 VCAP_IS2_HK_PCP,
177
178 VCAP_IS2_HK_L2_DMAC,
179 VCAP_IS2_HK_L2_SMAC,
180
181 VCAP_IS2_HK_MAC_ETYPE_ETYPE,
182 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
183 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
184 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
185
186 VCAP_IS2_HK_MAC_LLC_DMAC,
187 VCAP_IS2_HK_MAC_LLC_SMAC,
188 VCAP_IS2_HK_MAC_LLC_L2_LLC,
189
190 VCAP_IS2_HK_MAC_SNAP_SMAC,
191 VCAP_IS2_HK_MAC_SNAP_DMAC,
192 VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
193
194 VCAP_IS2_HK_MAC_ARP_SMAC,
195 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
196 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
197 VCAP_IS2_HK_MAC_ARP_LEN_OK,
198 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
199 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
200 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
201 VCAP_IS2_HK_MAC_ARP_OPCODE,
202 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
203 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
204 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
205
206 VCAP_IS2_HK_IP4,
207 VCAP_IS2_HK_L3_FRAGMENT,
208 VCAP_IS2_HK_L3_FRAG_OFS_GT0,
209 VCAP_IS2_HK_L3_OPTIONS,
210 VCAP_IS2_HK_IP4_L3_TTL_GT0,
211 VCAP_IS2_HK_L3_TOS,
212 VCAP_IS2_HK_L3_IP4_DIP,
213 VCAP_IS2_HK_L3_IP4_SIP,
214 VCAP_IS2_HK_DIP_EQ_SIP,
215
216 VCAP_IS2_HK_TCP,
217 VCAP_IS2_HK_L4_SPORT,
218 VCAP_IS2_HK_L4_DPORT,
219 VCAP_IS2_HK_L4_RNG,
220 VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
221 VCAP_IS2_HK_L4_SEQUENCE_EQ0,
222 VCAP_IS2_HK_L4_URG,
223 VCAP_IS2_HK_L4_ACK,
224 VCAP_IS2_HK_L4_PSH,
225 VCAP_IS2_HK_L4_RST,
226 VCAP_IS2_HK_L4_SYN,
227 VCAP_IS2_HK_L4_FIN,
228 VCAP_IS2_HK_L4_1588_DOM,
229 VCAP_IS2_HK_L4_1588_VER,
230
231 VCAP_IS2_HK_IP4_L3_PROTO,
232 VCAP_IS2_HK_L3_PAYLOAD,
233
234 VCAP_IS2_HK_IP6_L3_TTL_GT0,
235 VCAP_IS2_HK_IP6_L3_PROTO,
236 VCAP_IS2_HK_L3_IP6_SIP,
237
238 VCAP_IS2_HK_OAM_MEL_FLAGS,
239 VCAP_IS2_HK_OAM_VER,
240 VCAP_IS2_HK_OAM_OPCODE,
241 VCAP_IS2_HK_OAM_FLAGS,
242 VCAP_IS2_HK_OAM_MEPID,
243 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0,
244 VCAP_IS2_HK_OAM_IS_Y1731,
245};
246
247struct vcap_field {
248 int offset;
249 int length;
250};
251
252enum vcap_is2_action_field {
253 VCAP_IS2_ACT_HIT_ME_ONCE,
254 VCAP_IS2_ACT_CPU_COPY_ENA,
255 VCAP_IS2_ACT_CPU_QU_NUM,
256 VCAP_IS2_ACT_MASK_MODE,
257 VCAP_IS2_ACT_MIRROR_ENA,
258 VCAP_IS2_ACT_LRN_DIS,
259 VCAP_IS2_ACT_POLICE_ENA,
260 VCAP_IS2_ACT_POLICE_IDX,
261 VCAP_IS2_ACT_POLICE_VCAP_ONLY,
262 VCAP_IS2_ACT_PORT_MASK,
263 VCAP_IS2_ACT_REW_OP,
264 VCAP_IS2_ACT_SMAC_REPLACE_ENA,
265 VCAP_IS2_ACT_RSV,
266 VCAP_IS2_ACT_ACL_ID,
267 VCAP_IS2_ACT_HIT_CNT,
268};
269
270
271
272
273
274
275
276#define IS1_TYPE_S1_NORMAL 0
277#define IS1_TYPE_S1_5TUPLE_IP4 1
278
279
280#define IS1_TYPE_S1_NORMAL_IP6 0
281#define IS1_TYPE_S1_7TUPLE 1
282#define IS2_TYPE_S1_5TUPLE_IP6 2
283
284enum {
285 IS1_ACTION_TYPE_NORMAL,
286 IS1_ACTION_TYPE_MAX,
287};
288
289enum vcap_is1_half_key_field {
290 VCAP_IS1_HK_TYPE,
291 VCAP_IS1_HK_LOOKUP,
292 VCAP_IS1_HK_IGR_PORT_MASK,
293 VCAP_IS1_HK_RSV,
294 VCAP_IS1_HK_OAM_Y1731,
295 VCAP_IS1_HK_L2_MC,
296 VCAP_IS1_HK_L2_BC,
297 VCAP_IS1_HK_IP_MC,
298 VCAP_IS1_HK_VLAN_TAGGED,
299 VCAP_IS1_HK_VLAN_DBL_TAGGED,
300 VCAP_IS1_HK_TPID,
301 VCAP_IS1_HK_VID,
302 VCAP_IS1_HK_DEI,
303 VCAP_IS1_HK_PCP,
304
305 VCAP_IS1_HK_L2_SMAC,
306 VCAP_IS1_HK_ETYPE_LEN,
307 VCAP_IS1_HK_ETYPE,
308 VCAP_IS1_HK_IP_SNAP,
309 VCAP_IS1_HK_IP4,
310 VCAP_IS1_HK_L3_FRAGMENT,
311 VCAP_IS1_HK_L3_FRAG_OFS_GT0,
312 VCAP_IS1_HK_L3_OPTIONS,
313 VCAP_IS1_HK_L3_DSCP,
314 VCAP_IS1_HK_L3_IP4_SIP,
315 VCAP_IS1_HK_TCP_UDP,
316 VCAP_IS1_HK_TCP,
317 VCAP_IS1_HK_L4_SPORT,
318 VCAP_IS1_HK_L4_RNG,
319
320 VCAP_IS1_HK_IP4_INNER_TPID,
321 VCAP_IS1_HK_IP4_INNER_VID,
322 VCAP_IS1_HK_IP4_INNER_DEI,
323 VCAP_IS1_HK_IP4_INNER_PCP,
324 VCAP_IS1_HK_IP4_IP4,
325 VCAP_IS1_HK_IP4_L3_FRAGMENT,
326 VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0,
327 VCAP_IS1_HK_IP4_L3_OPTIONS,
328 VCAP_IS1_HK_IP4_L3_DSCP,
329 VCAP_IS1_HK_IP4_L3_IP4_DIP,
330 VCAP_IS1_HK_IP4_L3_IP4_SIP,
331 VCAP_IS1_HK_IP4_L3_PROTO,
332 VCAP_IS1_HK_IP4_TCP_UDP,
333 VCAP_IS1_HK_IP4_TCP,
334 VCAP_IS1_HK_IP4_L4_RNG,
335 VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE,
336};
337
338enum vcap_is1_action_field {
339 VCAP_IS1_ACT_DSCP_ENA,
340 VCAP_IS1_ACT_DSCP_VAL,
341 VCAP_IS1_ACT_QOS_ENA,
342 VCAP_IS1_ACT_QOS_VAL,
343 VCAP_IS1_ACT_DP_ENA,
344 VCAP_IS1_ACT_DP_VAL,
345 VCAP_IS1_ACT_PAG_OVERRIDE_MASK,
346 VCAP_IS1_ACT_PAG_VAL,
347 VCAP_IS1_ACT_RSV,
348 VCAP_IS1_ACT_VID_REPLACE_ENA,
349 VCAP_IS1_ACT_VID_ADD_VAL,
350 VCAP_IS1_ACT_FID_SEL,
351 VCAP_IS1_ACT_FID_VAL,
352 VCAP_IS1_ACT_PCP_DEI_ENA,
353 VCAP_IS1_ACT_PCP_VAL,
354 VCAP_IS1_ACT_DEI_VAL,
355 VCAP_IS1_ACT_VLAN_POP_CNT_ENA,
356 VCAP_IS1_ACT_VLAN_POP_CNT,
357 VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA,
358 VCAP_IS1_ACT_HIT_STICKY,
359};
360
361
362
363
364
365
366enum {
367 ES0_ACTION_TYPE_NORMAL,
368 ES0_ACTION_TYPE_MAX,
369};
370
371enum vcap_es0_key_field {
372 VCAP_ES0_EGR_PORT,
373 VCAP_ES0_IGR_PORT,
374 VCAP_ES0_RSV,
375 VCAP_ES0_L2_MC,
376 VCAP_ES0_L2_BC,
377 VCAP_ES0_VID,
378 VCAP_ES0_DP,
379 VCAP_ES0_PCP,
380};
381
382enum vcap_es0_action_field {
383 VCAP_ES0_ACT_PUSH_OUTER_TAG,
384 VCAP_ES0_ACT_PUSH_INNER_TAG,
385 VCAP_ES0_ACT_TAG_A_TPID_SEL,
386 VCAP_ES0_ACT_TAG_A_VID_SEL,
387 VCAP_ES0_ACT_TAG_A_PCP_SEL,
388 VCAP_ES0_ACT_TAG_A_DEI_SEL,
389 VCAP_ES0_ACT_TAG_B_TPID_SEL,
390 VCAP_ES0_ACT_TAG_B_VID_SEL,
391 VCAP_ES0_ACT_TAG_B_PCP_SEL,
392 VCAP_ES0_ACT_TAG_B_DEI_SEL,
393 VCAP_ES0_ACT_VID_A_VAL,
394 VCAP_ES0_ACT_PCP_A_VAL,
395 VCAP_ES0_ACT_DEI_A_VAL,
396 VCAP_ES0_ACT_VID_B_VAL,
397 VCAP_ES0_ACT_PCP_B_VAL,
398 VCAP_ES0_ACT_DEI_B_VAL,
399 VCAP_ES0_ACT_RSV,
400 VCAP_ES0_ACT_HIT_STICKY,
401};
402
403struct ocelot_ipv4 {
404 u8 addr[4];
405};
406
407enum ocelot_vcap_bit {
408 OCELOT_VCAP_BIT_ANY,
409 OCELOT_VCAP_BIT_0,
410 OCELOT_VCAP_BIT_1
411};
412
413struct ocelot_vcap_u8 {
414 u8 value[1];
415 u8 mask[1];
416};
417
418struct ocelot_vcap_u16 {
419 u8 value[2];
420 u8 mask[2];
421};
422
423struct ocelot_vcap_u24 {
424 u8 value[3];
425 u8 mask[3];
426};
427
428struct ocelot_vcap_u32 {
429 u8 value[4];
430 u8 mask[4];
431};
432
433struct ocelot_vcap_u40 {
434 u8 value[5];
435 u8 mask[5];
436};
437
438struct ocelot_vcap_u48 {
439 u8 value[6];
440 u8 mask[6];
441};
442
443struct ocelot_vcap_u64 {
444 u8 value[8];
445 u8 mask[8];
446};
447
448struct ocelot_vcap_u128 {
449 u8 value[16];
450 u8 mask[16];
451};
452
453struct ocelot_vcap_vid {
454 u16 value;
455 u16 mask;
456};
457
458struct ocelot_vcap_ipv4 {
459 struct ocelot_ipv4 value;
460 struct ocelot_ipv4 mask;
461};
462
463struct ocelot_vcap_udp_tcp {
464 u16 value;
465 u16 mask;
466};
467
468struct ocelot_vcap_port {
469 u8 value;
470 u8 mask;
471};
472
473enum ocelot_vcap_key_type {
474 OCELOT_VCAP_KEY_ANY,
475 OCELOT_VCAP_KEY_ETYPE,
476 OCELOT_VCAP_KEY_LLC,
477 OCELOT_VCAP_KEY_SNAP,
478 OCELOT_VCAP_KEY_ARP,
479 OCELOT_VCAP_KEY_IPV4,
480 OCELOT_VCAP_KEY_IPV6
481};
482
483struct ocelot_vcap_key_vlan {
484 struct ocelot_vcap_vid vid;
485 struct ocelot_vcap_u8 pcp;
486 enum ocelot_vcap_bit dei;
487 enum ocelot_vcap_bit tagged;
488};
489
490struct ocelot_vcap_key_etype {
491 struct ocelot_vcap_u48 dmac;
492 struct ocelot_vcap_u48 smac;
493 struct ocelot_vcap_u16 etype;
494 struct ocelot_vcap_u16 data;
495};
496
497struct ocelot_vcap_key_llc {
498 struct ocelot_vcap_u48 dmac;
499 struct ocelot_vcap_u48 smac;
500
501
502 struct ocelot_vcap_u32 llc;
503};
504
505struct ocelot_vcap_key_snap {
506 struct ocelot_vcap_u48 dmac;
507 struct ocelot_vcap_u48 smac;
508
509
510 struct ocelot_vcap_u40 snap;
511};
512
513struct ocelot_vcap_key_arp {
514 struct ocelot_vcap_u48 smac;
515 enum ocelot_vcap_bit arp;
516 enum ocelot_vcap_bit req;
517 enum ocelot_vcap_bit unknown;
518 enum ocelot_vcap_bit smac_match;
519 enum ocelot_vcap_bit dmac_match;
520
521
522 enum ocelot_vcap_bit length;
523
524 enum ocelot_vcap_bit ip;
525 enum ocelot_vcap_bit ethernet;
526 struct ocelot_vcap_ipv4 sip;
527 struct ocelot_vcap_ipv4 dip;
528};
529
530struct ocelot_vcap_key_ipv4 {
531 enum ocelot_vcap_bit ttl;
532 enum ocelot_vcap_bit fragment;
533 enum ocelot_vcap_bit options;
534 struct ocelot_vcap_u8 ds;
535 struct ocelot_vcap_u8 proto;
536 struct ocelot_vcap_ipv4 sip;
537 struct ocelot_vcap_ipv4 dip;
538 struct ocelot_vcap_u48 data;
539 struct ocelot_vcap_udp_tcp sport;
540 struct ocelot_vcap_udp_tcp dport;
541 enum ocelot_vcap_bit tcp_fin;
542 enum ocelot_vcap_bit tcp_syn;
543 enum ocelot_vcap_bit tcp_rst;
544 enum ocelot_vcap_bit tcp_psh;
545 enum ocelot_vcap_bit tcp_ack;
546 enum ocelot_vcap_bit tcp_urg;
547 enum ocelot_vcap_bit sip_eq_dip;
548 enum ocelot_vcap_bit sport_eq_dport;
549 enum ocelot_vcap_bit seq_zero;
550};
551
552struct ocelot_vcap_key_ipv6 {
553 struct ocelot_vcap_u8 proto;
554 struct ocelot_vcap_u128 sip;
555 struct ocelot_vcap_u128 dip;
556 enum ocelot_vcap_bit ttl;
557 struct ocelot_vcap_u8 ds;
558 struct ocelot_vcap_u48 data;
559 struct ocelot_vcap_udp_tcp sport;
560 struct ocelot_vcap_udp_tcp dport;
561 enum ocelot_vcap_bit tcp_fin;
562 enum ocelot_vcap_bit tcp_syn;
563 enum ocelot_vcap_bit tcp_rst;
564 enum ocelot_vcap_bit tcp_psh;
565 enum ocelot_vcap_bit tcp_ack;
566 enum ocelot_vcap_bit tcp_urg;
567 enum ocelot_vcap_bit sip_eq_dip;
568 enum ocelot_vcap_bit sport_eq_dport;
569 enum ocelot_vcap_bit seq_zero;
570};
571
572enum ocelot_mask_mode {
573 OCELOT_MASK_MODE_NONE,
574 OCELOT_MASK_MODE_PERMIT_DENY,
575 OCELOT_MASK_MODE_POLICY,
576 OCELOT_MASK_MODE_REDIRECT,
577};
578
579enum ocelot_es0_tag {
580 OCELOT_NO_ES0_TAG,
581 OCELOT_ES0_TAG,
582 OCELOT_FORCE_PORT_TAG,
583 OCELOT_FORCE_UNTAG,
584};
585
586enum ocelot_tag_tpid_sel {
587 OCELOT_TAG_TPID_SEL_8021Q,
588 OCELOT_TAG_TPID_SEL_8021AD,
589};
590
591struct ocelot_vcap_action {
592 union {
593
594 struct {
595 enum ocelot_es0_tag push_outer_tag;
596 enum ocelot_es0_tag push_inner_tag;
597 enum ocelot_tag_tpid_sel tag_a_tpid_sel;
598 int tag_a_vid_sel;
599 int tag_a_pcp_sel;
600 u16 vid_a_val;
601 u8 pcp_a_val;
602 u8 dei_a_val;
603 enum ocelot_tag_tpid_sel tag_b_tpid_sel;
604 int tag_b_vid_sel;
605 int tag_b_pcp_sel;
606 u16 vid_b_val;
607 u8 pcp_b_val;
608 u8 dei_b_val;
609 };
610
611
612 struct {
613 bool vid_replace_ena;
614 u16 vid;
615 bool vlan_pop_cnt_ena;
616 int vlan_pop_cnt;
617 bool pcp_dei_ena;
618 u8 pcp;
619 u8 dei;
620 bool qos_ena;
621 u8 qos_val;
622 u8 pag_override_mask;
623 u8 pag_val;
624 };
625
626
627 struct {
628 bool cpu_copy_ena;
629 u8 cpu_qu_num;
630 enum ocelot_mask_mode mask_mode;
631 unsigned long port_mask;
632 bool police_ena;
633 struct ocelot_policer pol;
634 u32 pol_ix;
635 };
636 };
637};
638
639struct ocelot_vcap_stats {
640 u64 bytes;
641 u64 pkts;
642 u64 used;
643};
644
645enum ocelot_vcap_filter_type {
646 OCELOT_VCAP_FILTER_DUMMY,
647 OCELOT_VCAP_FILTER_PAG,
648 OCELOT_VCAP_FILTER_OFFLOAD,
649};
650
651struct ocelot_vcap_id {
652 unsigned long cookie;
653 bool tc_offload;
654};
655
656struct ocelot_vcap_filter {
657 struct list_head list;
658
659 enum ocelot_vcap_filter_type type;
660 int block_id;
661 int goto_target;
662 int lookup;
663 u8 pag;
664 u16 prio;
665 struct ocelot_vcap_id id;
666
667 struct ocelot_vcap_action action;
668 struct ocelot_vcap_stats stats;
669
670 unsigned long ingress_port_mask;
671
672 struct ocelot_vcap_port ingress_port;
673 struct ocelot_vcap_port egress_port;
674
675 enum ocelot_vcap_bit dmac_mc;
676 enum ocelot_vcap_bit dmac_bc;
677 struct ocelot_vcap_key_vlan vlan;
678
679 enum ocelot_vcap_key_type key_type;
680 union {
681
682 struct ocelot_vcap_key_etype etype;
683 struct ocelot_vcap_key_llc llc;
684 struct ocelot_vcap_key_snap snap;
685 struct ocelot_vcap_key_arp arp;
686 struct ocelot_vcap_key_ipv4 ipv4;
687 struct ocelot_vcap_key_ipv6 ipv6;
688 } key;
689};
690
691int ocelot_vcap_filter_add(struct ocelot *ocelot,
692 struct ocelot_vcap_filter *rule,
693 struct netlink_ext_ack *extack);
694int ocelot_vcap_filter_del(struct ocelot *ocelot,
695 struct ocelot_vcap_filter *rule);
696struct ocelot_vcap_filter *
697ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block,
698 unsigned long cookie, bool tc_offload);
699
700#endif
701
