linux/include/soc/tegra/flowctrl.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Functions and macros to control the flowcontroller
   4 *
   5 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
   6 */
   7
   8#ifndef __SOC_TEGRA_FLOWCTRL_H__
   9#define __SOC_TEGRA_FLOWCTRL_H__
  10
  11#define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
  12#define FLOW_CTRL_WAITEVENT             (2 << 29)
  13#define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
  14#define FLOW_CTRL_JTAG_RESUME           (1 << 28)
  15#define FLOW_CTRL_SCLK_RESUME           (1 << 27)
  16#define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
  17#define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
  18#define FLOW_CTRL_HALT_LIC_IRQ          (1 << 11)
  19#define FLOW_CTRL_HALT_LIC_FIQ          (1 << 10)
  20#define FLOW_CTRL_HALT_GIC_IRQ          (1 << 9)
  21#define FLOW_CTRL_HALT_GIC_FIQ          (1 << 8)
  22#define FLOW_CTRL_CPU0_CSR              0x8
  23#define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
  24#define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
  25#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL  (1 << 13)
  26#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU   (1 << 12)
  27#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
  28                FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
  29                FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
  30#define FLOW_CTRL_CSR_ENABLE            (1 << 0)
  31#define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
  32#define FLOW_CTRL_CPU1_CSR              0x18
  33
  34#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0          (1 << 4)
  35#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP        (3 << 4)
  36#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP        0
  37
  38#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0          (1 << 8)
  39#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP        (0xF << 4)
  40#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP        (0xF << 8)
  41
  42#ifndef __ASSEMBLY__
  43#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
  44u32 flowctrl_read_cpu_csr(unsigned int cpuid);
  45void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
  46void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
  47
  48void flowctrl_cpu_suspend_enter(unsigned int cpuid);
  49void flowctrl_cpu_suspend_exit(unsigned int cpuid);
  50#else
  51static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
  52{
  53        return 0;
  54}
  55
  56static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
  57{
  58}
  59
  60static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
  61
  62static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
  63{
  64}
  65
  66static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
  67{
  68}
  69#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
  70#endif /* __ASSEMBLY */
  71#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
  72