1/* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#ifndef __MSM_DRM_H__ 26#define __MSM_DRM_H__ 27 28#include "drm.h" 29 30#if defined(__cplusplus) 31extern "C" { 32#endif 33 34/* Please note that modifications to all structs defined here are 35 * subject to backwards-compatibility constraints: 36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 37 * user/kernel compatibility 38 * 2) Keep fields aligned to their size 39 * 3) Because of how drm_ioctl() works, we can add new fields at 40 * the end of an ioctl if some care is taken: drm_ioctl() will 41 * zero out the new fields at the tail of the ioctl, so a zero 42 * value should have a backwards compatible meaning. And for 43 * output params, userspace won't see the newly added output 44 * fields.. so that has to be somehow ok. 45 */ 46 47#define MSM_PIPE_NONE 0x00 48#define MSM_PIPE_2D0 0x01 49#define MSM_PIPE_2D1 0x02 50#define MSM_PIPE_3D0 0x10 51 52/* The pipe-id just uses the lower bits, so can be OR'd with flags in 53 * the upper 16 bits (which could be extended further, if needed, maybe 54 * we extend/overload the pipe-id some day to deal with multiple rings, 55 * but even then I don't think we need the full lower 16 bits). 56 */ 57#define MSM_PIPE_ID_MASK 0xffff 58#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 59#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 60 61/* timeouts are specified in clock-monotonic absolute times (to simplify 62 * restarting interrupted ioctls). The following struct is logically the 63 * same as 'struct timespec' but 32/64b ABI safe. 64 */ 65struct drm_msm_timespec { 66 __s64 tv_sec; /* seconds */ 67 __s64 tv_nsec; /* nanoseconds */ 68}; 69 70#define MSM_PARAM_GPU_ID 0x01 71#define MSM_PARAM_GMEM_SIZE 0x02 72#define MSM_PARAM_CHIP_ID 0x03 73#define MSM_PARAM_MAX_FREQ 0x04 74#define MSM_PARAM_TIMESTAMP 0x05 75#define MSM_PARAM_GMEM_BASE 0x06 76#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */ 77#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */ 78#define MSM_PARAM_FAULTS 0x09 79#define MSM_PARAM_SUSPENDS 0x0a 80 81/* For backwards compat. The original support for preemption was based on 82 * a single ring per priority level so # of priority levels equals the # 83 * of rings. With drm/scheduler providing additional levels of priority, 84 * the number of priorities is greater than the # of rings. The param is 85 * renamed to better reflect this. 86 */ 87#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 88 89struct drm_msm_param { 90 __u32 pipe; /* in, MSM_PIPE_x */ 91 __u32 param; /* in, MSM_PARAM_x */ 92 __u64 value; /* out (get_param) or in (set_param) */ 93}; 94 95/* 96 * GEM buffers: 97 */ 98 99#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 100#define MSM_BO_GPU_READONLY 0x00000002 101#define MSM_BO_CACHE_MASK 0x000f0000 102/* cache modes */ 103#define MSM_BO_CACHED 0x00010000 104#define MSM_BO_WC 0x00020000 105#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */ 106#define MSM_BO_CACHED_COHERENT 0x080000 107 108#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 109 MSM_BO_GPU_READONLY | \ 110 MSM_BO_CACHE_MASK) 111 112struct drm_msm_gem_new { 113 __u64 size; /* in */ 114 __u32 flags; /* in, mask of MSM_BO_x */ 115 __u32 handle; /* out */ 116}; 117 118/* Get or set GEM buffer info. The requested value can be passed 119 * directly in 'value', or for data larger than 64b 'value' is a 120 * pointer to userspace buffer, with 'len' specifying the number of 121 * bytes copied into that buffer. For info returned by pointer, 122 * calling the GEM_INFO ioctl with null 'value' will return the 123 * required buffer size in 'len' 124 */ 125#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */ 126#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */ 127#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */ 128#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */ 129 130struct drm_msm_gem_info { 131 __u32 handle; /* in */ 132 __u32 info; /* in - one of MSM_INFO_* */ 133 __u64 value; /* in or out */ 134 __u32 len; /* in or out */ 135 __u32 pad; 136}; 137 138#define MSM_PREP_READ 0x01 139#define MSM_PREP_WRITE 0x02 140#define MSM_PREP_NOSYNC 0x04 141 142#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 143 144struct drm_msm_gem_cpu_prep { 145 __u32 handle; /* in */ 146 __u32 op; /* in, mask of MSM_PREP_x */ 147 struct drm_msm_timespec timeout; /* in */ 148}; 149 150struct drm_msm_gem_cpu_fini { 151 __u32 handle; /* in */ 152}; 153 154/* 155 * Cmdstream Submission: 156 */ 157 158/* The value written into the cmdstream is logically: 159 * 160 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 161 * 162 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 163 * with this by emit'ing two reloc entries with appropriate shift 164 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 165 * 166 * NOTE that reloc's must be sorted by order of increasing submit_offset, 167 * otherwise EINVAL. 168 */ 169struct drm_msm_gem_submit_reloc { 170 __u32 submit_offset; /* in, offset from submit_bo */ 171 __u32 or; /* in, value OR'd with result */ 172 __s32 shift; /* in, amount of left shift (can be negative) */ 173 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 174 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 175}; 176 177/* submit-types: 178 * BUF - this cmd buffer is executed normally. 179 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 180 * processed normally, but the kernel does not setup an IB to 181 * this buffer in the first-level ringbuffer 182 * CTX_RESTORE_BUF - only executed if there has been a GPU context 183 * switch since the last SUBMIT ioctl 184 */ 185#define MSM_SUBMIT_CMD_BUF 0x0001 186#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 187#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 188struct drm_msm_gem_submit_cmd { 189 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 190 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 191 __u32 submit_offset; /* in, offset into submit_bo */ 192 __u32 size; /* in, cmdstream size */ 193 __u32 pad; 194 __u32 nr_relocs; /* in, number of submit_reloc's */ 195 __u64 relocs; /* in, ptr to array of submit_reloc's */ 196}; 197 198/* Each buffer referenced elsewhere in the cmdstream submit (ie. the 199 * cmdstream buffer(s) themselves or reloc entries) has one (and only 200 * one) entry in the submit->bos[] table. 201 * 202 * As a optimization, the current buffer (gpu virtual address) can be 203 * passed back through the 'presumed' field. If on a subsequent reloc, 204 * userspace passes back a 'presumed' address that is still valid, 205 * then patching the cmdstream for this entry is skipped. This can 206 * avoid kernel needing to map/access the cmdstream bo in the common 207 * case. 208 */ 209#define MSM_SUBMIT_BO_READ 0x0001 210#define MSM_SUBMIT_BO_WRITE 0x0002 211#define MSM_SUBMIT_BO_DUMP 0x0004 212 213#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \ 214 MSM_SUBMIT_BO_WRITE | \ 215 MSM_SUBMIT_BO_DUMP) 216 217struct drm_msm_gem_submit_bo { 218 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 219 __u32 handle; /* in, GEM handle */ 220 __u64 presumed; /* in/out, presumed buffer address */ 221}; 222 223/* Valid submit ioctl flags: */ 224#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 225#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 226#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 227#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */ 228#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */ 229#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */ 230#define MSM_SUBMIT_FLAGS ( \ 231 MSM_SUBMIT_NO_IMPLICIT | \ 232 MSM_SUBMIT_FENCE_FD_IN | \ 233 MSM_SUBMIT_FENCE_FD_OUT | \ 234 MSM_SUBMIT_SUDO | \ 235 MSM_SUBMIT_SYNCOBJ_IN | \ 236 MSM_SUBMIT_SYNCOBJ_OUT | \ 237 0) 238 239#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */ 240#define MSM_SUBMIT_SYNCOBJ_FLAGS ( \ 241 MSM_SUBMIT_SYNCOBJ_RESET | \ 242 0) 243 244struct drm_msm_gem_submit_syncobj { 245 __u32 handle; /* in, syncobj handle. */ 246 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */ 247 __u64 point; /* in, timepoint for timeline syncobjs. */ 248}; 249 250/* Each cmdstream submit consists of a table of buffers involved, and 251 * one or more cmdstream buffers. This allows for conditional execution 252 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 253 */ 254struct drm_msm_gem_submit { 255 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 256 __u32 fence; /* out */ 257 __u32 nr_bos; /* in, number of submit_bo's */ 258 __u32 nr_cmds; /* in, number of submit_cmd's */ 259 __u64 bos; /* in, ptr to array of submit_bo's */ 260 __u64 cmds; /* in, ptr to array of submit_cmd's */ 261 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 262 __u32 queueid; /* in, submitqueue id */ 263 __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */ 264 __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */ 265 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */ 266 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */ 267 __u32 syncobj_stride; /* in, stride of syncobj arrays. */ 268 __u32 pad; /*in, reserved for future use, always 0. */ 269 270}; 271 272/* The normal way to synchronize with the GPU is just to CPU_PREP on 273 * a buffer if you need to access it from the CPU (other cmdstream 274 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 275 * handle the required synchronization under the hood). This ioctl 276 * mainly just exists as a way to implement the gallium pipe_fence 277 * APIs without requiring a dummy bo to synchronize on. 278 */ 279struct drm_msm_wait_fence { 280 __u32 fence; /* in */ 281 __u32 pad; 282 struct drm_msm_timespec timeout; /* in */ 283 __u32 queueid; /* in, submitqueue id */ 284}; 285 286/* madvise provides a way to tell the kernel in case a buffers contents 287 * can be discarded under memory pressure, which is useful for userspace 288 * bo cache where we want to optimistically hold on to buffer allocate 289 * and potential mmap, but allow the pages to be discarded under memory 290 * pressure. 291 * 292 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 293 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 294 * In the WILLNEED case, 'retained' indicates to userspace whether the 295 * backing pages still exist. 296 */ 297#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 298#define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 299#define __MSM_MADV_PURGED 2 /* internal state */ 300 301struct drm_msm_gem_madvise { 302 __u32 handle; /* in, GEM handle */ 303 __u32 madv; /* in, MSM_MADV_x */ 304 __u32 retained; /* out, whether backing store still exists */ 305}; 306 307/* 308 * Draw queues allow the user to set specific submission parameter. Command 309 * submissions specify a specific submitqueue to use. ID 0 is reserved for 310 * backwards compatibility as a "default" submitqueue 311 */ 312 313#define MSM_SUBMITQUEUE_FLAGS (0) 314 315/* 316 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, 317 * a lower numeric value is higher priority. 318 */ 319struct drm_msm_submitqueue { 320 __u32 flags; /* in, MSM_SUBMITQUEUE_x */ 321 __u32 prio; /* in, Priority level */ 322 __u32 id; /* out, identifier */ 323}; 324 325#define MSM_SUBMITQUEUE_PARAM_FAULTS 0 326 327struct drm_msm_submitqueue_query { 328 __u64 data; 329 __u32 id; 330 __u32 param; 331 __u32 len; 332 __u32 pad; 333}; 334 335#define DRM_MSM_GET_PARAM 0x00 336/* placeholder: 337#define DRM_MSM_SET_PARAM 0x01 338 */ 339#define DRM_MSM_GEM_NEW 0x02 340#define DRM_MSM_GEM_INFO 0x03 341#define DRM_MSM_GEM_CPU_PREP 0x04 342#define DRM_MSM_GEM_CPU_FINI 0x05 343#define DRM_MSM_GEM_SUBMIT 0x06 344#define DRM_MSM_WAIT_FENCE 0x07 345#define DRM_MSM_GEM_MADVISE 0x08 346/* placeholder: 347#define DRM_MSM_GEM_SVM_NEW 0x09 348 */ 349#define DRM_MSM_SUBMITQUEUE_NEW 0x0A 350#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 351#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 352 353#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 354#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 355#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 356#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 357#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 358#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 359#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 360#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 361#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 362#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 363#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 364 365#if defined(__cplusplus) 366} 367#endif 368 369#endif /* __MSM_DRM_H__ */ 370