LXR linux/include/uapi/linux/hdlc/ioctl.h

   1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2#ifndef __HDLC_IOCTL_H__
   3#define __HDLC_IOCTL_H__
   4
   5
   6#define GENERIC_HDLC_VERSION 4  /* For synchronization with sethdlc utility */
   7
   8#define CLOCK_DEFAULT   0       /* Default setting */
   9#define CLOCK_EXT       1       /* External TX and RX clock - DTE */
  10#define CLOCK_INT       2       /* Internal TX and RX clock - DCE */
  11#define CLOCK_TXINT     3       /* Internal TX and external RX clock */
  12#define CLOCK_TXFROMRX  4       /* TX clock derived from external RX clock */
  13
  14
  15#define ENCODING_DEFAULT        0 /* Default setting */
  16#define ENCODING_NRZ            1
  17#define ENCODING_NRZI           2
  18#define ENCODING_FM_MARK        3
  19#define ENCODING_FM_SPACE       4
  20#define ENCODING_MANCHESTER     5
  21
  22
  23#define PARITY_DEFAULT          0 /* Default setting */
  24#define PARITY_NONE             1 /* No parity */
  25#define PARITY_CRC16_PR0        2 /* CRC16, initial value 0x0000 */
  26#define PARITY_CRC16_PR1        3 /* CRC16, initial value 0xFFFF */
  27#define PARITY_CRC16_PR0_CCITT  4 /* CRC16, initial 0x0000, ITU-T version */
  28#define PARITY_CRC16_PR1_CCITT  5 /* CRC16, initial 0xFFFF, ITU-T version */
  29#define PARITY_CRC32_PR0_CCITT  6 /* CRC32, initial value 0x00000000 */
  30#define PARITY_CRC32_PR1_CCITT  7 /* CRC32, initial value 0xFFFFFFFF */
  31
  32#define LMI_DEFAULT             0 /* Default setting */
  33#define LMI_NONE                1 /* No LMI, all PVCs are static */
  34#define LMI_ANSI                2 /* ANSI Annex D */
  35#define LMI_CCITT               3 /* ITU-T Annex A */
  36#define LMI_CISCO               4 /* The "original" LMI, aka Gang of Four */
  37
  38#ifndef __ASSEMBLY__
  39
  40typedef struct {
  41        unsigned int clock_rate; /* bits per second */
  42        unsigned int clock_type; /* internal, external, TX-internal etc. */
  43        unsigned short loopback;
  44} sync_serial_settings;          /* V.35, V.24, X.21 */
  45
  46typedef struct {
  47        unsigned int clock_rate; /* bits per second */
  48        unsigned int clock_type; /* internal, external, TX-internal etc. */
  49        unsigned short loopback;
  50        unsigned int slot_map;
  51} te1_settings;                  /* T1, E1 */
  52
  53typedef struct {
  54        unsigned short encoding;
  55        unsigned short parity;
  56} raw_hdlc_proto;
  57
  58typedef struct {
  59        unsigned int t391;
  60        unsigned int t392;
  61        unsigned int n391;
  62        unsigned int n392;
  63        unsigned int n393;
  64        unsigned short lmi;
  65        unsigned short dce; /* 1 for DCE (network side) operation */
  66} fr_proto;
  67
  68typedef struct {
  69        unsigned int dlci;
  70} fr_proto_pvc;          /* for creating/deleting FR PVCs */
  71
  72typedef struct {
  73        unsigned int dlci;
  74        char master[IFNAMSIZ];  /* Name of master FRAD device */
  75}fr_proto_pvc_info;             /* for returning PVC information only */
  76
  77typedef struct {
  78    unsigned int interval;
  79    unsigned int timeout;
  80} cisco_proto;
  81
  82typedef struct {
  83        unsigned short dce; /* 1 for DCE (network side) operation */
  84        unsigned int modulo; /* modulo (8 = basic / 128 = extended) */
  85        unsigned int window; /* frame window size */
  86        unsigned int t1; /* timeout t1 */
  87        unsigned int t2; /* timeout t2 */
  88        unsigned int n2; /* frame retry counter */
  89} x25_hdlc_proto;
  90
  91/* PPP doesn't need any info now - supply length = 0 to ioctl */
  92
  93#endif /* __ASSEMBLY__ */
  94#endif /* __HDLC_IOCTL_H__ */
  95