1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15#ifndef _UAPI_LINUX_PERF_EVENT_H 16#define _UAPI_LINUX_PERF_EVENT_H 17 18#include <linux/types.h> 19#include <linux/ioctl.h> 20#include <asm/byteorder.h> 21 22/* 23 * User-space ABI bits: 24 */ 25 26/* 27 * attr.type 28 */ 29enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38}; 39 40/* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52#define PERF_PMU_TYPE_SHIFT 32 53#define PERF_HW_EVENT_MASK 0xffffffff 54 55/* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76}; 77 78/* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95}; 96 97enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103}; 104 105enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110}; 111 112/* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133}; 134 135/* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169}; 170 171#define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172/* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208}; 209 210enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 237}; 238 239/* 240 * Common flow change classification 241 */ 242enum { 243 PERF_BR_UNKNOWN = 0, /* unknown */ 244 PERF_BR_COND = 1, /* conditional */ 245 PERF_BR_UNCOND = 2, /* unconditional */ 246 PERF_BR_IND = 3, /* indirect */ 247 PERF_BR_CALL = 4, /* function call */ 248 PERF_BR_IND_CALL = 5, /* indirect function call */ 249 PERF_BR_RET = 6, /* function return */ 250 PERF_BR_SYSCALL = 7, /* syscall */ 251 PERF_BR_SYSRET = 8, /* syscall return */ 252 PERF_BR_COND_CALL = 9, /* conditional function call */ 253 PERF_BR_COND_RET = 10, /* conditional function return */ 254 PERF_BR_MAX, 255}; 256 257#define PERF_SAMPLE_BRANCH_PLM_ALL \ 258 (PERF_SAMPLE_BRANCH_USER|\ 259 PERF_SAMPLE_BRANCH_KERNEL|\ 260 PERF_SAMPLE_BRANCH_HV) 261 262/* 263 * Values to determine ABI of the registers dump. 264 */ 265enum perf_sample_regs_abi { 266 PERF_SAMPLE_REGS_ABI_NONE = 0, 267 PERF_SAMPLE_REGS_ABI_32 = 1, 268 PERF_SAMPLE_REGS_ABI_64 = 2, 269}; 270 271/* 272 * Values for the memory transaction event qualifier, mostly for 273 * abort events. Multiple bits can be set. 274 */ 275enum { 276 PERF_TXN_ELISION = (1 << 0), /* From elision */ 277 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 278 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 279 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 280 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 281 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 282 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 283 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 284 285 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 286 287 /* bits 32..63 are reserved for the abort code */ 288 289 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 290 PERF_TXN_ABORT_SHIFT = 32, 291}; 292 293/* 294 * The format of the data returned by read() on a perf event fd, 295 * as specified by attr.read_format: 296 * 297 * struct read_format { 298 * { u64 value; 299 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 300 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 301 * { u64 id; } && PERF_FORMAT_ID 302 * } && !PERF_FORMAT_GROUP 303 * 304 * { u64 nr; 305 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 306 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 307 * { u64 value; 308 * { u64 id; } && PERF_FORMAT_ID 309 * } cntr[nr]; 310 * } && PERF_FORMAT_GROUP 311 * }; 312 */ 313enum perf_event_read_format { 314 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 315 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 316 PERF_FORMAT_ID = 1U << 2, 317 PERF_FORMAT_GROUP = 1U << 3, 318 319 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 320}; 321 322#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 323#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 324#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 325#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 326 /* add: sample_stack_user */ 327#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 328#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 329#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 330#define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 331 332/* 333 * Hardware event_id to monitor via a performance monitoring event: 334 * 335 * @sample_max_stack: Max number of frame pointers in a callchain, 336 * should be < /proc/sys/kernel/perf_event_max_stack 337 */ 338struct perf_event_attr { 339 340 /* 341 * Major type: hardware/software/tracepoint/etc. 342 */ 343 __u32 type; 344 345 /* 346 * Size of the attr structure, for fwd/bwd compat. 347 */ 348 __u32 size; 349 350 /* 351 * Type specific configuration information. 352 */ 353 __u64 config; 354 355 union { 356 __u64 sample_period; 357 __u64 sample_freq; 358 }; 359 360 __u64 sample_type; 361 __u64 read_format; 362 363 __u64 disabled : 1, /* off by default */ 364 inherit : 1, /* children inherit it */ 365 pinned : 1, /* must always be on PMU */ 366 exclusive : 1, /* only group on PMU */ 367 exclude_user : 1, /* don't count user */ 368 exclude_kernel : 1, /* ditto kernel */ 369 exclude_hv : 1, /* ditto hypervisor */ 370 exclude_idle : 1, /* don't count when idle */ 371 mmap : 1, /* include mmap data */ 372 comm : 1, /* include comm data */ 373 freq : 1, /* use freq, not period */ 374 inherit_stat : 1, /* per task counts */ 375 enable_on_exec : 1, /* next exec enables */ 376 task : 1, /* trace fork/exit */ 377 watermark : 1, /* wakeup_watermark */ 378 /* 379 * precise_ip: 380 * 381 * 0 - SAMPLE_IP can have arbitrary skid 382 * 1 - SAMPLE_IP must have constant skid 383 * 2 - SAMPLE_IP requested to have 0 skid 384 * 3 - SAMPLE_IP must have 0 skid 385 * 386 * See also PERF_RECORD_MISC_EXACT_IP 387 */ 388 precise_ip : 2, /* skid constraint */ 389 mmap_data : 1, /* non-exec mmap data */ 390 sample_id_all : 1, /* sample_type all events */ 391 392 exclude_host : 1, /* don't count in host */ 393 exclude_guest : 1, /* don't count in guest */ 394 395 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 396 exclude_callchain_user : 1, /* exclude user callchains */ 397 mmap2 : 1, /* include mmap with inode data */ 398 comm_exec : 1, /* flag comm events that are due to an exec */ 399 use_clockid : 1, /* use @clockid for time fields */ 400 context_switch : 1, /* context switch data */ 401 write_backward : 1, /* Write ring buffer from end to beginning */ 402 namespaces : 1, /* include namespaces data */ 403 ksymbol : 1, /* include ksymbol events */ 404 bpf_event : 1, /* include bpf events */ 405 aux_output : 1, /* generate AUX records instead of events */ 406 cgroup : 1, /* include cgroup events */ 407 text_poke : 1, /* include text poke events */ 408 build_id : 1, /* use build id in mmap2 events */ 409 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 410 remove_on_exec : 1, /* event is removed from task on exec */ 411 sigtrap : 1, /* send synchronous SIGTRAP on event */ 412 __reserved_1 : 26; 413 414 union { 415 __u32 wakeup_events; /* wakeup every n events */ 416 __u32 wakeup_watermark; /* bytes before wakeup */ 417 }; 418 419 __u32 bp_type; 420 union { 421 __u64 bp_addr; 422 __u64 kprobe_func; /* for perf_kprobe */ 423 __u64 uprobe_path; /* for perf_uprobe */ 424 __u64 config1; /* extension of config */ 425 }; 426 union { 427 __u64 bp_len; 428 __u64 kprobe_addr; /* when kprobe_func == NULL */ 429 __u64 probe_offset; /* for perf_[k,u]probe */ 430 __u64 config2; /* extension of config1 */ 431 }; 432 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 433 434 /* 435 * Defines set of user regs to dump on samples. 436 * See asm/perf_regs.h for details. 437 */ 438 __u64 sample_regs_user; 439 440 /* 441 * Defines size of the user stack to dump on samples. 442 */ 443 __u32 sample_stack_user; 444 445 __s32 clockid; 446 /* 447 * Defines set of regs to dump for each sample 448 * state captured on: 449 * - precise = 0: PMU interrupt 450 * - precise > 0: sampled instruction 451 * 452 * See asm/perf_regs.h for details. 453 */ 454 __u64 sample_regs_intr; 455 456 /* 457 * Wakeup watermark for AUX area 458 */ 459 __u32 aux_watermark; 460 __u16 sample_max_stack; 461 __u16 __reserved_2; 462 __u32 aux_sample_size; 463 __u32 __reserved_3; 464 465 /* 466 * User provided data if sigtrap=1, passed back to user via 467 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 468 */ 469 __u64 sig_data; 470}; 471 472/* 473 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 474 * to query bpf programs attached to the same perf tracepoint 475 * as the given perf event. 476 */ 477struct perf_event_query_bpf { 478 /* 479 * The below ids array length 480 */ 481 __u32 ids_len; 482 /* 483 * Set by the kernel to indicate the number of 484 * available programs 485 */ 486 __u32 prog_cnt; 487 /* 488 * User provided buffer to store program ids 489 */ 490 __u32 ids[0]; 491}; 492 493/* 494 * Ioctls that can be done on a perf event fd: 495 */ 496#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 497#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 498#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 499#define PERF_EVENT_IOC_RESET _IO ('$', 3) 500#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 501#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 502#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 503#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 504#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 505#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 506#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 507#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 508 509enum perf_event_ioc_flags { 510 PERF_IOC_FLAG_GROUP = 1U << 0, 511}; 512 513/* 514 * Structure of the page that can be mapped via mmap 515 */ 516struct perf_event_mmap_page { 517 __u32 version; /* version number of this structure */ 518 __u32 compat_version; /* lowest version this is compat with */ 519 520 /* 521 * Bits needed to read the hw events in user-space. 522 * 523 * u32 seq, time_mult, time_shift, index, width; 524 * u64 count, enabled, running; 525 * u64 cyc, time_offset; 526 * s64 pmc = 0; 527 * 528 * do { 529 * seq = pc->lock; 530 * barrier() 531 * 532 * enabled = pc->time_enabled; 533 * running = pc->time_running; 534 * 535 * if (pc->cap_usr_time && enabled != running) { 536 * cyc = rdtsc(); 537 * time_offset = pc->time_offset; 538 * time_mult = pc->time_mult; 539 * time_shift = pc->time_shift; 540 * } 541 * 542 * index = pc->index; 543 * count = pc->offset; 544 * if (pc->cap_user_rdpmc && index) { 545 * width = pc->pmc_width; 546 * pmc = rdpmc(index - 1); 547 * } 548 * 549 * barrier(); 550 * } while (pc->lock != seq); 551 * 552 * NOTE: for obvious reason this only works on self-monitoring 553 * processes. 554 */ 555 __u32 lock; /* seqlock for synchronization */ 556 __u32 index; /* hardware event identifier */ 557 __s64 offset; /* add to hardware event value */ 558 __u64 time_enabled; /* time event active */ 559 __u64 time_running; /* time event on cpu */ 560 union { 561 __u64 capabilities; 562 struct { 563 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 564 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 565 566 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 567 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 568 cap_user_time_zero : 1, /* The time_zero field is used */ 569 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 570 cap_____res : 58; 571 }; 572 }; 573 574 /* 575 * If cap_user_rdpmc this field provides the bit-width of the value 576 * read using the rdpmc() or equivalent instruction. This can be used 577 * to sign extend the result like: 578 * 579 * pmc <<= 64 - width; 580 * pmc >>= 64 - width; // signed shift right 581 * count += pmc; 582 */ 583 __u16 pmc_width; 584 585 /* 586 * If cap_usr_time the below fields can be used to compute the time 587 * delta since time_enabled (in ns) using rdtsc or similar. 588 * 589 * u64 quot, rem; 590 * u64 delta; 591 * 592 * quot = (cyc >> time_shift); 593 * rem = cyc & (((u64)1 << time_shift) - 1); 594 * delta = time_offset + quot * time_mult + 595 * ((rem * time_mult) >> time_shift); 596 * 597 * Where time_offset,time_mult,time_shift and cyc are read in the 598 * seqcount loop described above. This delta can then be added to 599 * enabled and possible running (if index), improving the scaling: 600 * 601 * enabled += delta; 602 * if (index) 603 * running += delta; 604 * 605 * quot = count / running; 606 * rem = count % running; 607 * count = quot * enabled + (rem * enabled) / running; 608 */ 609 __u16 time_shift; 610 __u32 time_mult; 611 __u64 time_offset; 612 /* 613 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 614 * from sample timestamps. 615 * 616 * time = timestamp - time_zero; 617 * quot = time / time_mult; 618 * rem = time % time_mult; 619 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 620 * 621 * And vice versa: 622 * 623 * quot = cyc >> time_shift; 624 * rem = cyc & (((u64)1 << time_shift) - 1); 625 * timestamp = time_zero + quot * time_mult + 626 * ((rem * time_mult) >> time_shift); 627 */ 628 __u64 time_zero; 629 630 __u32 size; /* Header size up to __reserved[] fields. */ 631 __u32 __reserved_1; 632 633 /* 634 * If cap_usr_time_short, the hardware clock is less than 64bit wide 635 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 636 * 637 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 638 * 639 * NOTE: this form is explicitly chosen such that cap_usr_time_short 640 * is a correction on top of cap_usr_time, and code that doesn't 641 * know about cap_usr_time_short still works under the assumption 642 * the counter doesn't wrap. 643 */ 644 __u64 time_cycles; 645 __u64 time_mask; 646 647 /* 648 * Hole for extension of the self monitor capabilities 649 */ 650 651 __u8 __reserved[116*8]; /* align to 1k. */ 652 653 /* 654 * Control data for the mmap() data buffer. 655 * 656 * User-space reading the @data_head value should issue an smp_rmb(), 657 * after reading this value. 658 * 659 * When the mapping is PROT_WRITE the @data_tail value should be 660 * written by userspace to reflect the last read data, after issueing 661 * an smp_mb() to separate the data read from the ->data_tail store. 662 * In this case the kernel will not over-write unread data. 663 * 664 * See perf_output_put_handle() for the data ordering. 665 * 666 * data_{offset,size} indicate the location and size of the perf record 667 * buffer within the mmapped area. 668 */ 669 __u64 data_head; /* head in the data section */ 670 __u64 data_tail; /* user-space written tail */ 671 __u64 data_offset; /* where the buffer starts */ 672 __u64 data_size; /* data buffer size */ 673 674 /* 675 * AUX area is defined by aux_{offset,size} fields that should be set 676 * by the userspace, so that 677 * 678 * aux_offset >= data_offset + data_size 679 * 680 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 681 * 682 * Ring buffer pointers aux_{head,tail} have the same semantics as 683 * data_{head,tail} and same ordering rules apply. 684 */ 685 __u64 aux_head; 686 __u64 aux_tail; 687 __u64 aux_offset; 688 __u64 aux_size; 689}; 690 691/* 692 * The current state of perf_event_header::misc bits usage: 693 * ('|' used bit, '-' unused bit) 694 * 695 * 012 CDEF 696 * |||---------|||| 697 * 698 * Where: 699 * 0-2 CPUMODE_MASK 700 * 701 * C PROC_MAP_PARSE_TIMEOUT 702 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 703 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 704 * F (reserved) 705 */ 706 707#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 708#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 709#define PERF_RECORD_MISC_KERNEL (1 << 0) 710#define PERF_RECORD_MISC_USER (2 << 0) 711#define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 712#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 713#define PERF_RECORD_MISC_GUEST_USER (5 << 0) 714 715/* 716 * Indicates that /proc/PID/maps parsing are truncated by time out. 717 */ 718#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 719/* 720 * Following PERF_RECORD_MISC_* are used on different 721 * events, so can reuse the same bit position: 722 * 723 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 724 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 725 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 726 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 727 */ 728#define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 729#define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 730#define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 731#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 732/* 733 * These PERF_RECORD_MISC_* flags below are safely reused 734 * for the following events: 735 * 736 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 737 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 738 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 739 * 740 * 741 * PERF_RECORD_MISC_EXACT_IP: 742 * Indicates that the content of PERF_SAMPLE_IP points to 743 * the actual instruction that triggered the event. See also 744 * perf_event_attr::precise_ip. 745 * 746 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 747 * Indicates that thread was preempted in TASK_RUNNING state. 748 * 749 * PERF_RECORD_MISC_MMAP_BUILD_ID: 750 * Indicates that mmap2 event carries build id data. 751 */ 752#define PERF_RECORD_MISC_EXACT_IP (1 << 14) 753#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 754#define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 755/* 756 * Reserve the last bit to indicate some extended misc field 757 */ 758#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 759 760struct perf_event_header { 761 __u32 type; 762 __u16 misc; 763 __u16 size; 764}; 765 766struct perf_ns_link_info { 767 __u64 dev; 768 __u64 ino; 769}; 770 771enum { 772 NET_NS_INDEX = 0, 773 UTS_NS_INDEX = 1, 774 IPC_NS_INDEX = 2, 775 PID_NS_INDEX = 3, 776 USER_NS_INDEX = 4, 777 MNT_NS_INDEX = 5, 778 CGROUP_NS_INDEX = 6, 779 780 NR_NAMESPACES, /* number of available namespaces */ 781}; 782 783enum perf_event_type { 784 785 /* 786 * If perf_event_attr.sample_id_all is set then all event types will 787 * have the sample_type selected fields related to where/when 788 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 789 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 790 * just after the perf_event_header and the fields already present for 791 * the existing fields, i.e. at the end of the payload. That way a newer 792 * perf.data file will be supported by older perf tools, with these new 793 * optional fields being ignored. 794 * 795 * struct sample_id { 796 * { u32 pid, tid; } && PERF_SAMPLE_TID 797 * { u64 time; } && PERF_SAMPLE_TIME 798 * { u64 id; } && PERF_SAMPLE_ID 799 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 800 * { u32 cpu, res; } && PERF_SAMPLE_CPU 801 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 802 * } && perf_event_attr::sample_id_all 803 * 804 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 805 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 806 * relative to header.size. 807 */ 808 809 /* 810 * The MMAP events record the PROT_EXEC mappings so that we can 811 * correlate userspace IPs to code. They have the following structure: 812 * 813 * struct { 814 * struct perf_event_header header; 815 * 816 * u32 pid, tid; 817 * u64 addr; 818 * u64 len; 819 * u64 pgoff; 820 * char filename[]; 821 * struct sample_id sample_id; 822 * }; 823 */ 824 PERF_RECORD_MMAP = 1, 825 826 /* 827 * struct { 828 * struct perf_event_header header; 829 * u64 id; 830 * u64 lost; 831 * struct sample_id sample_id; 832 * }; 833 */ 834 PERF_RECORD_LOST = 2, 835 836 /* 837 * struct { 838 * struct perf_event_header header; 839 * 840 * u32 pid, tid; 841 * char comm[]; 842 * struct sample_id sample_id; 843 * }; 844 */ 845 PERF_RECORD_COMM = 3, 846 847 /* 848 * struct { 849 * struct perf_event_header header; 850 * u32 pid, ppid; 851 * u32 tid, ptid; 852 * u64 time; 853 * struct sample_id sample_id; 854 * }; 855 */ 856 PERF_RECORD_EXIT = 4, 857 858 /* 859 * struct { 860 * struct perf_event_header header; 861 * u64 time; 862 * u64 id; 863 * u64 stream_id; 864 * struct sample_id sample_id; 865 * }; 866 */ 867 PERF_RECORD_THROTTLE = 5, 868 PERF_RECORD_UNTHROTTLE = 6, 869 870 /* 871 * struct { 872 * struct perf_event_header header; 873 * u32 pid, ppid; 874 * u32 tid, ptid; 875 * u64 time; 876 * struct sample_id sample_id; 877 * }; 878 */ 879 PERF_RECORD_FORK = 7, 880 881 /* 882 * struct { 883 * struct perf_event_header header; 884 * u32 pid, tid; 885 * 886 * struct read_format values; 887 * struct sample_id sample_id; 888 * }; 889 */ 890 PERF_RECORD_READ = 8, 891 892 /* 893 * struct { 894 * struct perf_event_header header; 895 * 896 * # 897 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 898 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 899 * # is fixed relative to header. 900 * # 901 * 902 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 903 * { u64 ip; } && PERF_SAMPLE_IP 904 * { u32 pid, tid; } && PERF_SAMPLE_TID 905 * { u64 time; } && PERF_SAMPLE_TIME 906 * { u64 addr; } && PERF_SAMPLE_ADDR 907 * { u64 id; } && PERF_SAMPLE_ID 908 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 909 * { u32 cpu, res; } && PERF_SAMPLE_CPU 910 * { u64 period; } && PERF_SAMPLE_PERIOD 911 * 912 * { struct read_format values; } && PERF_SAMPLE_READ 913 * 914 * { u64 nr, 915 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 916 * 917 * # 918 * # The RAW record below is opaque data wrt the ABI 919 * # 920 * # That is, the ABI doesn't make any promises wrt to 921 * # the stability of its content, it may vary depending 922 * # on event, hardware, kernel version and phase of 923 * # the moon. 924 * # 925 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 926 * # 927 * 928 * { u32 size; 929 * char data[size];}&& PERF_SAMPLE_RAW 930 * 931 * { u64 nr; 932 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 933 * { u64 from, to, flags } lbr[nr]; 934 * } && PERF_SAMPLE_BRANCH_STACK 935 * 936 * { u64 abi; # enum perf_sample_regs_abi 937 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 938 * 939 * { u64 size; 940 * char data[size]; 941 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 942 * 943 * { union perf_sample_weight 944 * { 945 * u64 full; && PERF_SAMPLE_WEIGHT 946 * #if defined(__LITTLE_ENDIAN_BITFIELD) 947 * struct { 948 * u32 var1_dw; 949 * u16 var2_w; 950 * u16 var3_w; 951 * } && PERF_SAMPLE_WEIGHT_STRUCT 952 * #elif defined(__BIG_ENDIAN_BITFIELD) 953 * struct { 954 * u16 var3_w; 955 * u16 var2_w; 956 * u32 var1_dw; 957 * } && PERF_SAMPLE_WEIGHT_STRUCT 958 * #endif 959 * } 960 * } 961 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 962 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 963 * { u64 abi; # enum perf_sample_regs_abi 964 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 965 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 966 * { u64 size; 967 * char data[size]; } && PERF_SAMPLE_AUX 968 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 969 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 970 * }; 971 */ 972 PERF_RECORD_SAMPLE = 9, 973 974 /* 975 * The MMAP2 records are an augmented version of MMAP, they add 976 * maj, min, ino numbers to be used to uniquely identify each mapping 977 * 978 * struct { 979 * struct perf_event_header header; 980 * 981 * u32 pid, tid; 982 * u64 addr; 983 * u64 len; 984 * u64 pgoff; 985 * union { 986 * struct { 987 * u32 maj; 988 * u32 min; 989 * u64 ino; 990 * u64 ino_generation; 991 * }; 992 * struct { 993 * u8 build_id_size; 994 * u8 __reserved_1; 995 * u16 __reserved_2; 996 * u8 build_id[20]; 997 * }; 998 * }; 999 * u32 prot, flags; 1000 * char filename[];
1001 * struct sample_id sample_id; 1002 * }; 1003 */ 1004 PERF_RECORD_MMAP2 = 10, 1005 1006 /* 1007 * Records that new data landed in the AUX buffer part. 1008 * 1009 * struct { 1010 * struct perf_event_header header; 1011 * 1012 * u64 aux_offset; 1013 * u64 aux_size; 1014 * u64 flags; 1015 * struct sample_id sample_id; 1016 * }; 1017 */ 1018 PERF_RECORD_AUX = 11, 1019 1020 /* 1021 * Indicates that instruction trace has started 1022 * 1023 * struct { 1024 * struct perf_event_header header; 1025 * u32 pid; 1026 * u32 tid; 1027 * struct sample_id sample_id; 1028 * }; 1029 */ 1030 PERF_RECORD_ITRACE_START = 12, 1031 1032 /* 1033 * Records the dropped/lost sample number. 1034 * 1035 * struct { 1036 * struct perf_event_header header; 1037 * 1038 * u64 lost; 1039 * struct sample_id sample_id; 1040 * }; 1041 */ 1042 PERF_RECORD_LOST_SAMPLES = 13, 1043 1044 /* 1045 * Records a context switch in or out (flagged by 1046 * PERF_RECORD_MISC_SWITCH_OUT). See also 1047 * PERF_RECORD_SWITCH_CPU_WIDE. 1048 * 1049 * struct { 1050 * struct perf_event_header header; 1051 * struct sample_id sample_id; 1052 * }; 1053 */ 1054 PERF_RECORD_SWITCH = 14, 1055 1056 /* 1057 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1058 * next_prev_tid that are the next (switching out) or previous 1059 * (switching in) pid/tid. 1060 * 1061 * struct { 1062 * struct perf_event_header header; 1063 * u32 next_prev_pid; 1064 * u32 next_prev_tid; 1065 * struct sample_id sample_id; 1066 * }; 1067 */ 1068 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1069 1070 /* 1071 * struct { 1072 * struct perf_event_header header; 1073 * u32 pid; 1074 * u32 tid; 1075 * u64 nr_namespaces; 1076 * { u64 dev, inode; } [nr_namespaces]; 1077 * struct sample_id sample_id; 1078 * }; 1079 */ 1080 PERF_RECORD_NAMESPACES = 16, 1081 1082 /* 1083 * Record ksymbol register/unregister events: 1084 * 1085 * struct { 1086 * struct perf_event_header header; 1087 * u64 addr; 1088 * u32 len; 1089 * u16 ksym_type; 1090 * u16 flags; 1091 * char name[]; 1092 * struct sample_id sample_id; 1093 * }; 1094 */ 1095 PERF_RECORD_KSYMBOL = 17, 1096 1097 /* 1098 * Record bpf events: 1099 * enum perf_bpf_event_type { 1100 * PERF_BPF_EVENT_UNKNOWN = 0, 1101 * PERF_BPF_EVENT_PROG_LOAD = 1, 1102 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1103 * }; 1104 * 1105 * struct { 1106 * struct perf_event_header header; 1107 * u16 type; 1108 * u16 flags; 1109 * u32 id; 1110 * u8 tag[BPF_TAG_SIZE]; 1111 * struct sample_id sample_id; 1112 * }; 1113 */ 1114 PERF_RECORD_BPF_EVENT = 18, 1115 1116 /* 1117 * struct { 1118 * struct perf_event_header header; 1119 * u64 id; 1120 * char path[]; 1121 * struct sample_id sample_id; 1122 * }; 1123 */ 1124 PERF_RECORD_CGROUP = 19, 1125 1126 /* 1127 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1128 * the number of old bytes, 'new_len' is the number of new bytes. Either 1129 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1130 * addition or removal of a trampoline. 'bytes' contains the old bytes 1131 * followed immediately by the new bytes. 1132 * 1133 * struct { 1134 * struct perf_event_header header; 1135 * u64 addr; 1136 * u16 old_len; 1137 * u16 new_len; 1138 * u8 bytes[]; 1139 * struct sample_id sample_id; 1140 * }; 1141 */ 1142 PERF_RECORD_TEXT_POKE = 20, 1143 1144 PERF_RECORD_MAX, /* non-ABI */ 1145}; 1146 1147enum perf_record_ksymbol_type { 1148 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1149 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1150 /* 1151 * Out of line code such as kprobe-replaced instructions or optimized 1152 * kprobes or ftrace trampolines. 1153 */ 1154 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1155 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1156}; 1157 1158#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1159 1160enum perf_bpf_event_type { 1161 PERF_BPF_EVENT_UNKNOWN = 0, 1162 PERF_BPF_EVENT_PROG_LOAD = 1, 1163 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1164 PERF_BPF_EVENT_MAX, /* non-ABI */ 1165}; 1166 1167#define PERF_MAX_STACK_DEPTH 127 1168#define PERF_MAX_CONTEXTS_PER_STACK 8 1169 1170enum perf_callchain_context { 1171 PERF_CONTEXT_HV = (__u64)-32, 1172 PERF_CONTEXT_KERNEL = (__u64)-128, 1173 PERF_CONTEXT_USER = (__u64)-512, 1174 1175 PERF_CONTEXT_GUEST = (__u64)-2048, 1176 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1177 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1178 1179 PERF_CONTEXT_MAX = (__u64)-4095, 1180}; 1181 1182/** 1183 * PERF_RECORD_AUX::flags bits 1184 */ 1185#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1186#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1187#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1188#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1189#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1190 1191/* CoreSight PMU AUX buffer formats */ 1192#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1193#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1194 1195#define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1196#define PERF_FLAG_FD_OUTPUT (1UL << 1) 1197#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1198#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1199 1200#if defined(__LITTLE_ENDIAN_BITFIELD) 1201union perf_mem_data_src { 1202 __u64 val; 1203 struct { 1204 __u64 mem_op:5, /* type of opcode */ 1205 mem_lvl:14, /* memory hierarchy level */ 1206 mem_snoop:5, /* snoop mode */ 1207 mem_lock:2, /* lock instr */ 1208 mem_dtlb:7, /* tlb access */ 1209 mem_lvl_num:4, /* memory hierarchy level number */ 1210 mem_remote:1, /* remote */ 1211 mem_snoopx:2, /* snoop mode, ext */ 1212 mem_blk:3, /* access blocked */ 1213 mem_rsvd:21; 1214 }; 1215}; 1216#elif defined(__BIG_ENDIAN_BITFIELD) 1217union perf_mem_data_src { 1218 __u64 val; 1219 struct { 1220 __u64 mem_rsvd:21, 1221 mem_blk:3, /* access blocked */ 1222 mem_snoopx:2, /* snoop mode, ext */ 1223 mem_remote:1, /* remote */ 1224 mem_lvl_num:4, /* memory hierarchy level number */ 1225 mem_dtlb:7, /* tlb access */ 1226 mem_lock:2, /* lock instr */ 1227 mem_snoop:5, /* snoop mode */ 1228 mem_lvl:14, /* memory hierarchy level */ 1229 mem_op:5; /* type of opcode */ 1230 }; 1231}; 1232#else 1233#error "Unknown endianness" 1234#endif 1235 1236/* type of opcode (load/store/prefetch,code) */ 1237#define PERF_MEM_OP_NA 0x01 /* not available */ 1238#define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1239#define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1240#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1241#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1242#define PERF_MEM_OP_SHIFT 0 1243 1244/* memory hierarchy (memory level, hit or miss) */ 1245#define PERF_MEM_LVL_NA 0x01 /* not available */ 1246#define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1247#define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1248#define PERF_MEM_LVL_L1 0x08 /* L1 */ 1249#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1250#define PERF_MEM_LVL_L2 0x20 /* L2 */ 1251#define PERF_MEM_LVL_L3 0x40 /* L3 */ 1252#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1253#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1254#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1255#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1256#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1257#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1258#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1259#define PERF_MEM_LVL_SHIFT 5 1260 1261#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1262#define PERF_MEM_REMOTE_SHIFT 37 1263 1264#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1265#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1266#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1267#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1268/* 5-0xa available */ 1269#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1270#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1271#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1272#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1273#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1274 1275#define PERF_MEM_LVLNUM_SHIFT 33 1276 1277/* snoop mode */ 1278#define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1279#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1280#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1281#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1282#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1283#define PERF_MEM_SNOOP_SHIFT 19 1284 1285#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1286/* 1 free */ 1287#define PERF_MEM_SNOOPX_SHIFT 38 1288 1289/* locked instruction */ 1290#define PERF_MEM_LOCK_NA 0x01 /* not available */ 1291#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1292#define PERF_MEM_LOCK_SHIFT 24 1293 1294/* TLB access */ 1295#define PERF_MEM_TLB_NA 0x01 /* not available */ 1296#define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1297#define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1298#define PERF_MEM_TLB_L1 0x08 /* L1 */ 1299#define PERF_MEM_TLB_L2 0x10 /* L2 */ 1300#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1301#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1302#define PERF_MEM_TLB_SHIFT 26 1303 1304/* Access blocked */ 1305#define PERF_MEM_BLK_NA 0x01 /* not available */ 1306#define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1307#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1308#define PERF_MEM_BLK_SHIFT 40 1309 1310#define PERF_MEM_S(a, s) \ 1311 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1312 1313/* 1314 * single taken branch record layout: 1315 * 1316 * from: source instruction (may not always be a branch insn) 1317 * to: branch target 1318 * mispred: branch target was mispredicted 1319 * predicted: branch target was predicted 1320 * 1321 * support for mispred, predicted is optional. In case it 1322 * is not supported mispred = predicted = 0. 1323 * 1324 * in_tx: running in a hardware transaction 1325 * abort: aborting a hardware transaction 1326 * cycles: cycles from last branch (or 0 if not supported) 1327 * type: branch type 1328 */ 1329struct perf_branch_entry { 1330 __u64 from; 1331 __u64 to; 1332 __u64 mispred:1, /* target mispredicted */ 1333 predicted:1,/* target predicted */ 1334 in_tx:1, /* in transaction */ 1335 abort:1, /* transaction abort */ 1336 cycles:16, /* cycle count to last branch */ 1337 type:4, /* branch type */ 1338 reserved:40; 1339}; 1340 1341union perf_sample_weight { 1342 __u64 full; 1343#if defined(__LITTLE_ENDIAN_BITFIELD) 1344 struct { 1345 __u32 var1_dw; 1346 __u16 var2_w; 1347 __u16 var3_w; 1348 }; 1349#elif defined(__BIG_ENDIAN_BITFIELD) 1350 struct { 1351 __u16 var3_w; 1352 __u16 var2_w; 1353 __u32 var1_dw; 1354 }; 1355#else 1356#error "Unknown endianness" 1357#endif 1358}; 1359 1360#endif /* _UAPI_LINUX_PERF_EVENT_H */ 1361