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23#ifndef _UAPI__SOUND_EMU10K1_H
24#define _UAPI__SOUND_EMU10K1_H
25
26#ifdef __linux__
27#include <linux/types.h>
28#endif
29
30
31
32
33
34#define EMU10K1_CARD_CREATIVE 0x00000000
35#define EMU10K1_CARD_EMUAPS 0x00000001
36
37#define EMU10K1_FX8010_PCM_COUNT 8
38
39
40
41
42
43
44#define __EMU10K1_DECLARE_BITMAP(name,bits) \
45 unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
46
47
48#define iMAC0 0x00
49#define iMAC1 0x01
50#define iMAC2 0x02
51#define iMAC3 0x03
52#define iMACINT0 0x04
53#define iMACINT1 0x05
54#define iACC3 0x06
55#define iMACMV 0x07
56#define iANDXOR 0x08
57#define iTSTNEG 0x09
58#define iLIMITGE 0x0a
59#define iLIMITLT 0x0b
60#define iLOG 0x0c
61#define iEXP 0x0d
62#define iINTERP 0x0e
63#define iSKIP 0x0f
64
65
66#define FXBUS(x) (0x00 + (x))
67#define EXTIN(x) (0x10 + (x))
68#define EXTOUT(x) (0x20 + (x))
69#define FXBUS2(x) (0x30 + (x))
70
71
72#define C_00000000 0x40
73#define C_00000001 0x41
74#define C_00000002 0x42
75#define C_00000003 0x43
76#define C_00000004 0x44
77#define C_00000008 0x45
78#define C_00000010 0x46
79#define C_00000020 0x47
80#define C_00000100 0x48
81#define C_00010000 0x49
82#define C_00080000 0x4a
83#define C_10000000 0x4b
84#define C_20000000 0x4c
85#define C_40000000 0x4d
86#define C_80000000 0x4e
87#define C_7fffffff 0x4f
88#define C_ffffffff 0x50
89#define C_fffffffe 0x51
90#define C_c0000000 0x52
91#define C_4f1bbcdc 0x53
92#define C_5a7ef9db 0x54
93#define C_00100000 0x55
94#define GPR_ACCU 0x56
95#define GPR_COND 0x57
96#define GPR_NOISE0 0x58
97#define GPR_NOISE1 0x59
98#define GPR_IRQ 0x5a
99#define GPR_DBAC 0x5b
100#define GPR(x) (FXGPREGBASE + (x))
101#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
102#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
103#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
104#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
105
106#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
107#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
108#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
109#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
110#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
111#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
112
113#define A_FXBUS(x) (0x00 + (x))
114#define A_EXTIN(x) (0x40 + (x))
115#define A_P16VIN(x) (0x50 + (x))
116#define A_EXTOUT(x) (0x60 + (x))
117#define A_FXBUS2(x) (0x80 + (x))
118#define A_EMU32OUTH(x) (0xa0 + (x))
119#define A_EMU32OUTL(x) (0xb0 + (x))
120#define A3_EMU32IN(x) (0x160 + (x))
121#define A3_EMU32OUT(x) (0x1E0 + (x))
122#define A_GPR(x) (A_FXGPREGBASE + (x))
123
124
125#define CC_REG_NORMALIZED C_00000001
126#define CC_REG_BORROW C_00000002
127#define CC_REG_MINUS C_00000004
128#define CC_REG_ZERO C_00000008
129#define CC_REG_SATURATE C_00000010
130#define CC_REG_NONZERO C_00000100
131
132
133#define FXBUS_PCM_LEFT 0x00
134#define FXBUS_PCM_RIGHT 0x01
135#define FXBUS_PCM_LEFT_REAR 0x02
136#define FXBUS_PCM_RIGHT_REAR 0x03
137#define FXBUS_MIDI_LEFT 0x04
138#define FXBUS_MIDI_RIGHT 0x05
139#define FXBUS_PCM_CENTER 0x06
140#define FXBUS_PCM_LFE 0x07
141#define FXBUS_PCM_LEFT_FRONT 0x08
142#define FXBUS_PCM_RIGHT_FRONT 0x09
143#define FXBUS_MIDI_REVERB 0x0c
144#define FXBUS_MIDI_CHORUS 0x0d
145#define FXBUS_PCM_LEFT_SIDE 0x0e
146#define FXBUS_PCM_RIGHT_SIDE 0x0f
147#define FXBUS_PT_LEFT 0x14
148#define FXBUS_PT_RIGHT 0x15
149
150
151#define EXTIN_AC97_L 0x00
152#define EXTIN_AC97_R 0x01
153#define EXTIN_SPDIF_CD_L 0x02
154#define EXTIN_SPDIF_CD_R 0x03
155#define EXTIN_ZOOM_L 0x04
156#define EXTIN_ZOOM_R 0x05
157#define EXTIN_TOSLINK_L 0x06
158#define EXTIN_TOSLINK_R 0x07
159#define EXTIN_LINE1_L 0x08
160#define EXTIN_LINE1_R 0x09
161#define EXTIN_COAX_SPDIF_L 0x0a
162#define EXTIN_COAX_SPDIF_R 0x0b
163#define EXTIN_LINE2_L 0x0c
164#define EXTIN_LINE2_R 0x0d
165
166
167#define EXTOUT_AC97_L 0x00
168#define EXTOUT_AC97_R 0x01
169#define EXTOUT_TOSLINK_L 0x02
170#define EXTOUT_TOSLINK_R 0x03
171#define EXTOUT_AC97_CENTER 0x04
172#define EXTOUT_AC97_LFE 0x05
173#define EXTOUT_HEADPHONE_L 0x06
174#define EXTOUT_HEADPHONE_R 0x07
175#define EXTOUT_REAR_L 0x08
176#define EXTOUT_REAR_R 0x09
177#define EXTOUT_ADC_CAP_L 0x0a
178#define EXTOUT_ADC_CAP_R 0x0b
179#define EXTOUT_MIC_CAP 0x0c
180#define EXTOUT_AC97_REAR_L 0x0d
181#define EXTOUT_AC97_REAR_R 0x0e
182#define EXTOUT_ACENTER 0x11
183#define EXTOUT_ALFE 0x12
184
185
186#define A_EXTIN_AC97_L 0x00
187#define A_EXTIN_AC97_R 0x01
188#define A_EXTIN_SPDIF_CD_L 0x02
189#define A_EXTIN_SPDIF_CD_R 0x03
190#define A_EXTIN_OPT_SPDIF_L 0x04
191#define A_EXTIN_OPT_SPDIF_R 0x05
192#define A_EXTIN_LINE2_L 0x08
193#define A_EXTIN_LINE2_R 0x09
194#define A_EXTIN_ADC_L 0x0a
195#define A_EXTIN_ADC_R 0x0b
196#define A_EXTIN_AUX2_L 0x0c
197#define A_EXTIN_AUX2_R 0x0d
198
199
200#define A_EXTOUT_FRONT_L 0x00
201#define A_EXTOUT_FRONT_R 0x01
202#define A_EXTOUT_CENTER 0x02
203#define A_EXTOUT_LFE 0x03
204#define A_EXTOUT_HEADPHONE_L 0x04
205#define A_EXTOUT_HEADPHONE_R 0x05
206#define A_EXTOUT_REAR_L 0x06
207#define A_EXTOUT_REAR_R 0x07
208#define A_EXTOUT_AFRONT_L 0x08
209#define A_EXTOUT_AFRONT_R 0x09
210#define A_EXTOUT_ACENTER 0x0a
211#define A_EXTOUT_ALFE 0x0b
212#define A_EXTOUT_ASIDE_L 0x0c
213#define A_EXTOUT_ASIDE_R 0x0d
214#define A_EXTOUT_AREAR_L 0x0e
215#define A_EXTOUT_AREAR_R 0x0f
216#define A_EXTOUT_AC97_L 0x10
217#define A_EXTOUT_AC97_R 0x11
218#define A_EXTOUT_ADC_CAP_L 0x16
219#define A_EXTOUT_ADC_CAP_R 0x17
220#define A_EXTOUT_MIC_CAP 0x18
221
222
223#define A_C_00000000 0xc0
224#define A_C_00000001 0xc1
225#define A_C_00000002 0xc2
226#define A_C_00000003 0xc3
227#define A_C_00000004 0xc4
228#define A_C_00000008 0xc5
229#define A_C_00000010 0xc6
230#define A_C_00000020 0xc7
231#define A_C_00000100 0xc8
232#define A_C_00010000 0xc9
233#define A_C_00000800 0xca
234#define A_C_10000000 0xcb
235#define A_C_20000000 0xcc
236#define A_C_40000000 0xcd
237#define A_C_80000000 0xce
238#define A_C_7fffffff 0xcf
239#define A_C_ffffffff 0xd0
240#define A_C_fffffffe 0xd1
241#define A_C_c0000000 0xd2
242#define A_C_4f1bbcdc 0xd3
243#define A_C_5a7ef9db 0xd4
244#define A_C_00100000 0xd5
245#define A_GPR_ACCU 0xd6
246#define A_GPR_COND 0xd7
247#define A_GPR_NOISE0 0xd8
248#define A_GPR_NOISE1 0xd9
249#define A_GPR_IRQ 0xda
250#define A_GPR_DBAC 0xdb
251#define A_GPR_DBACE 0xde
252
253
254#define EMU10K1_DBG_ZC 0x80000000
255#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
256#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
257#define EMU10K1_DBG_SINGLE_STEP 0x00008000
258#define EMU10K1_DBG_STEP 0x00004000
259#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
260#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
261
262
263#ifndef __KERNEL__
264#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
265#define TANKMEMADDRREG_CLEAR 0x00800000
266#define TANKMEMADDRREG_ALIGN 0x00400000
267#define TANKMEMADDRREG_WRITE 0x00200000
268#define TANKMEMADDRREG_READ 0x00100000
269#endif
270
271struct snd_emu10k1_fx8010_info {
272 unsigned int internal_tram_size;
273 unsigned int external_tram_size;
274 char fxbus_names[16][32];
275 char extin_names[16][32];
276 char extout_names[32][32];
277 unsigned int gpr_controls;
278};
279
280#define EMU10K1_GPR_TRANSLATION_NONE 0
281#define EMU10K1_GPR_TRANSLATION_TABLE100 1
282#define EMU10K1_GPR_TRANSLATION_BASS 2
283#define EMU10K1_GPR_TRANSLATION_TREBLE 3
284#define EMU10K1_GPR_TRANSLATION_ONOFF 4
285
286enum emu10k1_ctl_elem_iface {
287 EMU10K1_CTL_ELEM_IFACE_MIXER = 2,
288 EMU10K1_CTL_ELEM_IFACE_PCM = 3,
289};
290
291struct emu10k1_ctl_elem_id {
292 unsigned int pad;
293 int iface;
294 unsigned int device;
295 unsigned int subdevice;
296 unsigned char name[44];
297 unsigned int index;
298};
299
300struct snd_emu10k1_fx8010_control_gpr {
301 struct emu10k1_ctl_elem_id id;
302 unsigned int vcount;
303 unsigned int count;
304 unsigned short gpr[32];
305 unsigned int value[32];
306 unsigned int min;
307 unsigned int max;
308 unsigned int translation;
309 const unsigned int *tlv;
310};
311
312
313struct snd_emu10k1_fx8010_control_old_gpr {
314 struct emu10k1_ctl_elem_id id;
315 unsigned int vcount;
316 unsigned int count;
317 unsigned short gpr[32];
318 unsigned int value[32];
319 unsigned int min;
320 unsigned int max;
321 unsigned int translation;
322};
323
324struct snd_emu10k1_fx8010_code {
325 char name[128];
326
327 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
328 __u32 *gpr_map;
329
330 unsigned int gpr_add_control_count;
331 struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls;
332
333 unsigned int gpr_del_control_count;
334 struct emu10k1_ctl_elem_id *gpr_del_controls;
335
336 unsigned int gpr_list_control_count;
337 unsigned int gpr_list_control_total;
338 struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls;
339
340 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
341 __u32 *tram_data_map;
342 __u32 *tram_addr_map;
343
344 __EMU10K1_DECLARE_BITMAP(code_valid, 1024);
345 __u32 *code;
346};
347
348struct snd_emu10k1_fx8010_tram {
349 unsigned int address;
350 unsigned int size;
351 unsigned int *samples;
352
353};
354
355struct snd_emu10k1_fx8010_pcm_rec {
356 unsigned int substream;
357 unsigned int res1;
358 unsigned int channels;
359 unsigned int tram_start;
360 unsigned int buffer_size;
361 unsigned short gpr_size;
362 unsigned short gpr_ptr;
363 unsigned short gpr_count;
364 unsigned short gpr_tmpcount;
365 unsigned short gpr_trigger;
366 unsigned short gpr_running;
367 unsigned char pad;
368 unsigned char etram[32];
369 unsigned int res2;
370};
371
372#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
373
374#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
375#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
376#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
377#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
378#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
379#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
380#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
381#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
382#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
383#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
384#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
385#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
386#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
387#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
388
389#endif
390