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10#ifndef __HDA_TPLG_INTERFACE_H__
11#define __HDA_TPLG_INTERFACE_H__
12
13#include <linux/types.h>
14
15
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18
19#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
20#define SKL_CONTROL_TYPE_MIC_SELECT 0x102
21#define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103
22#define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104
23
24#define HDA_SST_CFG_MAX 900
25#define MAX_IN_QUEUE 8
26#define MAX_OUT_QUEUE 8
27
28#define SKL_UUID_STR_SZ 40
29
30
31enum skl_event_types {
32 SKL_EVENT_NONE = 0,
33 SKL_MIXER_EVENT,
34 SKL_MUX_EVENT,
35 SKL_VMIXER_EVENT,
36 SKL_PGA_EVENT
37};
38
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54
55
56enum skl_ch_cfg {
57 SKL_CH_CFG_MONO = 0,
58 SKL_CH_CFG_STEREO = 1,
59 SKL_CH_CFG_2_1 = 2,
60 SKL_CH_CFG_3_0 = 3,
61 SKL_CH_CFG_3_1 = 4,
62 SKL_CH_CFG_QUATRO = 5,
63 SKL_CH_CFG_4_0 = 6,
64 SKL_CH_CFG_5_0 = 7,
65 SKL_CH_CFG_5_1 = 8,
66 SKL_CH_CFG_DUAL_MONO = 9,
67 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
68 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
69 SKL_CH_CFG_4_CHANNEL = 12,
70 SKL_CH_CFG_INVALID
71};
72
73enum skl_module_type {
74 SKL_MODULE_TYPE_MIXER = 0,
75 SKL_MODULE_TYPE_COPIER,
76 SKL_MODULE_TYPE_UPDWMIX,
77 SKL_MODULE_TYPE_SRCINT,
78 SKL_MODULE_TYPE_ALGO,
79 SKL_MODULE_TYPE_BASE_OUTFMT,
80 SKL_MODULE_TYPE_KPB,
81 SKL_MODULE_TYPE_MIC_SELECT,
82};
83
84enum skl_core_affinity {
85 SKL_AFFINITY_CORE_0 = 0,
86 SKL_AFFINITY_CORE_1,
87 SKL_AFFINITY_CORE_MAX
88};
89
90enum skl_pipe_conn_type {
91 SKL_PIPE_CONN_TYPE_NONE = 0,
92 SKL_PIPE_CONN_TYPE_FE,
93 SKL_PIPE_CONN_TYPE_BE
94};
95
96enum skl_hw_conn_type {
97 SKL_CONN_NONE = 0,
98 SKL_CONN_SOURCE = 1,
99 SKL_CONN_SINK = 2
100};
101
102enum skl_dev_type {
103 SKL_DEVICE_BT = 0x0,
104 SKL_DEVICE_DMIC = 0x1,
105 SKL_DEVICE_I2S = 0x2,
106 SKL_DEVICE_SLIMBUS = 0x3,
107 SKL_DEVICE_HDALINK = 0x4,
108 SKL_DEVICE_HDAHOST = 0x5,
109 SKL_DEVICE_NONE
110};
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117
118enum skl_interleaving {
119 SKL_INTERLEAVING_PER_CHANNEL = 0,
120 SKL_INTERLEAVING_PER_SAMPLE = 1,
121};
122
123enum skl_sample_type {
124 SKL_SAMPLE_TYPE_INT_MSB = 0,
125 SKL_SAMPLE_TYPE_INT_LSB = 1,
126 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
127 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
128 SKL_SAMPLE_TYPE_FLOAT = 4
129};
130
131enum module_pin_type {
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135 SKL_PIN_TYPE_HOMOGENEOUS,
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139 SKL_PIN_TYPE_HETEROGENEOUS,
140};
141
142enum skl_module_param_type {
143 SKL_PARAM_DEFAULT = 0,
144 SKL_PARAM_INIT,
145 SKL_PARAM_SET,
146 SKL_PARAM_BIND
147};
148
149struct skl_dfw_algo_data {
150 __u32 set_params:2;
151 __u32 rsvd:30;
152 __u32 param_id;
153 __u32 max;
154 char params[0];
155} __packed;
156
157enum skl_tkn_dir {
158 SKL_DIR_IN,
159 SKL_DIR_OUT
160};
161
162enum skl_tuple_type {
163 SKL_TYPE_TUPLE,
164 SKL_TYPE_DATA
165};
166
167
168
169struct skl_dfw_v4_module_pin {
170 __u16 module_id;
171 __u16 instance_id;
172} __packed;
173
174struct skl_dfw_v4_module_fmt {
175 __u32 channels;
176 __u32 freq;
177 __u32 bit_depth;
178 __u32 valid_bit_depth;
179 __u32 ch_cfg;
180 __u32 interleaving_style;
181 __u32 sample_type;
182 __u32 ch_map;
183} __packed;
184
185struct skl_dfw_v4_module_caps {
186 __u32 set_params:2;
187 __u32 rsvd:30;
188 __u32 param_id;
189 __u32 caps_size;
190 __u32 caps[HDA_SST_CFG_MAX];
191} __packed;
192
193struct skl_dfw_v4_pipe {
194 __u8 pipe_id;
195 __u8 pipe_priority;
196 __u16 conn_type:4;
197 __u16 rsvd:4;
198 __u16 memory_pages:8;
199} __packed;
200
201struct skl_dfw_v4_module {
202 char uuid[SKL_UUID_STR_SZ];
203
204 __u16 module_id;
205 __u16 instance_id;
206 __u32 max_mcps;
207 __u32 mem_pages;
208 __u32 obs;
209 __u32 ibs;
210 __u32 vbus_id;
211
212 __u32 max_in_queue:8;
213 __u32 max_out_queue:8;
214 __u32 time_slot:8;
215 __u32 core_id:4;
216 __u32 rsvd1:4;
217
218 __u32 module_type:8;
219 __u32 conn_type:4;
220 __u32 dev_type:4;
221 __u32 hw_conn_type:4;
222 __u32 rsvd2:12;
223
224 __u32 params_fixup:8;
225 __u32 converter:8;
226 __u32 input_pin_type:1;
227 __u32 output_pin_type:1;
228 __u32 is_dynamic_in_pin:1;
229 __u32 is_dynamic_out_pin:1;
230 __u32 is_loadable:1;
231 __u32 rsvd3:11;
232
233 struct skl_dfw_v4_pipe pipe;
234 struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
235 struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
236 struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
237 struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
238 struct skl_dfw_v4_module_caps caps;
239} __packed;
240
241#endif
242