1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 Aureal Vortex Soundcard driver. 4 5 IO addr collected from asp4core.vxd: 6 function address 7 0005D5A0 13004 8 00080674 14004 9 00080AFF 12818 10 11 */ 12 13#define CHIP_AU8830 14 15#define CARD_NAME "Aureal Vortex 2" 16#define CARD_NAME_SHORT "au8830" 17 18#define NR_ADB 0x20 19#define NR_SRC 0x10 20#define NR_A3D 0x10 21#define NR_MIXIN 0x20 22#define NR_MIXOUT 0x10 23#define NR_WT 0x40 24 25/* ADBDMA */ 26#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ 27#define POS_MASK 0x00000fff 28#define POS_SHIFT 0x0 29#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ 30#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ 31#define VORTEX_ADBDMA_CTRL 0x27a00 /* write only; format, flags, DMA pos */ 32#define OFFSET_MASK 0x00000fff 33#define OFFSET_SHIFT 0x0 34#define IE_MASK 0x00001000 /* interrupt enable. */ 35#define IE_SHIFT 0xc 36#define DIR_MASK 0x00002000 /* Direction. */ 37#define DIR_SHIFT 0xd 38#define FMT_MASK 0x0003c000 39#define FMT_SHIFT 0xe 40#define ADB_FIFO_EN_SHIFT 0x15 41#define ADB_FIFO_EN (1 << 0x15) 42// The ADB masks and shift also are valid for the wtdma, except if specified otherwise. 43#define VORTEX_ADBDMA_BUFCFG0 0x27800 44#define VORTEX_ADBDMA_BUFCFG1 0x27804 45#define VORTEX_ADBDMA_BUFBASE 0x27400 46#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */ 47 48#define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */ 49/* Starting at the MSB, each pair of bits seem to be the current DMA page. */ 50/* This current page bits are consistent (same value) with VORTEX_ADBDMA_STAT) */ 51 52/* DMA */ 53#define VORTEX_ENGINE_CTRL 0x27ae8 54#define ENGINE_INIT 0x1380000 55 56/* WTDMA */ 57#define VORTEX_WTDMA_CTRL 0x27900 /* format, DMA pos */ 58#define VORTEX_WTDMA_STAT 0x27d00 /* DMA subbuf, DMA pos */ 59#define WT_SUBBUF_MASK 0x3 60#define WT_SUBBUF_SHIFT 0xc 61#define VORTEX_WTDMA_BUFBASE 0x27000 62#define VORTEX_WTDMA_BUFCFG0 0x27600 63#define VORTEX_WTDMA_BUFCFG1 0x27604 64#define VORTEX_WTDMA_START 0x27b00 /* which subbuffer is first */ 65 66/* ADB */ 67#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */ 68#define VORTEX_ADB_RTBASE 0x28000 69#define VORTEX_ADB_RTBASE_COUNT 173 70#define VORTEX_ADB_CHNBASE 0x282b4 71#define VORTEX_ADB_CHNBASE_COUNT 24 72#define ROUTE_MASK 0xffff 73#define SOURCE_MASK 0xff00 74#define ADB_MASK 0xff 75#define ADB_SHIFT 0x8 76/* ADB address */ 77#define OFFSET_ADBDMA 0x00 78#define OFFSET_ADBDMAB 0x20 79#define OFFSET_SRCIN 0x40 80#define OFFSET_SRCOUT 0x20 /* ch 0x11 */ 81#define OFFSET_MIXIN 0x50 /* ch 0x11 */ 82#define OFFSET_MIXOUT 0x30 /* ch 0x11 */ 83#define OFFSET_CODECIN 0x70 /* ch 0x11 */ /* adb source */ 84#define OFFSET_CODECOUT 0x88 /* ch 0x11 */ /* adb target */ 85#define OFFSET_SPORTIN 0x78 /* ch 0x13 ADB source. 2 routes. */ 86#define OFFSET_SPORTOUT 0x90 /* ch 0x13 ADB sink. 2 routes. */ 87#define OFFSET_SPDIFIN 0x7A /* ch 0x14 ADB source. */ 88#define OFFSET_SPDIFOUT 0x92 /* ch 0x14 ADB sink. */ 89#define OFFSET_AC98IN 0x7c /* ch 0x14 ADB source. */ 90#define OFFSET_AC98OUT 0x94 /* ch 0x14 ADB sink. */ 91#define OFFSET_EQIN 0xa0 /* ch 0x11 */ 92#define OFFSET_EQOUT 0x7e /* ch 0x11 */ /* 2 routes on ch 0x11 */ 93#define OFFSET_A3DIN 0x70 /* ADB sink. */ 94#define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */ 95#define OFFSET_WT0 0x40 /* WT bank 0 output. 0x40 - 0x65 */ 96#define OFFSET_WT1 0x80 /* WT bank 1 output. 0x80 - 0xA5 */ 97/* WT sources offset : 0x00-0x1f Direct stream. */ 98/* WT sources offset : 0x20-0x25 Mixed Output. */ 99#define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) 2 routes */ 100#define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink). 10 routes */ 101#define OFFSET_EFXOUT 0x68 /* ADB source. 8 routes. */ 102#define OFFSET_EFXIN 0x80 /* ADB sink. 8 routes. */ 103 104/* ADB route translate helper */ 105#define ADB_DMA(x) (x) 106#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) 107#define ADB_SRCIN(x) (x + OFFSET_SRCIN) 108#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) 109#define ADB_MIXIN(x) (x + OFFSET_MIXIN) 110#define ADB_CODECIN(x) (x + OFFSET_CODECIN) 111#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) 112#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) 113#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) 114#define ADB_SPDIFIN(x) (x + OFFSET_SPDIFIN) 115#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT) 116#define ADB_EQIN(x) (x + OFFSET_EQIN) 117#define ADB_EQOUT(x) (x + OFFSET_EQOUT) 118#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */ 119#define ADB_A3DIN(x) (x + OFFSET_A3DIN) 120//#define ADB_WTOUT(x) ((x<x20)?(x + OFFSET_WT0):(x + OFFSET_WT1)) 121#define ADB_WTOUT(x,y) (((x)==0)?((y) + OFFSET_WT0):((y) + OFFSET_WT1)) 122#define ADB_XTALKIN(x) ((x) + OFFSET_XTALKIN) 123#define ADB_XTALKOUT(x) ((x) + OFFSET_XTALKOUT) 124 125#define MIX_DEFIGAIN 0x08 126#define MIX_DEFOGAIN 0x08 /* 0x8->6dB (6dB = x4) 16 to 18 bit conversion? */ 127 128/* MIXER */ 129#define VORTEX_MIXER_SR 0x21f00 130#define VORTEX_MIXER_CLIP 0x21f80 131#define VORTEX_MIXER_CHNBASE 0x21e40 132#define VORTEX_MIXER_RTBASE 0x21e00 133#define MIXER_RTBASE_SIZE 0x38 134#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */ 135#define VORTEX_MIX_SMP 0x21c00 /* wave data buffers. AU8820: 0x9c00 */ 136 137/* MIX */ 138#define VORTEX_MIX_INVOL_B 0x20000 /* Input volume current */ 139#define VORTEX_MIX_VOL_B 0x20800 /* Output Volume current */ 140#define VORTEX_MIX_INVOL_A 0x21000 /* Input Volume target */ 141#define VORTEX_MIX_VOL_A 0x21800 /* Output Volume target */ 142 143#define VOL_MIN 0x80 /* Input volume when muted. */ 144#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ 145 146/* SRC */ 147#define VORTEX_SRC_CHNBASE 0x26c40 148#define VORTEX_SRC_RTBASE 0x26c00 149#define VORTEX_SRCBLOCK_SR 0x26cc0 150#define VORTEX_SRC_SOURCE 0x26cc4 151#define VORTEX_SRC_SOURCESIZE 0x26cc8 152/* Params 153 0x26e00 : 1 U0 154 0x26e40 : 2 CR 155 0x26e80 : 3 U3 156 0x26ec0 : 4 DRIFT1 157 0x26f00 : 5 U1 158 0x26f40 : 6 DRIFT2 159 0x26f80 : 7 U2 : Target rate, direction 160*/ 161 162#define VORTEX_SRC_CONVRATIO 0x26e40 163#define VORTEX_SRC_DRIFT0 0x26e80 164#define VORTEX_SRC_DRIFT1 0x26ec0 165#define VORTEX_SRC_DRIFT2 0x26f40 166#define VORTEX_SRC_U0 0x26e00 167#define U0_SLOWLOCK 0x200 168#define VORTEX_SRC_U1 0x26f00 169#define VORTEX_SRC_U2 0x26f80 170#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */ 171#define VORTEX_SRC_DATA0 0x26000 172 173/* FIFO */ 174#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */ 175#define VORTEX_FIFO_WTCTRL 0x16000 176#define FIFO_RDONLY 0x00000001 177#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ 178#define FIFO_VALID 0x00000010 179#define FIFO_EMPTY 0x00000020 180#define FIFO_U0 0x00002000 /* Unknown. */ 181#define FIFO_U1 0x00040000 182#define FIFO_SIZE_BITS 6 183#define FIFO_SIZE (1<<(FIFO_SIZE_BITS)) // 0x40 184#define FIFO_MASK (FIFO_SIZE-1) //0x3f /* at shift left 0xc */ 185#define FIFO_BITS 0x1c400000 186#define VORTEX_FIFO_ADBDATA 0x14000 187#define VORTEX_FIFO_WTDATA 0x10000 188 189#define VORTEX_FIFO_GIRT 0x17000 /* wt0, wt1, adb */ 190#define GIRT_COUNT 3 191 192/* CODEC */ 193 194#define VORTEX_CODEC_CHN 0x29080 /* The name "CHN" is wrong. */ 195 196#define VORTEX_CODEC_CTRL 0x29184 197#define VORTEX_CODEC_IO 0x29188 198 199#define VORTEX_CODEC_SPORTCTRL 0x2918c 200 201#define VORTEX_CODEC_EN 0x29190 202#define EN_AUDIO0 0x00000300 203#define EN_MODEM 0x00000c00 204#define EN_AUDIO1 0x00003000 205#define EN_SPORT 0x00030000 206#define EN_SPDIF 0x000c0000 207#define EN_CODEC (EN_AUDIO1 | EN_AUDIO0) 208 209#define VORTEX_SPDIF_SMPRATE 0x29194 210 211#define VORTEX_SPDIF_FLAGS 0x2205c 212#define VORTEX_SPDIF_CFG0 0x291D0 /* status data */ 213#define VORTEX_SPDIF_CFG1 0x291D4 214 215#define VORTEX_SMP_TIME 0x29198 /* Sample counter/timer */ 216#define VORTEX_SMP_TIMER 0x2919c 217#define VORTEX_CODEC2_CTRL 0x291a0 218 219#define VORTEX_MODEM_CTRL 0x291ac 220 221/* IRQ */ 222#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */ 223#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */ 224 225//#define VORTEX_IRQ_U0 0x2a008 /* ?? */ 226#define VORTEX_STAT 0x2a008 /* Some sort of status */ 227#define STAT_IRQ 0x00000001 /* This bitis set if the IRQ is valid. */ 228 229#define VORTEX_CTRL 0x2a00c 230#define CTRL_MIDI_EN 0x00000001 231#define CTRL_MIDI_PORT 0x00000060 232#define CTRL_GAME_EN 0x00000008 233#define CTRL_GAME_PORT 0x00000e00 234#define CTRL_IRQ_ENABLE 0x00004000 235#define CTRL_SPDIF 0x00000000 /* unknown. Please find this value */ 236#define CTRL_SPORT 0x00200000 237#define CTRL_RST 0x00800000 238#define CTRL_UNKNOWN 0x01000000 239 240/* write: Timer period config / read: TIMER IRQ ack. */ 241#define VORTEX_IRQ_STAT 0x2919c 242 243 /* MIDI *//* GAME. */ 244#define VORTEX_MIDI_DATA 0x28800 245#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */ 246 247#define VORTEX_GAME_LEGACY 0x28808 248#define VORTEX_CTRL2 0x2880c 249#define CTRL2_GAME_ADCMODE 0x40 250#define VORTEX_GAME_AXIS 0x28810 /* Axis base register. 4 axis's */ 251#define AXIS_SIZE 4 252#define AXIS_RANGE 0x1fff 253