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11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/interrupt.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/module.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/ac97_codec.h>
21#include <sound/info.h>
22#include <sound/initval.h>
23
24MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
25MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
26 "SiS 7013; NVidia MCP/2/2S/3 modems");
27MODULE_LICENSE("GPL");
28
29static int index = -2;
30static char *id = SNDRV_DEFAULT_STR1;
31static int ac97_clock;
32
33module_param(index, int, 0444);
34MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
35module_param(id, charp, 0444);
36MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
37module_param(ac97_clock, int, 0444);
38MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
39
40
41static bool enable;
42module_param(enable, bool, 0444);
43
44
45
46
47enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
48
49#define ICHREG(x) ICH_REG_##x
50
51#define DEFINE_REGSET(name,base) \
52enum { \
53 ICH_REG_##name##_BDBAR = base + 0x0, \
54 ICH_REG_##name##_CIV = base + 0x04, \
55 ICH_REG_##name##_LVI = base + 0x05, \
56 ICH_REG_##name##_SR = base + 0x06, \
57 ICH_REG_##name##_PICB = base + 0x08, \
58 ICH_REG_##name##_PIV = base + 0x0a, \
59 ICH_REG_##name##_CR = base + 0x0b, \
60}
61
62
63DEFINE_REGSET(OFF, 0);
64
65
66
67
68#define ICH_REG_LVI_MASK 0x1f
69
70
71#define ICH_FIFOE 0x10
72#define ICH_BCIS 0x08
73#define ICH_LVBCI 0x04
74#define ICH_CELV 0x02
75#define ICH_DCH 0x01
76
77
78#define ICH_REG_PIV_MASK 0x1f
79
80
81#define ICH_IOCE 0x10
82#define ICH_FEIE 0x08
83#define ICH_LVBIE 0x04
84#define ICH_RESETREGS 0x02
85#define ICH_STARTBM 0x01
86
87
88
89#define ICH_REG_GLOB_CNT 0x3c
90#define ICH_TRIE 0x00000040
91#define ICH_SRIE 0x00000020
92#define ICH_PRIE 0x00000010
93#define ICH_ACLINK 0x00000008
94#define ICH_AC97WARM 0x00000004
95#define ICH_AC97COLD 0x00000002
96#define ICH_GIE 0x00000001
97#define ICH_REG_GLOB_STA 0x40
98#define ICH_TRI 0x20000000
99#define ICH_TCR 0x10000000
100#define ICH_BCS 0x08000000
101#define ICH_SPINT 0x04000000
102#define ICH_P2INT 0x02000000
103#define ICH_M2INT 0x01000000
104#define ICH_SAMPLE_CAP 0x00c00000
105#define ICH_MULTICHAN_CAP 0x00300000
106#define ICH_MD3 0x00020000
107#define ICH_AD3 0x00010000
108#define ICH_RCS 0x00008000
109#define ICH_BIT3 0x00004000
110#define ICH_BIT2 0x00002000
111#define ICH_BIT1 0x00001000
112#define ICH_SRI 0x00000800
113#define ICH_PRI 0x00000400
114#define ICH_SCR 0x00000200
115#define ICH_PCR 0x00000100
116#define ICH_MCINT 0x00000080
117#define ICH_POINT 0x00000040
118#define ICH_PIINT 0x00000020
119#define ICH_NVSPINT 0x00000010
120#define ICH_MOINT 0x00000004
121#define ICH_MIINT 0x00000002
122#define ICH_GSCI 0x00000001
123#define ICH_REG_ACC_SEMA 0x44
124#define ICH_CAS 0x01
125
126#define ICH_MAX_FRAGS 32
127
128
129
130
131
132
133enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
134enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
135
136#define get_ichdev(substream) (substream->runtime->private_data)
137
138struct ichdev {
139 unsigned int ichd;
140 unsigned long reg_offset;
141 __le32 *bdbar;
142 unsigned int bdbar_addr;
143 struct snd_pcm_substream *substream;
144 unsigned int physbuf;
145 unsigned int size;
146 unsigned int fragsize;
147 unsigned int fragsize1;
148 unsigned int position;
149 int frags;
150 int lvi;
151 int lvi_frag;
152 int civ;
153 int ack;
154 int ack_reload;
155 unsigned int ack_bit;
156 unsigned int roff_sr;
157 unsigned int roff_picb;
158 unsigned int int_sta_mask;
159 unsigned int ali_slot;
160 struct snd_ac97 *ac97;
161};
162
163struct intel8x0m {
164 unsigned int device_type;
165
166 int irq;
167
168 void __iomem *addr;
169 void __iomem *bmaddr;
170
171 struct pci_dev *pci;
172 struct snd_card *card;
173
174 int pcm_devs;
175 struct snd_pcm *pcm[2];
176 struct ichdev ichd[2];
177
178 unsigned int in_ac97_init: 1;
179
180 struct snd_ac97_bus *ac97_bus;
181 struct snd_ac97 *ac97;
182
183 spinlock_t reg_lock;
184
185 struct snd_dma_buffer *bdbars;
186 u32 bdbars_count;
187 u32 int_sta_reg;
188 u32 int_sta_mask;
189 unsigned int pcm_pos_shift;
190};
191
192static const struct pci_device_id snd_intel8x0m_ids[] = {
193 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL },
194 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL },
195 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL },
196 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL },
197 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL },
198 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL },
199 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL },
200 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL },
201 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL },
202 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL },
203 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS },
204 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE },
205 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE },
206 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE },
207 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE },
208 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL },
209#if 0
210 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },
211#endif
212 { 0, }
213};
214
215MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
216
217
218
219
220
221static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
222{
223 return ioread8(chip->bmaddr + offset);
224}
225
226static inline u16 igetword(struct intel8x0m *chip, u32 offset)
227{
228 return ioread16(chip->bmaddr + offset);
229}
230
231static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
232{
233 return ioread32(chip->bmaddr + offset);
234}
235
236static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
237{
238 iowrite8(val, chip->bmaddr + offset);
239}
240
241static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
242{
243 iowrite16(val, chip->bmaddr + offset);
244}
245
246static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
247{
248 iowrite32(val, chip->bmaddr + offset);
249}
250
251
252
253
254
255static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
256{
257 return ioread16(chip->addr + offset);
258}
259
260static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
261{
262 iowrite16(val, chip->addr + offset);
263}
264
265
266
267
268
269
270
271
272
273
274static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
275{
276 static const unsigned int codec_bit[3] = {
277 ICH_PCR, ICH_SCR, ICH_TCR
278 };
279 if (snd_BUG_ON(codec >= 3))
280 return ICH_PCR;
281 return codec_bit[codec];
282}
283
284static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
285{
286 int time;
287
288 if (codec > 1)
289 return -EIO;
290 codec = get_ich_codec_bit(chip, codec);
291
292
293 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
294 return -EIO;
295
296
297 time = 100;
298 do {
299 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
300 return 0;
301 udelay(10);
302 } while (time--);
303
304
305
306
307 dev_err(chip->card->dev,
308 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
309 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
310 iagetword(chip, 0);
311
312 return -EBUSY;
313}
314
315static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
316 unsigned short reg,
317 unsigned short val)
318{
319 struct intel8x0m *chip = ac97->private_data;
320
321 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
322 if (! chip->in_ac97_init)
323 dev_err(chip->card->dev,
324 "codec_write %d: semaphore is not ready for register 0x%x\n",
325 ac97->num, reg);
326 }
327 iaputword(chip, reg + ac97->num * 0x80, val);
328}
329
330static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
331 unsigned short reg)
332{
333 struct intel8x0m *chip = ac97->private_data;
334 unsigned short res;
335 unsigned int tmp;
336
337 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
338 if (! chip->in_ac97_init)
339 dev_err(chip->card->dev,
340 "codec_read %d: semaphore is not ready for register 0x%x\n",
341 ac97->num, reg);
342 res = 0xffff;
343 } else {
344 res = iagetword(chip, reg + ac97->num * 0x80);
345 tmp = igetdword(chip, ICHREG(GLOB_STA));
346 if (tmp & ICH_RCS) {
347
348 iputdword(chip, ICHREG(GLOB_STA),
349 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
350 if (! chip->in_ac97_init)
351 dev_err(chip->card->dev,
352 "codec_read %d: read timeout for register 0x%x\n",
353 ac97->num, reg);
354 res = 0xffff;
355 }
356 }
357 if (reg == AC97_GPIO_STATUS)
358 iagetword(chip, 0);
359 return res;
360}
361
362
363
364
365
366static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
367{
368 int idx;
369 __le32 *bdbar = ichdev->bdbar;
370 unsigned long port = ichdev->reg_offset;
371
372 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
373 if (ichdev->size == ichdev->fragsize) {
374 ichdev->ack_reload = ichdev->ack = 2;
375 ichdev->fragsize1 = ichdev->fragsize >> 1;
376 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
377 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
378 bdbar[idx + 1] = cpu_to_le32(0x80000000 |
379 ichdev->fragsize1 >> chip->pcm_pos_shift);
380 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
381 bdbar[idx + 3] = cpu_to_le32(0x80000000 |
382 ichdev->fragsize1 >> chip->pcm_pos_shift);
383 }
384 ichdev->frags = 2;
385 } else {
386 ichdev->ack_reload = ichdev->ack = 1;
387 ichdev->fragsize1 = ichdev->fragsize;
388 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
389 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
390 bdbar[idx + 1] = cpu_to_le32(0x80000000 |
391 ichdev->fragsize >> chip->pcm_pos_shift);
392
393
394
395
396 }
397 ichdev->frags = ichdev->size / ichdev->fragsize;
398 }
399 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
400 ichdev->civ = 0;
401 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
402 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
403 ichdev->position = 0;
404#if 0
405 dev_dbg(chip->card->dev,
406 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
407 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
408 ichdev->fragsize1);
409#endif
410
411 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
412}
413
414
415
416
417
418static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
419{
420 unsigned long port = ichdev->reg_offset;
421 int civ, i, step;
422 int ack = 0;
423
424 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
425 if (civ == ichdev->civ) {
426
427 step = 1;
428 ichdev->civ++;
429 ichdev->civ &= ICH_REG_LVI_MASK;
430 } else {
431 step = civ - ichdev->civ;
432 if (step < 0)
433 step += ICH_REG_LVI_MASK + 1;
434
435
436 ichdev->civ = civ;
437 }
438
439 ichdev->position += step * ichdev->fragsize1;
440 ichdev->position %= ichdev->size;
441 ichdev->lvi += step;
442 ichdev->lvi &= ICH_REG_LVI_MASK;
443 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
444 for (i = 0; i < step; i++) {
445 ichdev->lvi_frag++;
446 ichdev->lvi_frag %= ichdev->frags;
447 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
448 ichdev->lvi_frag *
449 ichdev->fragsize1);
450#if 0
451 dev_dbg(chip->card->dev,
452 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
453 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
454 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
455 inl(port + 4), inb(port + ICH_REG_OFF_CR));
456#endif
457 if (--ichdev->ack == 0) {
458 ichdev->ack = ichdev->ack_reload;
459 ack = 1;
460 }
461 }
462 if (ack && ichdev->substream) {
463 spin_unlock(&chip->reg_lock);
464 snd_pcm_period_elapsed(ichdev->substream);
465 spin_lock(&chip->reg_lock);
466 }
467 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
468}
469
470static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
471{
472 struct intel8x0m *chip = dev_id;
473 struct ichdev *ichdev;
474 unsigned int status;
475 unsigned int i;
476
477 spin_lock(&chip->reg_lock);
478 status = igetdword(chip, chip->int_sta_reg);
479 if (status == 0xffffffff) {
480 spin_unlock(&chip->reg_lock);
481 return IRQ_NONE;
482 }
483 if ((status & chip->int_sta_mask) == 0) {
484 if (status)
485 iputdword(chip, chip->int_sta_reg, status);
486 spin_unlock(&chip->reg_lock);
487 return IRQ_NONE;
488 }
489
490 for (i = 0; i < chip->bdbars_count; i++) {
491 ichdev = &chip->ichd[i];
492 if (status & ichdev->int_sta_mask)
493 snd_intel8x0m_update(chip, ichdev);
494 }
495
496
497 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
498 spin_unlock(&chip->reg_lock);
499
500 return IRQ_HANDLED;
501}
502
503
504
505
506
507static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
508{
509 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
510 struct ichdev *ichdev = get_ichdev(substream);
511 unsigned char val = 0;
512 unsigned long port = ichdev->reg_offset;
513
514 switch (cmd) {
515 case SNDRV_PCM_TRIGGER_START:
516 case SNDRV_PCM_TRIGGER_RESUME:
517 val = ICH_IOCE | ICH_STARTBM;
518 break;
519 case SNDRV_PCM_TRIGGER_STOP:
520 case SNDRV_PCM_TRIGGER_SUSPEND:
521 val = 0;
522 break;
523 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
524 val = ICH_IOCE;
525 break;
526 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
527 val = ICH_IOCE | ICH_STARTBM;
528 break;
529 default:
530 return -EINVAL;
531 }
532 iputbyte(chip, port + ICH_REG_OFF_CR, val);
533 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
534
535 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
536
537 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
538 }
539 return 0;
540}
541
542static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
543{
544 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
545 struct ichdev *ichdev = get_ichdev(substream);
546 size_t ptr1, ptr;
547
548 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
549 if (ptr1 != 0)
550 ptr = ichdev->fragsize1 - ptr1;
551 else
552 ptr = 0;
553 ptr += ichdev->position;
554 if (ptr >= ichdev->size)
555 return 0;
556 return bytes_to_frames(substream->runtime, ptr);
557}
558
559static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
560{
561 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
562 struct snd_pcm_runtime *runtime = substream->runtime;
563 struct ichdev *ichdev = get_ichdev(substream);
564
565 ichdev->physbuf = runtime->dma_addr;
566 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
567 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
568 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
569 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
570 snd_intel8x0m_setup_periods(chip, ichdev);
571 return 0;
572}
573
574static const struct snd_pcm_hardware snd_intel8x0m_stream =
575{
576 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
577 SNDRV_PCM_INFO_BLOCK_TRANSFER |
578 SNDRV_PCM_INFO_MMAP_VALID |
579 SNDRV_PCM_INFO_PAUSE |
580 SNDRV_PCM_INFO_RESUME),
581 .formats = SNDRV_PCM_FMTBIT_S16_LE,
582 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
583 .rate_min = 8000,
584 .rate_max = 16000,
585 .channels_min = 1,
586 .channels_max = 1,
587 .buffer_bytes_max = 64 * 1024,
588 .period_bytes_min = 32,
589 .period_bytes_max = 64 * 1024,
590 .periods_min = 1,
591 .periods_max = 1024,
592 .fifo_size = 0,
593};
594
595
596static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
597{
598 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
599 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
600 .count = ARRAY_SIZE(rates),
601 .list = rates,
602 .mask = 0,
603 };
604 struct snd_pcm_runtime *runtime = substream->runtime;
605 int err;
606
607 ichdev->substream = substream;
608 runtime->hw = snd_intel8x0m_stream;
609 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
610 &hw_constraints_rates);
611 if ( err < 0 )
612 return err;
613 runtime->private_data = ichdev;
614 return 0;
615}
616
617static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
618{
619 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
620
621 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
622}
623
624static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
625{
626 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
627
628 chip->ichd[ICHD_MDMOUT].substream = NULL;
629 return 0;
630}
631
632static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
633{
634 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
635
636 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
637}
638
639static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
640{
641 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
642
643 chip->ichd[ICHD_MDMIN].substream = NULL;
644 return 0;
645}
646
647
648static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
649 .open = snd_intel8x0m_playback_open,
650 .close = snd_intel8x0m_playback_close,
651 .prepare = snd_intel8x0m_pcm_prepare,
652 .trigger = snd_intel8x0m_pcm_trigger,
653 .pointer = snd_intel8x0m_pcm_pointer,
654};
655
656static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
657 .open = snd_intel8x0m_capture_open,
658 .close = snd_intel8x0m_capture_close,
659 .prepare = snd_intel8x0m_pcm_prepare,
660 .trigger = snd_intel8x0m_pcm_trigger,
661 .pointer = snd_intel8x0m_pcm_pointer,
662};
663
664
665struct ich_pcm_table {
666 char *suffix;
667 const struct snd_pcm_ops *playback_ops;
668 const struct snd_pcm_ops *capture_ops;
669 size_t prealloc_size;
670 size_t prealloc_max_size;
671 int ac97_idx;
672};
673
674static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
675 const struct ich_pcm_table *rec)
676{
677 struct snd_pcm *pcm;
678 int err;
679 char name[32];
680
681 if (rec->suffix)
682 sprintf(name, "Intel ICH - %s", rec->suffix);
683 else
684 strcpy(name, "Intel ICH");
685 err = snd_pcm_new(chip->card, name, device,
686 rec->playback_ops ? 1 : 0,
687 rec->capture_ops ? 1 : 0, &pcm);
688 if (err < 0)
689 return err;
690
691 if (rec->playback_ops)
692 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
693 if (rec->capture_ops)
694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
695
696 pcm->private_data = chip;
697 pcm->info_flags = 0;
698 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
699 if (rec->suffix)
700 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
701 else
702 strcpy(pcm->name, chip->card->shortname);
703 chip->pcm[device] = pcm;
704
705 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
706 &chip->pci->dev,
707 rec->prealloc_size,
708 rec->prealloc_max_size);
709
710 return 0;
711}
712
713static const struct ich_pcm_table intel_pcms[] = {
714 {
715 .suffix = "Modem",
716 .playback_ops = &snd_intel8x0m_playback_ops,
717 .capture_ops = &snd_intel8x0m_capture_ops,
718 .prealloc_size = 32 * 1024,
719 .prealloc_max_size = 64 * 1024,
720 },
721};
722
723static int snd_intel8x0m_pcm(struct intel8x0m *chip)
724{
725 int i, tblsize, device, err;
726 const struct ich_pcm_table *tbl, *rec;
727
728#if 1
729 tbl = intel_pcms;
730 tblsize = 1;
731#else
732 switch (chip->device_type) {
733 case DEVICE_NFORCE:
734 tbl = nforce_pcms;
735 tblsize = ARRAY_SIZE(nforce_pcms);
736 break;
737 case DEVICE_ALI:
738 tbl = ali_pcms;
739 tblsize = ARRAY_SIZE(ali_pcms);
740 break;
741 default:
742 tbl = intel_pcms;
743 tblsize = 2;
744 break;
745 }
746#endif
747 device = 0;
748 for (i = 0; i < tblsize; i++) {
749 rec = tbl + i;
750 if (i > 0 && rec->ac97_idx) {
751
752 if (! chip->ichd[rec->ac97_idx].ac97)
753 continue;
754 }
755 err = snd_intel8x0m_pcm1(chip, device, rec);
756 if (err < 0)
757 return err;
758 device++;
759 }
760
761 chip->pcm_devs = device;
762 return 0;
763}
764
765
766
767
768
769
770static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
771{
772 struct intel8x0m *chip = bus->private_data;
773 chip->ac97_bus = NULL;
774}
775
776static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
777{
778 struct intel8x0m *chip = ac97->private_data;
779 chip->ac97 = NULL;
780}
781
782
783static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
784{
785 struct snd_ac97_bus *pbus;
786 struct snd_ac97_template ac97;
787 struct snd_ac97 *x97;
788 int err;
789 unsigned int glob_sta = 0;
790 static const struct snd_ac97_bus_ops ops = {
791 .write = snd_intel8x0m_codec_write,
792 .read = snd_intel8x0m_codec_read,
793 };
794
795 chip->in_ac97_init = 1;
796
797 memset(&ac97, 0, sizeof(ac97));
798 ac97.private_data = chip;
799 ac97.private_free = snd_intel8x0m_mixer_free_ac97;
800 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
801
802 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
803
804 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
805 if (err < 0)
806 goto __err;
807 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
808 if (ac97_clock >= 8000 && ac97_clock <= 48000)
809 pbus->clock = ac97_clock;
810 chip->ac97_bus = pbus;
811
812 ac97.pci = chip->pci;
813 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
814 err = snd_ac97_mixer(pbus, &ac97, &x97);
815 if (err < 0) {
816 dev_err(chip->card->dev,
817 "Unable to initialize codec #%d\n", ac97.num);
818 if (ac97.num == 0)
819 goto __err;
820 return err;
821 }
822 chip->ac97 = x97;
823 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
824 chip->ichd[ICHD_MDMIN].ac97 = x97;
825 chip->ichd[ICHD_MDMOUT].ac97 = x97;
826 }
827
828 chip->in_ac97_init = 0;
829 return 0;
830
831 __err:
832
833 if (chip->device_type != DEVICE_ALI)
834 iputdword(chip, ICHREG(GLOB_CNT),
835 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
836 return err;
837}
838
839
840
841
842
843
844static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
845{
846 unsigned long end_time;
847 unsigned int cnt, status, nstatus;
848
849
850
851 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
852 cnt = igetdword(chip, ICHREG(GLOB_STA));
853 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
854
855
856 cnt = igetdword(chip, ICHREG(GLOB_CNT));
857 cnt &= ~(ICH_ACLINK);
858
859 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
860 iputdword(chip, ICHREG(GLOB_CNT), cnt);
861 usleep_range(500, 1000);
862 end_time = jiffies + HZ / 4;
863 do {
864 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
865 goto __ok;
866 schedule_timeout_uninterruptible(1);
867 } while (time_after_eq(end_time, jiffies));
868 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
869 igetdword(chip, ICHREG(GLOB_CNT)));
870 return -EIO;
871
872 __ok:
873 if (probing) {
874
875
876
877
878 end_time = jiffies + HZ;
879 do {
880 status = igetdword(chip, ICHREG(GLOB_STA)) &
881 (ICH_PCR | ICH_SCR | ICH_TCR);
882 if (status)
883 break;
884 schedule_timeout_uninterruptible(1);
885 } while (time_after_eq(end_time, jiffies));
886 if (! status) {
887
888 dev_err(chip->card->dev,
889 "codec_ready: codec is not ready [0x%x]\n",
890 igetdword(chip, ICHREG(GLOB_STA)));
891 return -EIO;
892 }
893
894
895 nstatus = ICH_PCR | ICH_SCR;
896
897
898 end_time = jiffies + HZ / 4;
899 while (status != nstatus && time_after_eq(end_time, jiffies)) {
900 schedule_timeout_uninterruptible(1);
901 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
902 }
903
904 } else {
905
906 status = 0;
907 if (chip->ac97)
908 status |= get_ich_codec_bit(chip, chip->ac97->num);
909
910 end_time = jiffies + HZ;
911 do {
912 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
913 (ICH_PCR | ICH_SCR | ICH_TCR);
914 if (status == nstatus)
915 break;
916 schedule_timeout_uninterruptible(1);
917 } while (time_after_eq(end_time, jiffies));
918 }
919
920 if (chip->device_type == DEVICE_SIS) {
921
922 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
923 }
924
925 return 0;
926}
927
928static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
929{
930 unsigned int i;
931 int err;
932
933 err = snd_intel8x0m_ich_chip_init(chip, probing);
934 if (err < 0)
935 return err;
936 iagetword(chip, 0);
937
938
939 for (i = 0; i < chip->bdbars_count; i++)
940 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
941
942 for (i = 0; i < chip->bdbars_count; i++)
943 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
944
945 for (i = 0; i < chip->bdbars_count; i++)
946 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
947 return 0;
948}
949
950static void snd_intel8x0m_free(struct snd_card *card)
951{
952 struct intel8x0m *chip = card->private_data;
953 unsigned int i;
954
955 if (chip->irq < 0)
956 goto __hw_end;
957
958 for (i = 0; i < chip->bdbars_count; i++)
959 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
960
961 for (i = 0; i < chip->bdbars_count; i++)
962 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
963 __hw_end:
964 if (chip->irq >= 0)
965 free_irq(chip->irq, chip);
966}
967
968#ifdef CONFIG_PM_SLEEP
969
970
971
972static int intel8x0m_suspend(struct device *dev)
973{
974 struct snd_card *card = dev_get_drvdata(dev);
975 struct intel8x0m *chip = card->private_data;
976
977 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
978 snd_ac97_suspend(chip->ac97);
979 if (chip->irq >= 0) {
980 free_irq(chip->irq, chip);
981 chip->irq = -1;
982 card->sync_irq = -1;
983 }
984 return 0;
985}
986
987static int intel8x0m_resume(struct device *dev)
988{
989 struct pci_dev *pci = to_pci_dev(dev);
990 struct snd_card *card = dev_get_drvdata(dev);
991 struct intel8x0m *chip = card->private_data;
992
993 if (request_irq(pci->irq, snd_intel8x0m_interrupt,
994 IRQF_SHARED, KBUILD_MODNAME, chip)) {
995 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
996 pci->irq);
997 snd_card_disconnect(card);
998 return -EIO;
999 }
1000 chip->irq = pci->irq;
1001 card->sync_irq = chip->irq;
1002 snd_intel8x0m_chip_init(chip, 0);
1003 snd_ac97_resume(chip->ac97);
1004
1005 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1006 return 0;
1007}
1008
1009static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1010#define INTEL8X0M_PM_OPS &intel8x0m_pm
1011#else
1012#define INTEL8X0M_PM_OPS NULL
1013#endif
1014
1015static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1016 struct snd_info_buffer *buffer)
1017{
1018 struct intel8x0m *chip = entry->private_data;
1019 unsigned int tmp;
1020
1021 snd_iprintf(buffer, "Intel8x0m\n\n");
1022 if (chip->device_type == DEVICE_ALI)
1023 return;
1024 tmp = igetdword(chip, ICHREG(GLOB_STA));
1025 snd_iprintf(buffer, "Global control : 0x%08x\n",
1026 igetdword(chip, ICHREG(GLOB_CNT)));
1027 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1028 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1029 tmp & ICH_PCR ? " primary" : "",
1030 tmp & ICH_SCR ? " secondary" : "",
1031 tmp & ICH_TCR ? " tertiary" : "",
1032 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1033}
1034
1035static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1036{
1037 snd_card_ro_proc_new(chip->card, "intel8x0m", chip,
1038 snd_intel8x0m_proc_read);
1039}
1040
1041struct ich_reg_info {
1042 unsigned int int_sta_mask;
1043 unsigned int offset;
1044};
1045
1046static int snd_intel8x0m_init(struct snd_card *card,
1047 struct pci_dev *pci,
1048 unsigned long device_type)
1049{
1050 struct intel8x0m *chip = card->private_data;
1051 int err;
1052 unsigned int i;
1053 unsigned int int_sta_masks;
1054 struct ichdev *ichdev;
1055 static const struct ich_reg_info intel_regs[2] = {
1056 { ICH_MIINT, 0 },
1057 { ICH_MOINT, 0x10 },
1058 };
1059 const struct ich_reg_info *tbl;
1060
1061 err = pcim_enable_device(pci);
1062 if (err < 0)
1063 return err;
1064
1065 spin_lock_init(&chip->reg_lock);
1066 chip->device_type = device_type;
1067 chip->card = card;
1068 chip->pci = pci;
1069 chip->irq = -1;
1070
1071 err = pci_request_regions(pci, card->shortname);
1072 if (err < 0)
1073 return err;
1074
1075 if (device_type == DEVICE_ALI) {
1076
1077 chip->bmaddr = pcim_iomap(pci, 0, 0);
1078 } else {
1079 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM)
1080 chip->addr = pcim_iomap(pci, 2, 0);
1081 else
1082 chip->addr = pcim_iomap(pci, 0, 0);
1083 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM)
1084 chip->bmaddr = pcim_iomap(pci, 3, 0);
1085 else
1086 chip->bmaddr = pcim_iomap(pci, 1, 0);
1087 }
1088
1089
1090 chip->bdbars_count = 2;
1091 tbl = intel_regs;
1092
1093 for (i = 0; i < chip->bdbars_count; i++) {
1094 ichdev = &chip->ichd[i];
1095 ichdev->ichd = i;
1096 ichdev->reg_offset = tbl[i].offset;
1097 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1098 if (device_type == DEVICE_SIS) {
1099
1100 ichdev->roff_sr = ICH_REG_OFF_PICB;
1101 ichdev->roff_picb = ICH_REG_OFF_SR;
1102 } else {
1103 ichdev->roff_sr = ICH_REG_OFF_SR;
1104 ichdev->roff_picb = ICH_REG_OFF_PICB;
1105 }
1106 if (device_type == DEVICE_ALI)
1107 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1108 }
1109
1110 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1111
1112
1113
1114 chip->bdbars = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV,
1115 chip->bdbars_count * sizeof(u32) *
1116 ICH_MAX_FRAGS * 2);
1117 if (!chip->bdbars)
1118 return -ENOMEM;
1119
1120
1121
1122 int_sta_masks = 0;
1123 for (i = 0; i < chip->bdbars_count; i++) {
1124 ichdev = &chip->ichd[i];
1125 ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2);
1126 ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1127 int_sta_masks |= ichdev->int_sta_mask;
1128 }
1129 chip->int_sta_reg = ICH_REG_GLOB_STA;
1130 chip->int_sta_mask = int_sta_masks;
1131
1132 pci_set_master(pci);
1133
1134 err = snd_intel8x0m_chip_init(chip, 1);
1135 if (err < 0)
1136 return err;
1137
1138
1139
1140
1141
1142 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
1143 KBUILD_MODNAME, chip)) {
1144 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1145 return -EBUSY;
1146 }
1147 chip->irq = pci->irq;
1148 card->sync_irq = chip->irq;
1149
1150 card->private_free = snd_intel8x0m_free;
1151
1152 return 0;
1153}
1154
1155static struct shortname_table {
1156 unsigned int id;
1157 const char *s;
1158} shortnames[] = {
1159 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1160 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1161 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1162 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1163 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1164 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1165 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1166 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1167 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1168 { 0x7446, "AMD AMD768" },
1169 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1170 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1171 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1172 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1173 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1174 { 0x746e, "AMD AMD8111" },
1175#if 0
1176 { 0x5455, "ALi M5455" },
1177#endif
1178 { 0 },
1179};
1180
1181static int snd_intel8x0m_probe(struct pci_dev *pci,
1182 const struct pci_device_id *pci_id)
1183{
1184 struct snd_card *card;
1185 struct intel8x0m *chip;
1186 int err;
1187 struct shortname_table *name;
1188
1189 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1190 sizeof(*chip), &card);
1191 if (err < 0)
1192 return err;
1193 chip = card->private_data;
1194
1195 strcpy(card->driver, "ICH-MODEM");
1196 strcpy(card->shortname, "Intel ICH");
1197 for (name = shortnames; name->id; name++) {
1198 if (pci->device == name->id) {
1199 strcpy(card->shortname, name->s);
1200 break;
1201 }
1202 }
1203 strcat(card->shortname," Modem");
1204
1205 err = snd_intel8x0m_init(card, pci, pci_id->driver_data);
1206 if (err < 0)
1207 return err;
1208
1209 err = snd_intel8x0m_mixer(chip, ac97_clock);
1210 if (err < 0)
1211 return err;
1212 err = snd_intel8x0m_pcm(chip);
1213 if (err < 0)
1214 return err;
1215
1216 snd_intel8x0m_proc_init(chip);
1217
1218 sprintf(card->longname, "%s at irq %i",
1219 card->shortname, chip->irq);
1220
1221 err = snd_card_register(card);
1222 if (err < 0)
1223 return err;
1224 pci_set_drvdata(pci, card);
1225 return 0;
1226}
1227
1228static struct pci_driver intel8x0m_driver = {
1229 .name = KBUILD_MODNAME,
1230 .id_table = snd_intel8x0m_ids,
1231 .probe = snd_intel8x0m_probe,
1232 .driver = {
1233 .pm = INTEL8X0M_PM_OPS,
1234 },
1235};
1236
1237module_pci_driver(intel8x0m_driver);
1238
