1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Driver for Digigram miXart soundcards 4 * 5 * definitions and makros for basic card access 6 * 7 * Copyright (c) 2003 by Digigram <alsa@digigram.com> 8 */ 9 10#ifndef __SOUND_MIXART_HWDEP_H 11#define __SOUND_MIXART_HWDEP_H 12 13#include <sound/hwdep.h> 14 15#ifndef readl_be 16#define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x)) 17#endif 18 19#ifndef writel_be 20#define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr) 21#endif 22 23#ifndef readl_le 24#define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x)) 25#endif 26 27#ifndef writel_le 28#define writel_le(data,addr) __raw_writel((__force u32)cpu_to_le32(data),addr) 29#endif 30 31#define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x)) 32#define MIXART_REG(mgr,x) ((mgr)->mem[1].virt + (x)) 33 34 35/* Daughter board Type */ 36#define DAUGHTER_TYPE_MASK 0x0F 37#define DAUGHTER_VER_MASK 0xF0 38#define DAUGHTER_TYPEVER_MASK (DAUGHTER_TYPE_MASK|DAUGHTER_VER_MASK) 39 40#define MIXART_DAUGHTER_TYPE_NONE 0x00 41#define MIXART_DAUGHTER_TYPE_COBRANET 0x08 42#define MIXART_DAUGHTER_TYPE_AES 0x0E 43 44 45 46#define MIXART_BA0_SIZE (16 * 1024 * 1024) /* 16M */ 47#define MIXART_BA1_SIZE (4 * 1024) /* 4k */ 48 49/* 50 * -----------BAR 0 -------------------------------------------------------------------------------------------------------- 51 */ 52#define MIXART_PSEUDOREG 0x2000 /* base address for pseudoregister */ 53 54#define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */ 55 56/* perfmeter (available when elf loaded)*/ 57#define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */ 58#define MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET MIXART_PSEUDOREG+0x78 /* system load (reference)*/ 59#define MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET MIXART_PSEUDOREG+0x7C /* mailbox load */ 60#define MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET MIXART_PSEUDOREG+0x74 /* interrupt handling load */ 61 62/* motherboard xilinx loader info */ 63#define MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x9C /* 0x00600000 */ 64#define MIXART_PSEUDOREG_MXLX_SIZE_OFFSET MIXART_PSEUDOREG+0xA0 /* xilinx size in bytes */ 65#define MIXART_PSEUDOREG_MXLX_STATUS_OFFSET MIXART_PSEUDOREG+0xA4 /* status = EMBEBBED_STAT_XXX */ 66 67/* elf loader info */ 68#define MIXART_PSEUDOREG_ELF_STATUS_OFFSET MIXART_PSEUDOREG+0xB0 /* status = EMBEBBED_STAT_XXX */ 69 70/* 71* after the elf code is loaded, and the flowtable info was passed to it, 72* the driver polls on this address, until it shows 1 (presence) or 2 (absence) 73* once it is non-zero, the daughter board type may be read 74*/ 75#define MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET MIXART_PSEUDOREG+0x990 76 77/* Global info structure */ 78#define MIXART_PSEUDOREG_DBRD_TYPE_OFFSET MIXART_PSEUDOREG+0x994 /* Type and version of daughterboard */ 79 80 81/* daughterboard xilinx loader info */ 82#define MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x998 /* get the address here where to write the file */ 83#define MIXART_PSEUDOREG_DXLX_SIZE_OFFSET MIXART_PSEUDOREG+0x99C /* xilinx size in bytes */ 84#define MIXART_PSEUDOREG_DXLX_STATUS_OFFSET MIXART_PSEUDOREG+0x9A0 /* status = EMBEBBED_STAT_XXX */ 85 86/* */ 87#define MIXART_FLOWTABLE_PTR 0x3000 /* pointer to flow table */ 88 89/* mailbox addresses */ 90 91/* message DRV -> EMB */ 92#define MSG_INBOUND_POST_HEAD 0x010008 /* DRV posts MF + increment4 */ 93#define MSG_INBOUND_POST_TAIL 0x01000C /* EMB gets MF + increment4 */ 94/* message EMB -> DRV */ 95#define MSG_OUTBOUND_POST_TAIL 0x01001C /* DRV gets MF + increment4 */ 96#define MSG_OUTBOUND_POST_HEAD 0x010018 /* EMB posts MF + increment4 */ 97/* Get Free Frames */ 98#define MSG_INBOUND_FREE_TAIL 0x010004 /* DRV gets MFA + increment4 */ 99#define MSG_OUTBOUND_FREE_TAIL 0x010014 /* EMB gets MFA + increment4 */ 100/* Put Free Frames */ 101#define MSG_OUTBOUND_FREE_HEAD 0x010010 /* DRV puts MFA + increment4 */ 102#define MSG_INBOUND_FREE_HEAD 0x010000 /* EMB puts MFA + increment4 */ 103 104/* firmware addresses of the message fifos */ 105#define MSG_BOUND_STACK_SIZE 0x004000 /* size of each following stack */ 106/* posted messages */ 107#define MSG_OUTBOUND_POST_STACK 0x108000 /* stack of messages to the DRV */ 108#define MSG_INBOUND_POST_STACK 0x104000 /* stack of messages to the EMB */ 109/* available empty messages */ 110#define MSG_OUTBOUND_FREE_STACK 0x10C000 /* stack of free enveloped for EMB */ 111#define MSG_INBOUND_FREE_STACK 0x100000 /* stack of free enveloped for DRV */ 112 113 114/* defines for mailbox message frames */ 115#define MSG_FRAME_OFFSET 0x64 116#define MSG_FRAME_SIZE 0x6400 117#define MSG_FRAME_NUMBER 32 118#define MSG_FROM_AGENT_ITMF_OFFSET (MSG_FRAME_OFFSET + (MSG_FRAME_SIZE * MSG_FRAME_NUMBER)) 119#define MSG_TO_AGENT_ITMF_OFFSET (MSG_FROM_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE) 120#define MSG_HOST_RSC_PROTECTION (MSG_TO_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE) 121#define MSG_AGENT_RSC_PROTECTION (MSG_HOST_RSC_PROTECTION + 4) 122 123 124/* 125 * -----------BAR 1 -------------------------------------------------------------------------------------------------------- 126 */ 127 128/* interrupt addresses and constants */ 129#define MIXART_PCI_OMIMR_OFFSET 0x34 /* outbound message interrupt mask register */ 130#define MIXART_PCI_OMISR_OFFSET 0x30 /* outbound message interrupt status register */ 131#define MIXART_PCI_ODBR_OFFSET 0x60 /* outbound doorbell register */ 132 133#define MIXART_BA1_BRUTAL_RESET_OFFSET 0x68 /* write 1 in LSBit to reset board */ 134 135#define MIXART_HOST_ALL_INTERRUPT_MASKED 0x02B /* 0000 0010 1011 */ 136#define MIXART_ALLOW_OUTBOUND_DOORBELL 0x023 /* 0000 0010 0011 */ 137#define MIXART_OIDI 0x008 /* 0000 0000 1000 */ 138 139 140int snd_mixart_setup_firmware(struct mixart_mgr *mgr); 141 142#endif /* __SOUND_MIXART_HWDEP_H */ 143