linux/sound/pci/rme9652/hdsp.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *   ALSA driver for RME Hammerfall DSP audio interface(s)
   4 *
   5 *      Copyright (c) 2002  Paul Davis
   6 *                          Marcus Andersson
   7 *                          Thomas Charbonnel
   8 */
   9
  10#include <linux/init.h>
  11#include <linux/delay.h>
  12#include <linux/interrupt.h>
  13#include <linux/pci.h>
  14#include <linux/firmware.h>
  15#include <linux/module.h>
  16#include <linux/math64.h>
  17#include <linux/vmalloc.h>
  18#include <linux/io.h>
  19#include <linux/nospec.h>
  20
  21#include <sound/core.h>
  22#include <sound/control.h>
  23#include <sound/pcm.h>
  24#include <sound/info.h>
  25#include <sound/asoundef.h>
  26#include <sound/rawmidi.h>
  27#include <sound/hwdep.h>
  28#include <sound/initval.h>
  29#include <sound/hdsp.h>
  30
  31#include <asm/byteorder.h>
  32#include <asm/current.h>
  33
  34static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  35static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  36static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  37
  38module_param_array(index, int, NULL, 0444);
  39MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  40module_param_array(id, charp, NULL, 0444);
  41MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  42module_param_array(enable, bool, NULL, 0444);
  43MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  44MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  45MODULE_DESCRIPTION("RME Hammerfall DSP");
  46MODULE_LICENSE("GPL");
  47MODULE_FIRMWARE("rpm_firmware.bin");
  48MODULE_FIRMWARE("multiface_firmware.bin");
  49MODULE_FIRMWARE("multiface_firmware_rev11.bin");
  50MODULE_FIRMWARE("digiface_firmware.bin");
  51MODULE_FIRMWARE("digiface_firmware_rev11.bin");
  52
  53#define HDSP_MAX_CHANNELS        26
  54#define HDSP_MAX_DS_CHANNELS     14
  55#define HDSP_MAX_QS_CHANNELS     8
  56#define DIGIFACE_SS_CHANNELS     26
  57#define DIGIFACE_DS_CHANNELS     14
  58#define MULTIFACE_SS_CHANNELS    18
  59#define MULTIFACE_DS_CHANNELS    14
  60#define H9652_SS_CHANNELS        26
  61#define H9652_DS_CHANNELS        14
  62/* This does not include possible Analog Extension Boards
  63   AEBs are detected at card initialization
  64*/
  65#define H9632_SS_CHANNELS        12
  66#define H9632_DS_CHANNELS        8
  67#define H9632_QS_CHANNELS        4
  68#define RPM_CHANNELS             6
  69
  70/* Write registers. These are defined as byte-offsets from the iobase value.
  71 */
  72#define HDSP_resetPointer               0
  73#define HDSP_freqReg                    0
  74#define HDSP_outputBufferAddress        32
  75#define HDSP_inputBufferAddress         36
  76#define HDSP_controlRegister            64
  77#define HDSP_interruptConfirmation      96
  78#define HDSP_outputEnable               128
  79#define HDSP_control2Reg                256
  80#define HDSP_midiDataOut0               352
  81#define HDSP_midiDataOut1               356
  82#define HDSP_fifoData                   368
  83#define HDSP_inputEnable                384
  84
  85/* Read registers. These are defined as byte-offsets from the iobase value
  86 */
  87
  88#define HDSP_statusRegister    0
  89#define HDSP_timecode        128
  90#define HDSP_status2Register 192
  91#define HDSP_midiDataIn0     360
  92#define HDSP_midiDataIn1     364
  93#define HDSP_midiStatusOut0  384
  94#define HDSP_midiStatusOut1  388
  95#define HDSP_midiStatusIn0   392
  96#define HDSP_midiStatusIn1   396
  97#define HDSP_fifoStatus      400
  98
  99/* the meters are regular i/o-mapped registers, but offset
 100   considerably from the rest. the peak registers are reset
 101   when read; the least-significant 4 bits are full-scale counters;
 102   the actual peak value is in the most-significant 24 bits.
 103*/
 104
 105#define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 106#define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 107#define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 108#define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 109#define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 110
 111
 112/* This is for H9652 cards
 113   Peak values are read downward from the base
 114   Rms values are read upward
 115   There are rms values for the outputs too
 116   26*3 values are read in ss mode
 117   14*3 in ds mode, with no gap between values
 118*/
 119#define HDSP_9652_peakBase      7164
 120#define HDSP_9652_rmsBase       4096
 121
 122/* c.f. the hdsp_9632_meters_t struct */
 123#define HDSP_9632_metersBase    4096
 124
 125#define HDSP_IO_EXTENT     7168
 126
 127/* control2 register bits */
 128
 129#define HDSP_TMS                0x01
 130#define HDSP_TCK                0x02
 131#define HDSP_TDI                0x04
 132#define HDSP_JTAG               0x08
 133#define HDSP_PWDN               0x10
 134#define HDSP_PROGRAM            0x020
 135#define HDSP_CONFIG_MODE_0      0x040
 136#define HDSP_CONFIG_MODE_1      0x080
 137#define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 138#define HDSP_BIGENDIAN_MODE     0x200
 139#define HDSP_RD_MULTIPLE        0x400
 140#define HDSP_9652_ENABLE_MIXER  0x800
 141#define HDSP_S200               0x800
 142#define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 143#define HDSP_CYCLIC_MODE        0x1000
 144#define HDSP_TDO                0x10000000
 145
 146#define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 147#define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 148
 149/* Control Register bits */
 150
 151#define HDSP_Start                (1<<0)  /* start engine */
 152#define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 153#define HDSP_Latency1             (1<<2)  /* [ see above ] */
 154#define HDSP_Latency2             (1<<3)  /* [ see above ] */
 155#define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 156#define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 157#define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 158#define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 159#define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 160#define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 161#define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 162#define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 163#define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 164#define HDSP_SyncRef2             (1<<13)
 165#define HDSP_SPDIFInputSelect0    (1<<14)
 166#define HDSP_SPDIFInputSelect1    (1<<15)
 167#define HDSP_SyncRef0             (1<<16)
 168#define HDSP_SyncRef1             (1<<17)
 169#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 170#define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 171#define HDSP_Midi0InterruptEnable (1<<22)
 172#define HDSP_Midi1InterruptEnable (1<<23)
 173#define HDSP_LineOut              (1<<24)
 174#define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 175#define HDSP_ADGain1              (1<<26)
 176#define HDSP_DAGain0              (1<<27)
 177#define HDSP_DAGain1              (1<<28)
 178#define HDSP_PhoneGain0           (1<<29)
 179#define HDSP_PhoneGain1           (1<<30)
 180#define HDSP_QuadSpeed            (1<<31)
 181
 182/* RPM uses some of the registers for special purposes */
 183#define HDSP_RPM_Inp12            0x04A00
 184#define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 185#define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 186#define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 187#define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 188#define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 189
 190#define HDSP_RPM_Inp34            0x32000
 191#define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 192#define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 193#define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 194#define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 195#define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 196
 197#define HDSP_RPM_Bypass           0x01000
 198
 199#define HDSP_RPM_Disconnect       0x00001
 200
 201#define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 202#define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 203#define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 204#define HDSP_ADGainLowGain     0
 205
 206#define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 207#define HDSP_DAGainHighGain      HDSP_DAGainMask
 208#define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 209#define HDSP_DAGainMinus10dBV    0
 210
 211#define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 212#define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 213#define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 214#define HDSP_PhoneGainMinus12dB  0
 215
 216#define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 217#define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 218
 219#define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 220#define HDSP_SPDIFInputADAT1    0
 221#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 222#define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 223#define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 224
 225#define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 226#define HDSP_SyncRef_ADAT1       0
 227#define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 228#define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 229#define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 230#define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 231#define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 232
 233/* Sample Clock Sources */
 234
 235#define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 236#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 237#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 238#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 239#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 240#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 241#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 242#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 243#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 244#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 245
 246/* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 247
 248#define HDSP_SYNC_FROM_WORD      0
 249#define HDSP_SYNC_FROM_SPDIF     1
 250#define HDSP_SYNC_FROM_ADAT1     2
 251#define HDSP_SYNC_FROM_ADAT_SYNC 3
 252#define HDSP_SYNC_FROM_ADAT2     4
 253#define HDSP_SYNC_FROM_ADAT3     5
 254
 255/* SyncCheck status */
 256
 257#define HDSP_SYNC_CHECK_NO_LOCK 0
 258#define HDSP_SYNC_CHECK_LOCK    1
 259#define HDSP_SYNC_CHECK_SYNC    2
 260
 261/* AutoSync references - used by "autosync_ref" control switch */
 262
 263#define HDSP_AUTOSYNC_FROM_WORD      0
 264#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 265#define HDSP_AUTOSYNC_FROM_SPDIF     2
 266#define HDSP_AUTOSYNC_FROM_NONE      3
 267#define HDSP_AUTOSYNC_FROM_ADAT1     4
 268#define HDSP_AUTOSYNC_FROM_ADAT2     5
 269#define HDSP_AUTOSYNC_FROM_ADAT3     6
 270
 271/* Possible sources of S/PDIF input */
 272
 273#define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 274#define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 275#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 276#define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 277
 278#define HDSP_Frequency32KHz    HDSP_Frequency0
 279#define HDSP_Frequency44_1KHz  HDSP_Frequency1
 280#define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 281#define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 282#define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 283#define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 284/* For H9632 cards */
 285#define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 286#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 287#define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 288/* RME says n = 104857600000000, but in the windows MADI driver, I see:
 289        return 104857600000000 / rate; // 100 MHz
 290        return 110100480000000 / rate; // 105 MHz
 291*/
 292#define DDS_NUMERATOR 104857600000000ULL  /*  =  2^20 * 10^8 */
 293
 294#define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 295#define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 296
 297#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 298#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 299
 300/* Status Register bits */
 301
 302#define HDSP_audioIRQPending    (1<<0)
 303#define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 304#define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 305#define HDSP_Lock1              (1<<2)
 306#define HDSP_Lock0              (1<<3)
 307#define HDSP_SPDIFSync          (1<<4)
 308#define HDSP_TimecodeLock       (1<<5)
 309#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 310#define HDSP_Sync2              (1<<16)
 311#define HDSP_Sync1              (1<<17)
 312#define HDSP_Sync0              (1<<18)
 313#define HDSP_DoubleSpeedStatus  (1<<19)
 314#define HDSP_ConfigError        (1<<20)
 315#define HDSP_DllError           (1<<21)
 316#define HDSP_spdifFrequency0    (1<<22)
 317#define HDSP_spdifFrequency1    (1<<23)
 318#define HDSP_spdifFrequency2    (1<<24)
 319#define HDSP_SPDIFErrorFlag     (1<<25)
 320#define HDSP_BufferID           (1<<26)
 321#define HDSP_TimecodeSync       (1<<27)
 322#define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 323#define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 324#define HDSP_midi0IRQPending    (1<<30)
 325#define HDSP_midi1IRQPending    (1<<31)
 326
 327#define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 328#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 329                                      HDSP_spdifFrequency1|\
 330                                      HDSP_spdifFrequency2|\
 331                                      HDSP_spdifFrequency3)
 332
 333#define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 334#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 335#define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 336
 337#define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 338#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 339#define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 340
 341/* This is for H9632 cards */
 342#define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 343                                     HDSP_spdifFrequency1|\
 344                                     HDSP_spdifFrequency2)
 345#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 346#define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 347
 348/* Status2 Register bits */
 349
 350#define HDSP_version0     (1<<0)
 351#define HDSP_version1     (1<<1)
 352#define HDSP_version2     (1<<2)
 353#define HDSP_wc_lock      (1<<3)
 354#define HDSP_wc_sync      (1<<4)
 355#define HDSP_inp_freq0    (1<<5)
 356#define HDSP_inp_freq1    (1<<6)
 357#define HDSP_inp_freq2    (1<<7)
 358#define HDSP_SelSyncRef0  (1<<8)
 359#define HDSP_SelSyncRef1  (1<<9)
 360#define HDSP_SelSyncRef2  (1<<10)
 361
 362#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 363
 364#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 365#define HDSP_systemFrequency32   (HDSP_inp_freq0)
 366#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 367#define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 368#define HDSP_systemFrequency64   (HDSP_inp_freq2)
 369#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 370#define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 371/* FIXME : more values for 9632 cards ? */
 372
 373#define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 374#define HDSP_SelSyncRef_ADAT1      0
 375#define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 376#define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 377#define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 378#define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 379#define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 380
 381/* Card state flags */
 382
 383#define HDSP_InitializationComplete  (1<<0)
 384#define HDSP_FirmwareLoaded          (1<<1)
 385#define HDSP_FirmwareCached          (1<<2)
 386
 387/* FIFO wait times, defined in terms of 1/10ths of msecs */
 388
 389#define HDSP_LONG_WAIT   5000
 390#define HDSP_SHORT_WAIT  30
 391
 392#define UNITY_GAIN                       32768
 393#define MINUS_INFINITY_GAIN              0
 394
 395/* the size of a substream (1 mono data stream) */
 396
 397#define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 398#define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 399
 400/* the size of the area we need to allocate for DMA transfers. the
 401   size is the same regardless of the number of channels - the
 402   Multiface still uses the same memory area.
 403
 404   Note that we allocate 1 more channel than is apparently needed
 405   because the h/w seems to write 1 byte beyond the end of the last
 406   page. Sigh.
 407*/
 408
 409#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 410#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 411
 412#define HDSP_FIRMWARE_SIZE      (24413 * 4)
 413
 414struct hdsp_9632_meters {
 415    u32 input_peak[16];
 416    u32 playback_peak[16];
 417    u32 output_peak[16];
 418    u32 xxx_peak[16];
 419    u32 padding[64];
 420    u32 input_rms_low[16];
 421    u32 playback_rms_low[16];
 422    u32 output_rms_low[16];
 423    u32 xxx_rms_low[16];
 424    u32 input_rms_high[16];
 425    u32 playback_rms_high[16];
 426    u32 output_rms_high[16];
 427    u32 xxx_rms_high[16];
 428};
 429
 430struct hdsp_midi {
 431    struct hdsp             *hdsp;
 432    int                      id;
 433    struct snd_rawmidi           *rmidi;
 434    struct snd_rawmidi_substream *input;
 435    struct snd_rawmidi_substream *output;
 436    char                     istimer; /* timer in use */
 437    struct timer_list        timer;
 438    spinlock_t               lock;
 439    int                      pending;
 440};
 441
 442struct hdsp {
 443        spinlock_t            lock;
 444        struct snd_pcm_substream *capture_substream;
 445        struct snd_pcm_substream *playback_substream;
 446        struct hdsp_midi      midi[2];
 447        struct work_struct    midi_work;
 448        int                   use_midi_work;
 449        int                   precise_ptr;
 450        u32                   control_register;      /* cached value */
 451        u32                   control2_register;     /* cached value */
 452        u32                   creg_spdif;
 453        u32                   creg_spdif_stream;
 454        int                   clock_source_locked;
 455        char                 *card_name;         /* digiface/multiface/rpm */
 456        enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 457        unsigned short        firmware_rev;
 458        unsigned short        state;                 /* stores state bits */
 459        const struct firmware *firmware;
 460        u32                  *fw_uploaded;
 461        size_t                period_bytes;          /* guess what this is */
 462        unsigned char         max_channels;
 463        unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 464        unsigned char         ds_in_channels;
 465        unsigned char         ss_in_channels;       /* different for multiface/digiface */
 466        unsigned char         qs_out_channels;
 467        unsigned char         ds_out_channels;
 468        unsigned char         ss_out_channels;
 469        u32                   io_loopback;          /* output loopback channel states*/
 470
 471        struct snd_dma_buffer *capture_dma_buf;
 472        struct snd_dma_buffer *playback_dma_buf;
 473        unsigned char        *capture_buffer;       /* suitably aligned address */
 474        unsigned char        *playback_buffer;      /* suitably aligned address */
 475
 476        pid_t                 capture_pid;
 477        pid_t                 playback_pid;
 478        int                   running;
 479        int                   system_sample_rate;
 480        const char           *channel_map;
 481        int                   dev;
 482        int                   irq;
 483        unsigned long         port;
 484        void __iomem         *iobase;
 485        struct snd_card *card;
 486        struct snd_pcm *pcm;
 487        struct snd_hwdep          *hwdep;
 488        struct pci_dev       *pci;
 489        struct snd_kcontrol *spdif_ctl;
 490        unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 491        unsigned int          dds_value; /* last value written to freq register */
 492};
 493
 494/* These tables map the ALSA channels 1..N to the channels that we
 495   need to use in order to find the relevant channel buffer. RME
 496   refer to this kind of mapping as between "the ADAT channel and
 497   the DMA channel." We index it using the logical audio channel,
 498   and the value is the DMA channel (i.e. channel buffer number)
 499   where the data for that channel can be read/written from/to.
 500*/
 501
 502static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 503        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 504        18, 19, 20, 21, 22, 23, 24, 25
 505};
 506
 507static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 508        /* Analog */
 509        0, 1, 2, 3, 4, 5, 6, 7,
 510        /* ADAT 2 */
 511        16, 17, 18, 19, 20, 21, 22, 23,
 512        /* SPDIF */
 513        24, 25,
 514        -1, -1, -1, -1, -1, -1, -1, -1
 515};
 516
 517static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
 518        /* ADAT channels are remapped */
 519        1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 520        /* channels 12 and 13 are S/PDIF */
 521        24, 25,
 522        /* others don't exist */
 523        -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 524};
 525
 526static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 527        /* ADAT channels */
 528        0, 1, 2, 3, 4, 5, 6, 7,
 529        /* SPDIF */
 530        8, 9,
 531        /* Analog */
 532        10, 11,
 533        /* AO4S-192 and AI4S-192 extension boards */
 534        12, 13, 14, 15,
 535        /* others don't exist */
 536        -1, -1, -1, -1, -1, -1, -1, -1,
 537        -1, -1
 538};
 539
 540static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 541        /* ADAT */
 542        1, 3, 5, 7,
 543        /* SPDIF */
 544        8, 9,
 545        /* Analog */
 546        10, 11,
 547        /* AO4S-192 and AI4S-192 extension boards */
 548        12, 13, 14, 15,
 549        /* others don't exist */
 550        -1, -1, -1, -1, -1, -1, -1, -1,
 551        -1, -1, -1, -1, -1, -1
 552};
 553
 554static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 555        /* ADAT is disabled in this mode */
 556        /* SPDIF */
 557        8, 9,
 558        /* Analog */
 559        10, 11,
 560        /* AO4S-192 and AI4S-192 extension boards */
 561        12, 13, 14, 15,
 562        /* others don't exist */
 563        -1, -1, -1, -1, -1, -1, -1, -1,
 564        -1, -1, -1, -1, -1, -1, -1, -1,
 565        -1, -1
 566};
 567
 568static struct snd_dma_buffer *
 569snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
 570{
 571        return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
 572}
 573
 574static const struct pci_device_id snd_hdsp_ids[] = {
 575        {
 576                .vendor = PCI_VENDOR_ID_XILINX,
 577                .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 578                .subvendor = PCI_ANY_ID,
 579                .subdevice = PCI_ANY_ID,
 580        }, /* RME Hammerfall-DSP */
 581        { 0, },
 582};
 583
 584MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 585
 586/* prototypes */
 587static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 588static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 589static int snd_hdsp_enable_io (struct hdsp *hdsp);
 590static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 591static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 592static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 593static int hdsp_autosync_ref(struct hdsp *hdsp);
 594static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 595static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 596
 597static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 598{
 599        switch (hdsp->io_type) {
 600        case Multiface:
 601        case Digiface:
 602        case RPM:
 603        default:
 604                if (hdsp->firmware_rev == 0xa)
 605                        return (64 * out) + (32 + (in));
 606                else
 607                        return (52 * out) + (26 + (in));
 608        case H9632:
 609                return (32 * out) + (16 + (in));
 610        case H9652:
 611                return (52 * out) + (26 + (in));
 612        }
 613}
 614
 615static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 616{
 617        switch (hdsp->io_type) {
 618        case Multiface:
 619        case Digiface:
 620        case RPM:
 621        default:
 622                if (hdsp->firmware_rev == 0xa)
 623                        return (64 * out) + in;
 624                else
 625                        return (52 * out) + in;
 626        case H9632:
 627                return (32 * out) + in;
 628        case H9652:
 629                return (52 * out) + in;
 630        }
 631}
 632
 633static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 634{
 635        writel(val, hdsp->iobase + reg);
 636}
 637
 638static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 639{
 640        return readl (hdsp->iobase + reg);
 641}
 642
 643static int hdsp_check_for_iobox (struct hdsp *hdsp)
 644{
 645        int i;
 646
 647        if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 648        for (i = 0; i < 500; i++) {
 649                if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 650                                        HDSP_ConfigError)) {
 651                        if (i) {
 652                                dev_dbg(hdsp->card->dev,
 653                                        "IO box found after %d ms\n",
 654                                                (20 * i));
 655                        }
 656                        return 0;
 657                }
 658                msleep(20);
 659        }
 660        dev_err(hdsp->card->dev, "no IO box connected!\n");
 661        hdsp->state &= ~HDSP_FirmwareLoaded;
 662        return -EIO;
 663}
 664
 665static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 666                               unsigned int delay)
 667{
 668        unsigned int i;
 669
 670        if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 671                return 0;
 672
 673        for (i = 0; i != loops; ++i) {
 674                if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 675                        msleep(delay);
 676                else {
 677                        dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 678                                   i * delay);
 679                        return 0;
 680                }
 681        }
 682
 683        dev_info(hdsp->card->dev, "no IO box connected!\n");
 684        hdsp->state &= ~HDSP_FirmwareLoaded;
 685        return -EIO;
 686}
 687
 688static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 689
 690        int i;
 691        unsigned long flags;
 692        const u32 *cache;
 693
 694        if (hdsp->fw_uploaded)
 695                cache = hdsp->fw_uploaded;
 696        else {
 697                if (!hdsp->firmware)
 698                        return -ENODEV;
 699                cache = (u32 *)hdsp->firmware->data;
 700                if (!cache)
 701                        return -ENODEV;
 702        }
 703
 704        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 705
 706                dev_info(hdsp->card->dev, "loading firmware\n");
 707
 708                hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 709                hdsp_write (hdsp, HDSP_fifoData, 0);
 710
 711                if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 712                        dev_info(hdsp->card->dev,
 713                                 "timeout waiting for download preparation\n");
 714                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 715                        return -EIO;
 716                }
 717
 718                hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 719
 720                for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 721                        hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 722                        if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 723                                dev_info(hdsp->card->dev,
 724                                         "timeout during firmware loading\n");
 725                                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 726                                return -EIO;
 727                        }
 728                }
 729
 730                hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 731                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 732
 733                ssleep(3);
 734#ifdef SNDRV_BIG_ENDIAN
 735                hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 736#else
 737                hdsp->control2_register = 0;
 738#endif
 739                hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 740                dev_info(hdsp->card->dev, "finished firmware loading\n");
 741
 742        }
 743        if (hdsp->state & HDSP_InitializationComplete) {
 744                dev_info(hdsp->card->dev,
 745                         "firmware loaded from cache, restoring defaults\n");
 746                spin_lock_irqsave(&hdsp->lock, flags);
 747                snd_hdsp_set_defaults(hdsp);
 748                spin_unlock_irqrestore(&hdsp->lock, flags);
 749        }
 750
 751        hdsp->state |= HDSP_FirmwareLoaded;
 752
 753        return 0;
 754}
 755
 756static int hdsp_get_iobox_version (struct hdsp *hdsp)
 757{
 758        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 759
 760                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 761                hdsp_write(hdsp, HDSP_fifoData, 0);
 762
 763                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 764                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 765                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 766                }
 767
 768                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 769                hdsp_write (hdsp, HDSP_fifoData, 0);
 770                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 771                        goto set_multi;
 772
 773                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 774                hdsp_write(hdsp, HDSP_fifoData, 0);
 775                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 776                        hdsp->io_type = Digiface;
 777                        dev_info(hdsp->card->dev, "Digiface found\n");
 778                        return 0;
 779                }
 780
 781                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 782                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 783                hdsp_write(hdsp, HDSP_fifoData, 0);
 784                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 785                        goto set_multi;
 786
 787                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 788                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 789                hdsp_write(hdsp, HDSP_fifoData, 0);
 790                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 791                        goto set_multi;
 792
 793                hdsp->io_type = RPM;
 794                dev_info(hdsp->card->dev, "RPM found\n");
 795                return 0;
 796        } else {
 797                /* firmware was already loaded, get iobox type */
 798                if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 799                        hdsp->io_type = RPM;
 800                else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 801                        hdsp->io_type = Multiface;
 802                else
 803                        hdsp->io_type = Digiface;
 804        }
 805        return 0;
 806
 807set_multi:
 808        hdsp->io_type = Multiface;
 809        dev_info(hdsp->card->dev, "Multiface found\n");
 810        return 0;
 811}
 812
 813
 814static int hdsp_request_fw_loader(struct hdsp *hdsp);
 815
 816static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 817{
 818        if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 819                return 0;
 820        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 821                hdsp->state &= ~HDSP_FirmwareLoaded;
 822                if (! load_on_demand)
 823                        return -EIO;
 824                dev_err(hdsp->card->dev, "firmware not present.\n");
 825                /* try to load firmware */
 826                if (! (hdsp->state & HDSP_FirmwareCached)) {
 827                        if (! hdsp_request_fw_loader(hdsp))
 828                                return 0;
 829                        dev_err(hdsp->card->dev,
 830                                   "No firmware loaded nor cached, please upload firmware.\n");
 831                        return -EIO;
 832                }
 833                if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 834                        dev_err(hdsp->card->dev,
 835                                   "Firmware loading from cache failed, please upload manually.\n");
 836                        return -EIO;
 837                }
 838        }
 839        return 0;
 840}
 841
 842
 843static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 844{
 845        int i;
 846
 847        /* the fifoStatus registers reports on how many words
 848           are available in the command FIFO.
 849        */
 850
 851        for (i = 0; i < timeout; i++) {
 852
 853                if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 854                        return 0;
 855
 856                /* not very friendly, but we only do this during a firmware
 857                   load and changing the mixer, so we just put up with it.
 858                */
 859
 860                udelay (100);
 861        }
 862
 863        dev_warn(hdsp->card->dev,
 864                 "wait for FIFO status <= %d failed after %d iterations\n",
 865                    count, timeout);
 866        return -1;
 867}
 868
 869static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 870{
 871        if (addr >= HDSP_MATRIX_MIXER_SIZE)
 872                return 0;
 873
 874        return hdsp->mixer_matrix[addr];
 875}
 876
 877static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 878{
 879        unsigned int ad;
 880
 881        if (addr >= HDSP_MATRIX_MIXER_SIZE)
 882                return -1;
 883
 884        if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 885
 886                /* from martin bjornsen:
 887
 888                   "You can only write dwords to the
 889                   mixer memory which contain two
 890                   mixer values in the low and high
 891                   word. So if you want to change
 892                   value 0 you have to read value 1
 893                   from the cache and write both to
 894                   the first dword in the mixer
 895                   memory."
 896                */
 897
 898                if (hdsp->io_type == H9632 && addr >= 512)
 899                        return 0;
 900
 901                if (hdsp->io_type == H9652 && addr >= 1352)
 902                        return 0;
 903
 904                hdsp->mixer_matrix[addr] = data;
 905
 906
 907                /* `addr' addresses a 16-bit wide address, but
 908                   the address space accessed via hdsp_write
 909                   uses byte offsets. put another way, addr
 910                   varies from 0 to 1351, but to access the
 911                   corresponding memory location, we need
 912                   to access 0 to 2703 ...
 913                */
 914                ad = addr/2;
 915
 916                hdsp_write (hdsp, 4096 + (ad*4),
 917                            (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 918                            hdsp->mixer_matrix[addr&0x7fe]);
 919
 920                return 0;
 921
 922        } else {
 923
 924                ad = (addr << 16) + data;
 925
 926                if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 927                        return -1;
 928
 929                hdsp_write (hdsp, HDSP_fifoData, ad);
 930                hdsp->mixer_matrix[addr] = data;
 931
 932        }
 933
 934        return 0;
 935}
 936
 937static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 938{
 939        unsigned long flags;
 940        int ret = 1;
 941
 942        spin_lock_irqsave(&hdsp->lock, flags);
 943        if ((hdsp->playback_pid != hdsp->capture_pid) &&
 944            (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 945                ret = 0;
 946        spin_unlock_irqrestore(&hdsp->lock, flags);
 947        return ret;
 948}
 949
 950static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 951{
 952        unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 953        unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 954
 955        /* For the 9632, the mask is different */
 956        if (hdsp->io_type == H9632)
 957                 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 958
 959        if (status & HDSP_SPDIFErrorFlag)
 960                return 0;
 961
 962        switch (rate_bits) {
 963        case HDSP_spdifFrequency32KHz: return 32000;
 964        case HDSP_spdifFrequency44_1KHz: return 44100;
 965        case HDSP_spdifFrequency48KHz: return 48000;
 966        case HDSP_spdifFrequency64KHz: return 64000;
 967        case HDSP_spdifFrequency88_2KHz: return 88200;
 968        case HDSP_spdifFrequency96KHz: return 96000;
 969        case HDSP_spdifFrequency128KHz:
 970                if (hdsp->io_type == H9632) return 128000;
 971                break;
 972        case HDSP_spdifFrequency176_4KHz:
 973                if (hdsp->io_type == H9632) return 176400;
 974                break;
 975        case HDSP_spdifFrequency192KHz:
 976                if (hdsp->io_type == H9632) return 192000;
 977                break;
 978        default:
 979                break;
 980        }
 981        dev_warn(hdsp->card->dev,
 982                 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
 983                 rate_bits, status);
 984        return 0;
 985}
 986
 987static int hdsp_external_sample_rate(struct hdsp *hdsp)
 988{
 989        unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 990        unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 991
 992        /* For the 9632 card, there seems to be no bit for indicating external
 993         * sample rate greater than 96kHz. The card reports the corresponding
 994         * single speed. So the best means seems to get spdif rate when
 995         * autosync reference is spdif */
 996        if (hdsp->io_type == H9632 &&
 997            hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
 998                 return hdsp_spdif_sample_rate(hdsp);
 999
1000        switch (rate_bits) {
1001        case HDSP_systemFrequency32:   return 32000;
1002        case HDSP_systemFrequency44_1: return 44100;
1003        case HDSP_systemFrequency48:   return 48000;
1004        case HDSP_systemFrequency64:   return 64000;
1005        case HDSP_systemFrequency88_2: return 88200;
1006        case HDSP_systemFrequency96:   return 96000;
1007        default:
1008                return 0;
1009        }
1010}
1011
1012static void hdsp_compute_period_size(struct hdsp *hdsp)
1013{
1014        hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1015}
1016
1017static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1018{
1019        int position;
1020
1021        position = hdsp_read(hdsp, HDSP_statusRegister);
1022
1023        if (!hdsp->precise_ptr)
1024                return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1025
1026        position &= HDSP_BufferPositionMask;
1027        position /= 4;
1028        position &= (hdsp->period_bytes/2) - 1;
1029        return position;
1030}
1031
1032static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1033{
1034        hdsp_write (hdsp, HDSP_resetPointer, 0);
1035        if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1036                /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1037                 * requires (?) to write again DDS value after a reset pointer
1038                 * (at least, it works like this) */
1039                hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1040}
1041
1042static void hdsp_start_audio(struct hdsp *s)
1043{
1044        s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1045        hdsp_write(s, HDSP_controlRegister, s->control_register);
1046}
1047
1048static void hdsp_stop_audio(struct hdsp *s)
1049{
1050        s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1051        hdsp_write(s, HDSP_controlRegister, s->control_register);
1052}
1053
1054static void hdsp_silence_playback(struct hdsp *hdsp)
1055{
1056        memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1057}
1058
1059static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1060{
1061        int n;
1062
1063        spin_lock_irq(&s->lock);
1064
1065        frames >>= 7;
1066        n = 0;
1067        while (frames) {
1068                n++;
1069                frames >>= 1;
1070        }
1071
1072        s->control_register &= ~HDSP_LatencyMask;
1073        s->control_register |= hdsp_encode_latency(n);
1074
1075        hdsp_write(s, HDSP_controlRegister, s->control_register);
1076
1077        hdsp_compute_period_size(s);
1078
1079        spin_unlock_irq(&s->lock);
1080
1081        return 0;
1082}
1083
1084static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1085{
1086        u64 n;
1087
1088        if (rate >= 112000)
1089                rate /= 4;
1090        else if (rate >= 56000)
1091                rate /= 2;
1092
1093        n = DDS_NUMERATOR;
1094        n = div_u64(n, rate);
1095        /* n should be less than 2^32 for being written to FREQ register */
1096        snd_BUG_ON(n >> 32);
1097        /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1098           value to write it after a reset */
1099        hdsp->dds_value = n;
1100        hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1101}
1102
1103static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1104{
1105        int reject_if_open = 0;
1106        int current_rate;
1107        int rate_bits;
1108
1109        /* ASSUMPTION: hdsp->lock is either held, or
1110           there is no need for it (e.g. during module
1111           initialization).
1112        */
1113
1114        if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1115                if (called_internally) {
1116                        /* request from ctl or card initialization */
1117                        dev_err(hdsp->card->dev,
1118                                "device is not running as a clock master: cannot set sample rate.\n");
1119                        return -1;
1120                } else {
1121                        /* hw_param request while in AutoSync mode */
1122                        int external_freq = hdsp_external_sample_rate(hdsp);
1123                        int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1124
1125                        if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1126                                dev_info(hdsp->card->dev,
1127                                         "Detected ADAT in double speed mode\n");
1128                        else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1129                                dev_info(hdsp->card->dev,
1130                                         "Detected ADAT in quad speed mode\n");
1131                        else if (rate != external_freq) {
1132                                dev_info(hdsp->card->dev,
1133                                         "No AutoSync source for requested rate\n");
1134                                return -1;
1135                        }
1136                }
1137        }
1138
1139        current_rate = hdsp->system_sample_rate;
1140
1141        /* Changing from a "single speed" to a "double speed" rate is
1142           not allowed if any substreams are open. This is because
1143           such a change causes a shift in the location of
1144           the DMA buffers and a reduction in the number of available
1145           buffers.
1146
1147           Note that a similar but essentially insoluble problem
1148           exists for externally-driven rate changes. All we can do
1149           is to flag rate changes in the read/write routines.  */
1150
1151        if (rate > 96000 && hdsp->io_type != H9632)
1152                return -EINVAL;
1153
1154        switch (rate) {
1155        case 32000:
1156                if (current_rate > 48000)
1157                        reject_if_open = 1;
1158                rate_bits = HDSP_Frequency32KHz;
1159                break;
1160        case 44100:
1161                if (current_rate > 48000)
1162                        reject_if_open = 1;
1163                rate_bits = HDSP_Frequency44_1KHz;
1164                break;
1165        case 48000:
1166                if (current_rate > 48000)
1167                        reject_if_open = 1;
1168                rate_bits = HDSP_Frequency48KHz;
1169                break;
1170        case 64000:
1171                if (current_rate <= 48000 || current_rate > 96000)
1172                        reject_if_open = 1;
1173                rate_bits = HDSP_Frequency64KHz;
1174                break;
1175        case 88200:
1176                if (current_rate <= 48000 || current_rate > 96000)
1177                        reject_if_open = 1;
1178                rate_bits = HDSP_Frequency88_2KHz;
1179                break;
1180        case 96000:
1181                if (current_rate <= 48000 || current_rate > 96000)
1182                        reject_if_open = 1;
1183                rate_bits = HDSP_Frequency96KHz;
1184                break;
1185        case 128000:
1186                if (current_rate < 128000)
1187                        reject_if_open = 1;
1188                rate_bits = HDSP_Frequency128KHz;
1189                break;
1190        case 176400:
1191                if (current_rate < 128000)
1192                        reject_if_open = 1;
1193                rate_bits = HDSP_Frequency176_4KHz;
1194                break;
1195        case 192000:
1196                if (current_rate < 128000)
1197                        reject_if_open = 1;
1198                rate_bits = HDSP_Frequency192KHz;
1199                break;
1200        default:
1201                return -EINVAL;
1202        }
1203
1204        if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1205                dev_warn(hdsp->card->dev,
1206                         "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1207                            hdsp->capture_pid,
1208                            hdsp->playback_pid);
1209                return -EBUSY;
1210        }
1211
1212        hdsp->control_register &= ~HDSP_FrequencyMask;
1213        hdsp->control_register |= rate_bits;
1214        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1215
1216        /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1217        if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1218                hdsp_set_dds_value(hdsp, rate);
1219
1220        if (rate >= 128000) {
1221                hdsp->channel_map = channel_map_H9632_qs;
1222        } else if (rate > 48000) {
1223                if (hdsp->io_type == H9632)
1224                        hdsp->channel_map = channel_map_H9632_ds;
1225                else
1226                        hdsp->channel_map = channel_map_ds;
1227        } else {
1228                switch (hdsp->io_type) {
1229                case RPM:
1230                case Multiface:
1231                        hdsp->channel_map = channel_map_mf_ss;
1232                        break;
1233                case Digiface:
1234                case H9652:
1235                        hdsp->channel_map = channel_map_df_ss;
1236                        break;
1237                case H9632:
1238                        hdsp->channel_map = channel_map_H9632_ss;
1239                        break;
1240                default:
1241                        /* should never happen */
1242                        break;
1243                }
1244        }
1245
1246        hdsp->system_sample_rate = rate;
1247
1248        return 0;
1249}
1250
1251/*----------------------------------------------------------------------------
1252   MIDI
1253  ----------------------------------------------------------------------------*/
1254
1255static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1256{
1257        /* the hardware already does the relevant bit-mask with 0xff */
1258        if (id)
1259                return hdsp_read(hdsp, HDSP_midiDataIn1);
1260        else
1261                return hdsp_read(hdsp, HDSP_midiDataIn0);
1262}
1263
1264static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1265{
1266        /* the hardware already does the relevant bit-mask with 0xff */
1267        if (id)
1268                hdsp_write(hdsp, HDSP_midiDataOut1, val);
1269        else
1270                hdsp_write(hdsp, HDSP_midiDataOut0, val);
1271}
1272
1273static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1274{
1275        if (id)
1276                return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1277        else
1278                return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1279}
1280
1281static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1282{
1283        int fifo_bytes_used;
1284
1285        if (id)
1286                fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1287        else
1288                fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1289
1290        if (fifo_bytes_used < 128)
1291                return  128 - fifo_bytes_used;
1292        else
1293                return 0;
1294}
1295
1296static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1297{
1298        while (snd_hdsp_midi_input_available (hdsp, id))
1299                snd_hdsp_midi_read_byte (hdsp, id);
1300}
1301
1302static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1303{
1304        unsigned long flags;
1305        int n_pending;
1306        int to_write;
1307        int i;
1308        unsigned char buf[128];
1309
1310        /* Output is not interrupt driven */
1311
1312        spin_lock_irqsave (&hmidi->lock, flags);
1313        if (hmidi->output) {
1314                if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1315                        n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
1316                        if (n_pending > 0) {
1317                                if (n_pending > (int)sizeof (buf))
1318                                        n_pending = sizeof (buf);
1319
1320                                to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
1321                                if (to_write > 0) {
1322                                        for (i = 0; i < to_write; ++i)
1323                                                snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1324                                }
1325                        }
1326                }
1327        }
1328        spin_unlock_irqrestore (&hmidi->lock, flags);
1329        return 0;
1330}
1331
1332static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1333{
1334        unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1335        unsigned long flags;
1336        int n_pending;
1337        int i;
1338
1339        spin_lock_irqsave (&hmidi->lock, flags);
1340        n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
1341        if (n_pending > 0) {
1342                if (hmidi->input) {
1343                        if (n_pending > (int)sizeof (buf))
1344                                n_pending = sizeof (buf);
1345                        for (i = 0; i < n_pending; ++i)
1346                                buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1347                        if (n_pending)
1348                                snd_rawmidi_receive (hmidi->input, buf, n_pending);
1349                } else {
1350                        /* flush the MIDI input FIFO */
1351                        while (--n_pending)
1352                                snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1353                }
1354        }
1355        hmidi->pending = 0;
1356        if (hmidi->id)
1357                hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1358        else
1359                hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1360        hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1361        spin_unlock_irqrestore (&hmidi->lock, flags);
1362        return snd_hdsp_midi_output_write (hmidi);
1363}
1364
1365static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1366{
1367        struct hdsp *hdsp;
1368        struct hdsp_midi *hmidi;
1369        unsigned long flags;
1370        u32 ie;
1371
1372        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1373        hdsp = hmidi->hdsp;
1374        ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1375        spin_lock_irqsave (&hdsp->lock, flags);
1376        if (up) {
1377                if (!(hdsp->control_register & ie)) {
1378                        snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1379                        hdsp->control_register |= ie;
1380                }
1381        } else {
1382                hdsp->control_register &= ~ie;
1383        }
1384
1385        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1386        spin_unlock_irqrestore (&hdsp->lock, flags);
1387}
1388
1389static void snd_hdsp_midi_output_timer(struct timer_list *t)
1390{
1391        struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1392        unsigned long flags;
1393
1394        snd_hdsp_midi_output_write(hmidi);
1395        spin_lock_irqsave (&hmidi->lock, flags);
1396
1397        /* this does not bump hmidi->istimer, because the
1398           kernel automatically removed the timer when it
1399           expired, and we are now adding it back, thus
1400           leaving istimer wherever it was set before.
1401        */
1402
1403        if (hmidi->istimer)
1404                mod_timer(&hmidi->timer, 1 + jiffies);
1405
1406        spin_unlock_irqrestore (&hmidi->lock, flags);
1407}
1408
1409static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1410{
1411        struct hdsp_midi *hmidi;
1412        unsigned long flags;
1413
1414        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1415        spin_lock_irqsave (&hmidi->lock, flags);
1416        if (up) {
1417                if (!hmidi->istimer) {
1418                        timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1419                                    0);
1420                        mod_timer(&hmidi->timer, 1 + jiffies);
1421                        hmidi->istimer++;
1422                }
1423        } else {
1424                if (hmidi->istimer && --hmidi->istimer <= 0)
1425                        del_timer (&hmidi->timer);
1426        }
1427        spin_unlock_irqrestore (&hmidi->lock, flags);
1428        if (up)
1429                snd_hdsp_midi_output_write(hmidi);
1430}
1431
1432static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1433{
1434        struct hdsp_midi *hmidi;
1435
1436        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1437        spin_lock_irq (&hmidi->lock);
1438        snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1439        hmidi->input = substream;
1440        spin_unlock_irq (&hmidi->lock);
1441
1442        return 0;
1443}
1444
1445static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1446{
1447        struct hdsp_midi *hmidi;
1448
1449        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1450        spin_lock_irq (&hmidi->lock);
1451        hmidi->output = substream;
1452        spin_unlock_irq (&hmidi->lock);
1453
1454        return 0;
1455}
1456
1457static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1458{
1459        struct hdsp_midi *hmidi;
1460
1461        snd_hdsp_midi_input_trigger (substream, 0);
1462
1463        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1464        spin_lock_irq (&hmidi->lock);
1465        hmidi->input = NULL;
1466        spin_unlock_irq (&hmidi->lock);
1467
1468        return 0;
1469}
1470
1471static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1472{
1473        struct hdsp_midi *hmidi;
1474
1475        snd_hdsp_midi_output_trigger (substream, 0);
1476
1477        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1478        spin_lock_irq (&hmidi->lock);
1479        hmidi->output = NULL;
1480        spin_unlock_irq (&hmidi->lock);
1481
1482        return 0;
1483}
1484
1485static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1486{
1487        .open =         snd_hdsp_midi_output_open,
1488        .close =        snd_hdsp_midi_output_close,
1489        .trigger =      snd_hdsp_midi_output_trigger,
1490};
1491
1492static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1493{
1494        .open =         snd_hdsp_midi_input_open,
1495        .close =        snd_hdsp_midi_input_close,
1496        .trigger =      snd_hdsp_midi_input_trigger,
1497};
1498
1499static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1500{
1501        char buf[40];
1502
1503        hdsp->midi[id].id = id;
1504        hdsp->midi[id].rmidi = NULL;
1505        hdsp->midi[id].input = NULL;
1506        hdsp->midi[id].output = NULL;
1507        hdsp->midi[id].hdsp = hdsp;
1508        hdsp->midi[id].istimer = 0;
1509        hdsp->midi[id].pending = 0;
1510        spin_lock_init (&hdsp->midi[id].lock);
1511
1512        snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1513        if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1514                return -1;
1515
1516        sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1517        hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1518
1519        snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1520        snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1521
1522        hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1523                SNDRV_RAWMIDI_INFO_INPUT |
1524                SNDRV_RAWMIDI_INFO_DUPLEX;
1525
1526        return 0;
1527}
1528
1529/*-----------------------------------------------------------------------------
1530  Control Interface
1531  ----------------------------------------------------------------------------*/
1532
1533static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1534{
1535        u32 val = 0;
1536        val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1537        val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1538        if (val & HDSP_SPDIFProfessional)
1539                val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1540        else
1541                val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1542        return val;
1543}
1544
1545static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1546{
1547        aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1548                         ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1549        if (val & HDSP_SPDIFProfessional)
1550                aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1551        else
1552                aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1553}
1554
1555static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1556{
1557        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1558        uinfo->count = 1;
1559        return 0;
1560}
1561
1562static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1563{
1564        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1565
1566        snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1567        return 0;
1568}
1569
1570static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1571{
1572        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1573        int change;
1574        u32 val;
1575
1576        val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1577        spin_lock_irq(&hdsp->lock);
1578        change = val != hdsp->creg_spdif;
1579        hdsp->creg_spdif = val;
1580        spin_unlock_irq(&hdsp->lock);
1581        return change;
1582}
1583
1584static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1585{
1586        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1587        uinfo->count = 1;
1588        return 0;
1589}
1590
1591static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1592{
1593        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1594
1595        snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1596        return 0;
1597}
1598
1599static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1600{
1601        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1602        int change;
1603        u32 val;
1604
1605        val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1606        spin_lock_irq(&hdsp->lock);
1607        change = val != hdsp->creg_spdif_stream;
1608        hdsp->creg_spdif_stream = val;
1609        hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1610        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1611        spin_unlock_irq(&hdsp->lock);
1612        return change;
1613}
1614
1615static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1616{
1617        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1618        uinfo->count = 1;
1619        return 0;
1620}
1621
1622static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1623{
1624        ucontrol->value.iec958.status[0] = kcontrol->private_value;
1625        return 0;
1626}
1627
1628#define HDSP_SPDIF_IN(xname, xindex) \
1629{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1630  .name = xname, \
1631  .index = xindex, \
1632  .info = snd_hdsp_info_spdif_in, \
1633  .get = snd_hdsp_get_spdif_in, \
1634  .put = snd_hdsp_put_spdif_in }
1635
1636static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1637{
1638        return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1639}
1640
1641static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1642{
1643        hdsp->control_register &= ~HDSP_SPDIFInputMask;
1644        hdsp->control_register |= hdsp_encode_spdif_in(in);
1645        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1646        return 0;
1647}
1648
1649static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1650{
1651        static const char * const texts[4] = {
1652                "Optical", "Coaxial", "Internal", "AES"
1653        };
1654        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1655
1656        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1657                                 texts);
1658}
1659
1660static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1661{
1662        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1663
1664        ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1665        return 0;
1666}
1667
1668static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1669{
1670        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1671        int change;
1672        unsigned int val;
1673
1674        if (!snd_hdsp_use_is_exclusive(hdsp))
1675                return -EBUSY;
1676        val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1677        spin_lock_irq(&hdsp->lock);
1678        change = val != hdsp_spdif_in(hdsp);
1679        if (change)
1680                hdsp_set_spdif_input(hdsp, val);
1681        spin_unlock_irq(&hdsp->lock);
1682        return change;
1683}
1684
1685#define HDSP_TOGGLE_SETTING(xname, xindex) \
1686{   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1687        .name = xname, \
1688        .private_value = xindex, \
1689        .info = snd_hdsp_info_toggle_setting, \
1690        .get = snd_hdsp_get_toggle_setting, \
1691        .put = snd_hdsp_put_toggle_setting \
1692}
1693
1694static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1695{
1696        return (hdsp->control_register & regmask) ? 1 : 0;
1697}
1698
1699static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1700{
1701        if (out)
1702                hdsp->control_register |= regmask;
1703        else
1704                hdsp->control_register &= ~regmask;
1705        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1706
1707        return 0;
1708}
1709
1710#define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1711
1712static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1713                struct snd_ctl_elem_value *ucontrol)
1714{
1715        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1716        u32 regmask = kcontrol->private_value;
1717
1718        spin_lock_irq(&hdsp->lock);
1719        ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1720        spin_unlock_irq(&hdsp->lock);
1721        return 0;
1722}
1723
1724static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1725                struct snd_ctl_elem_value *ucontrol)
1726{
1727        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1728        u32 regmask = kcontrol->private_value;
1729        int change;
1730        unsigned int val;
1731
1732        if (!snd_hdsp_use_is_exclusive(hdsp))
1733                return -EBUSY;
1734        val = ucontrol->value.integer.value[0] & 1;
1735        spin_lock_irq(&hdsp->lock);
1736        change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1737        if (change)
1738                hdsp_set_toggle_setting(hdsp, regmask, val);
1739        spin_unlock_irq(&hdsp->lock);
1740        return change;
1741}
1742
1743#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1744{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1745  .name = xname, \
1746  .index = xindex, \
1747  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1748  .info = snd_hdsp_info_spdif_sample_rate, \
1749  .get = snd_hdsp_get_spdif_sample_rate \
1750}
1751
1752static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1753{
1754        static const char * const texts[] = {
1755                "32000", "44100", "48000", "64000", "88200", "96000",
1756                "None", "128000", "176400", "192000"
1757        };
1758        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1759
1760        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1761                                 texts);
1762}
1763
1764static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1765{
1766        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1767
1768        switch (hdsp_spdif_sample_rate(hdsp)) {
1769        case 32000:
1770                ucontrol->value.enumerated.item[0] = 0;
1771                break;
1772        case 44100:
1773                ucontrol->value.enumerated.item[0] = 1;
1774                break;
1775        case 48000:
1776                ucontrol->value.enumerated.item[0] = 2;
1777                break;
1778        case 64000:
1779                ucontrol->value.enumerated.item[0] = 3;
1780                break;
1781        case 88200:
1782                ucontrol->value.enumerated.item[0] = 4;
1783                break;
1784        case 96000:
1785                ucontrol->value.enumerated.item[0] = 5;
1786                break;
1787        case 128000:
1788                ucontrol->value.enumerated.item[0] = 7;
1789                break;
1790        case 176400:
1791                ucontrol->value.enumerated.item[0] = 8;
1792                break;
1793        case 192000:
1794                ucontrol->value.enumerated.item[0] = 9;
1795                break;
1796        default:
1797                ucontrol->value.enumerated.item[0] = 6;
1798        }
1799        return 0;
1800}
1801
1802#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1803{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1804  .name = xname, \
1805  .index = xindex, \
1806  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1807  .info = snd_hdsp_info_system_sample_rate, \
1808  .get = snd_hdsp_get_system_sample_rate \
1809}
1810
1811static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1812{
1813        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1814        uinfo->count = 1;
1815        return 0;
1816}
1817
1818static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1819{
1820        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1821
1822        ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1823        return 0;
1824}
1825
1826#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1827{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1828  .name = xname, \
1829  .index = xindex, \
1830  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1831  .info = snd_hdsp_info_autosync_sample_rate, \
1832  .get = snd_hdsp_get_autosync_sample_rate \
1833}
1834
1835static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1836{
1837        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1838        static const char * const texts[] = {
1839                "32000", "44100", "48000", "64000", "88200", "96000",
1840                "None", "128000", "176400", "192000"
1841        };
1842
1843        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1844                                 texts);
1845}
1846
1847static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1848{
1849        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1850
1851        switch (hdsp_external_sample_rate(hdsp)) {
1852        case 32000:
1853                ucontrol->value.enumerated.item[0] = 0;
1854                break;
1855        case 44100:
1856                ucontrol->value.enumerated.item[0] = 1;
1857                break;
1858        case 48000:
1859                ucontrol->value.enumerated.item[0] = 2;
1860                break;
1861        case 64000:
1862                ucontrol->value.enumerated.item[0] = 3;
1863                break;
1864        case 88200:
1865                ucontrol->value.enumerated.item[0] = 4;
1866                break;
1867        case 96000:
1868                ucontrol->value.enumerated.item[0] = 5;
1869                break;
1870        case 128000:
1871                ucontrol->value.enumerated.item[0] = 7;
1872                break;
1873        case 176400:
1874                ucontrol->value.enumerated.item[0] = 8;
1875                break;
1876        case 192000:
1877                ucontrol->value.enumerated.item[0] = 9;
1878                break;
1879        default:
1880                ucontrol->value.enumerated.item[0] = 6;
1881        }
1882        return 0;
1883}
1884
1885#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1886{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1887  .name = xname, \
1888  .index = xindex, \
1889  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1890  .info = snd_hdsp_info_system_clock_mode, \
1891  .get = snd_hdsp_get_system_clock_mode \
1892}
1893
1894static int hdsp_system_clock_mode(struct hdsp *hdsp)
1895{
1896        if (hdsp->control_register & HDSP_ClockModeMaster)
1897                return 0;
1898        else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1899                        return 0;
1900        return 1;
1901}
1902
1903static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1904{
1905        static const char * const texts[] = {"Master", "Slave" };
1906
1907        return snd_ctl_enum_info(uinfo, 1, 2, texts);
1908}
1909
1910static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1911{
1912        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1913
1914        ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1915        return 0;
1916}
1917
1918#define HDSP_CLOCK_SOURCE(xname, xindex) \
1919{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1920  .name = xname, \
1921  .index = xindex, \
1922  .info = snd_hdsp_info_clock_source, \
1923  .get = snd_hdsp_get_clock_source, \
1924  .put = snd_hdsp_put_clock_source \
1925}
1926
1927static int hdsp_clock_source(struct hdsp *hdsp)
1928{
1929        if (hdsp->control_register & HDSP_ClockModeMaster) {
1930                switch (hdsp->system_sample_rate) {
1931                case 32000:
1932                        return 1;
1933                case 44100:
1934                        return 2;
1935                case 48000:
1936                        return 3;
1937                case 64000:
1938                        return 4;
1939                case 88200:
1940                        return 5;
1941                case 96000:
1942                        return 6;
1943                case 128000:
1944                        return 7;
1945                case 176400:
1946                        return 8;
1947                case 192000:
1948                        return 9;
1949                default:
1950                        return 3;
1951                }
1952        } else {
1953                return 0;
1954        }
1955}
1956
1957static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1958{
1959        int rate;
1960        switch (mode) {
1961        case HDSP_CLOCK_SOURCE_AUTOSYNC:
1962                if (hdsp_external_sample_rate(hdsp) != 0) {
1963                    if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1964                        hdsp->control_register &= ~HDSP_ClockModeMaster;
1965                        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1966                        return 0;
1967                    }
1968                }
1969                return -1;
1970        case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1971                rate = 32000;
1972                break;
1973        case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1974                rate = 44100;
1975                break;
1976        case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1977                rate = 48000;
1978                break;
1979        case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1980                rate = 64000;
1981                break;
1982        case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1983                rate = 88200;
1984                break;
1985        case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1986                rate = 96000;
1987                break;
1988        case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1989                rate = 128000;
1990                break;
1991        case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1992                rate = 176400;
1993                break;
1994        case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
1995                rate = 192000;
1996                break;
1997        default:
1998                rate = 48000;
1999        }
2000        hdsp->control_register |= HDSP_ClockModeMaster;
2001        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2002        hdsp_set_rate(hdsp, rate, 1);
2003        return 0;
2004}
2005
2006static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2007{
2008        static const char * const texts[] = {
2009                "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2010                "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2011                "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2012                "Internal 192.0 KHz"
2013        };
2014        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2015
2016        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2017                                 texts);
2018}
2019
2020static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2021{
2022        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2023
2024        ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2025        return 0;
2026}
2027
2028static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2029{
2030        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2031        int change;
2032        int val;
2033
2034        if (!snd_hdsp_use_is_exclusive(hdsp))
2035                return -EBUSY;
2036        val = ucontrol->value.enumerated.item[0];
2037        if (val < 0) val = 0;
2038        if (hdsp->io_type == H9632) {
2039                if (val > 9)
2040                        val = 9;
2041        } else {
2042                if (val > 6)
2043                        val = 6;
2044        }
2045        spin_lock_irq(&hdsp->lock);
2046        if (val != hdsp_clock_source(hdsp))
2047                change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2048        else
2049                change = 0;
2050        spin_unlock_irq(&hdsp->lock);
2051        return change;
2052}
2053
2054#define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2055
2056static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2057{
2058        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2059
2060        ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2061        return 0;
2062}
2063
2064static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2065{
2066        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2067        int change;
2068
2069        change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2070        if (change)
2071                hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2072        return change;
2073}
2074
2075#define HDSP_DA_GAIN(xname, xindex) \
2076{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2077  .name = xname, \
2078  .index = xindex, \
2079  .info = snd_hdsp_info_da_gain, \
2080  .get = snd_hdsp_get_da_gain, \
2081  .put = snd_hdsp_put_da_gain \
2082}
2083
2084static int hdsp_da_gain(struct hdsp *hdsp)
2085{
2086        switch (hdsp->control_register & HDSP_DAGainMask) {
2087        case HDSP_DAGainHighGain:
2088                return 0;
2089        case HDSP_DAGainPlus4dBu:
2090                return 1;
2091        case HDSP_DAGainMinus10dBV:
2092                return 2;
2093        default:
2094                return 1;
2095        }
2096}
2097
2098static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2099{
2100        hdsp->control_register &= ~HDSP_DAGainMask;
2101        switch (mode) {
2102        case 0:
2103                hdsp->control_register |= HDSP_DAGainHighGain;
2104                break;
2105        case 1:
2106                hdsp->control_register |= HDSP_DAGainPlus4dBu;
2107                break;
2108        case 2:
2109                hdsp->control_register |= HDSP_DAGainMinus10dBV;
2110                break;
2111        default:
2112                return -1;
2113
2114        }
2115        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2116        return 0;
2117}
2118
2119static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2120{
2121        static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2122
2123        return snd_ctl_enum_info(uinfo, 1, 3, texts);
2124}
2125
2126static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2127{
2128        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2129
2130        ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2131        return 0;
2132}
2133
2134static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2135{
2136        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2137        int change;
2138        int val;
2139
2140        if (!snd_hdsp_use_is_exclusive(hdsp))
2141                return -EBUSY;
2142        val = ucontrol->value.enumerated.item[0];
2143        if (val < 0) val = 0;
2144        if (val > 2) val = 2;
2145        spin_lock_irq(&hdsp->lock);
2146        if (val != hdsp_da_gain(hdsp))
2147                change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2148        else
2149                change = 0;
2150        spin_unlock_irq(&hdsp->lock);
2151        return change;
2152}
2153
2154#define HDSP_AD_GAIN(xname, xindex) \
2155{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2156  .name = xname, \
2157  .index = xindex, \
2158  .info = snd_hdsp_info_ad_gain, \
2159  .get = snd_hdsp_get_ad_gain, \
2160  .put = snd_hdsp_put_ad_gain \
2161}
2162
2163static int hdsp_ad_gain(struct hdsp *hdsp)
2164{
2165        switch (hdsp->control_register & HDSP_ADGainMask) {
2166        case HDSP_ADGainMinus10dBV:
2167                return 0;
2168        case HDSP_ADGainPlus4dBu:
2169                return 1;
2170        case HDSP_ADGainLowGain:
2171                return 2;
2172        default:
2173                return 1;
2174        }
2175}
2176
2177static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2178{
2179        hdsp->control_register &= ~HDSP_ADGainMask;
2180        switch (mode) {
2181        case 0:
2182                hdsp->control_register |= HDSP_ADGainMinus10dBV;
2183                break;
2184        case 1:
2185                hdsp->control_register |= HDSP_ADGainPlus4dBu;
2186                break;
2187        case 2:
2188                hdsp->control_register |= HDSP_ADGainLowGain;
2189                break;
2190        default:
2191                return -1;
2192
2193        }
2194        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2195        return 0;
2196}
2197
2198static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2199{
2200        static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2201
2202        return snd_ctl_enum_info(uinfo, 1, 3, texts);
2203}
2204
2205static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2206{
2207        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2208
2209        ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2210        return 0;
2211}
2212
2213static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2214{
2215        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2216        int change;
2217        int val;
2218
2219        if (!snd_hdsp_use_is_exclusive(hdsp))
2220                return -EBUSY;
2221        val = ucontrol->value.enumerated.item[0];
2222        if (val < 0) val = 0;
2223        if (val > 2) val = 2;
2224        spin_lock_irq(&hdsp->lock);
2225        if (val != hdsp_ad_gain(hdsp))
2226                change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2227        else
2228                change = 0;
2229        spin_unlock_irq(&hdsp->lock);
2230        return change;
2231}
2232
2233#define HDSP_PHONE_GAIN(xname, xindex) \
2234{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2235  .name = xname, \
2236  .index = xindex, \
2237  .info = snd_hdsp_info_phone_gain, \
2238  .get = snd_hdsp_get_phone_gain, \
2239  .put = snd_hdsp_put_phone_gain \
2240}
2241
2242static int hdsp_phone_gain(struct hdsp *hdsp)
2243{
2244        switch (hdsp->control_register & HDSP_PhoneGainMask) {
2245        case HDSP_PhoneGain0dB:
2246                return 0;
2247        case HDSP_PhoneGainMinus6dB:
2248                return 1;
2249        case HDSP_PhoneGainMinus12dB:
2250                return 2;
2251        default:
2252                return 0;
2253        }
2254}
2255
2256static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2257{
2258        hdsp->control_register &= ~HDSP_PhoneGainMask;
2259        switch (mode) {
2260        case 0:
2261                hdsp->control_register |= HDSP_PhoneGain0dB;
2262                break;
2263        case 1:
2264                hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2265                break;
2266        case 2:
2267                hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2268                break;
2269        default:
2270                return -1;
2271
2272        }
2273        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2274        return 0;
2275}
2276
2277static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2278{
2279        static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2280
2281        return snd_ctl_enum_info(uinfo, 1, 3, texts);
2282}
2283
2284static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2285{
2286        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2287
2288        ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2289        return 0;
2290}
2291
2292static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2293{
2294        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2295        int change;
2296        int val;
2297
2298        if (!snd_hdsp_use_is_exclusive(hdsp))
2299                return -EBUSY;
2300        val = ucontrol->value.enumerated.item[0];
2301        if (val < 0) val = 0;
2302        if (val > 2) val = 2;
2303        spin_lock_irq(&hdsp->lock);
2304        if (val != hdsp_phone_gain(hdsp))
2305                change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2306        else
2307                change = 0;
2308        spin_unlock_irq(&hdsp->lock);
2309        return change;
2310}
2311
2312#define HDSP_PREF_SYNC_REF(xname, xindex) \
2313{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2314  .name = xname, \
2315  .index = xindex, \
2316  .info = snd_hdsp_info_pref_sync_ref, \
2317  .get = snd_hdsp_get_pref_sync_ref, \
2318  .put = snd_hdsp_put_pref_sync_ref \
2319}
2320
2321static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2322{
2323        /* Notice that this looks at the requested sync source,
2324           not the one actually in use.
2325        */
2326
2327        switch (hdsp->control_register & HDSP_SyncRefMask) {
2328        case HDSP_SyncRef_ADAT1:
2329                return HDSP_SYNC_FROM_ADAT1;
2330        case HDSP_SyncRef_ADAT2:
2331                return HDSP_SYNC_FROM_ADAT2;
2332        case HDSP_SyncRef_ADAT3:
2333                return HDSP_SYNC_FROM_ADAT3;
2334        case HDSP_SyncRef_SPDIF:
2335                return HDSP_SYNC_FROM_SPDIF;
2336        case HDSP_SyncRef_WORD:
2337                return HDSP_SYNC_FROM_WORD;
2338        case HDSP_SyncRef_ADAT_SYNC:
2339                return HDSP_SYNC_FROM_ADAT_SYNC;
2340        default:
2341                return HDSP_SYNC_FROM_WORD;
2342        }
2343        return 0;
2344}
2345
2346static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2347{
2348        hdsp->control_register &= ~HDSP_SyncRefMask;
2349        switch (pref) {
2350        case HDSP_SYNC_FROM_ADAT1:
2351                hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2352                break;
2353        case HDSP_SYNC_FROM_ADAT2:
2354                hdsp->control_register |= HDSP_SyncRef_ADAT2;
2355                break;
2356        case HDSP_SYNC_FROM_ADAT3:
2357                hdsp->control_register |= HDSP_SyncRef_ADAT3;
2358                break;
2359        case HDSP_SYNC_FROM_SPDIF:
2360                hdsp->control_register |= HDSP_SyncRef_SPDIF;
2361                break;
2362        case HDSP_SYNC_FROM_WORD:
2363                hdsp->control_register |= HDSP_SyncRef_WORD;
2364                break;
2365        case HDSP_SYNC_FROM_ADAT_SYNC:
2366                hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2367                break;
2368        default:
2369                return -1;
2370        }
2371        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2372        return 0;
2373}
2374
2375static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2376{
2377        static const char * const texts[] = {
2378                "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2379        };
2380        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2381        int num_items;
2382
2383        switch (hdsp->io_type) {
2384        case Digiface:
2385        case H9652:
2386                num_items = 6;
2387                break;
2388        case Multiface:
2389                num_items = 4;
2390                break;
2391        case H9632:
2392                num_items = 3;
2393                break;
2394        default:
2395                return -EINVAL;
2396        }
2397
2398        return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2399}
2400
2401static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2402{
2403        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2404
2405        ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2406        return 0;
2407}
2408
2409static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2410{
2411        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2412        int change, max;
2413        unsigned int val;
2414
2415        if (!snd_hdsp_use_is_exclusive(hdsp))
2416                return -EBUSY;
2417
2418        switch (hdsp->io_type) {
2419        case Digiface:
2420        case H9652:
2421                max = 6;
2422                break;
2423        case Multiface:
2424                max = 4;
2425                break;
2426        case H9632:
2427                max = 3;
2428                break;
2429        default:
2430                return -EIO;
2431        }
2432
2433        val = ucontrol->value.enumerated.item[0] % max;
2434        spin_lock_irq(&hdsp->lock);
2435        change = (int)val != hdsp_pref_sync_ref(hdsp);
2436        hdsp_set_pref_sync_ref(hdsp, val);
2437        spin_unlock_irq(&hdsp->lock);
2438        return change;
2439}
2440
2441#define HDSP_AUTOSYNC_REF(xname, xindex) \
2442{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2443  .name = xname, \
2444  .index = xindex, \
2445  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2446  .info = snd_hdsp_info_autosync_ref, \
2447  .get = snd_hdsp_get_autosync_ref, \
2448}
2449
2450static int hdsp_autosync_ref(struct hdsp *hdsp)
2451{
2452        /* This looks at the autosync selected sync reference */
2453        unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2454
2455        switch (status2 & HDSP_SelSyncRefMask) {
2456        case HDSP_SelSyncRef_WORD:
2457                return HDSP_AUTOSYNC_FROM_WORD;
2458        case HDSP_SelSyncRef_ADAT_SYNC:
2459                return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2460        case HDSP_SelSyncRef_SPDIF:
2461                return HDSP_AUTOSYNC_FROM_SPDIF;
2462        case HDSP_SelSyncRefMask:
2463                return HDSP_AUTOSYNC_FROM_NONE;
2464        case HDSP_SelSyncRef_ADAT1:
2465                return HDSP_AUTOSYNC_FROM_ADAT1;
2466        case HDSP_SelSyncRef_ADAT2:
2467                return HDSP_AUTOSYNC_FROM_ADAT2;
2468        case HDSP_SelSyncRef_ADAT3:
2469                return HDSP_AUTOSYNC_FROM_ADAT3;
2470        default:
2471                return HDSP_AUTOSYNC_FROM_WORD;
2472        }
2473        return 0;
2474}
2475
2476static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2477{
2478        static const char * const texts[] = {
2479                "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2480        };
2481
2482        return snd_ctl_enum_info(uinfo, 1, 7, texts);
2483}
2484
2485static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2486{
2487        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2488
2489        ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2490        return 0;
2491}
2492
2493#define HDSP_PRECISE_POINTER(xname, xindex) \
2494{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2495  .name = xname, \
2496  .index = xindex, \
2497  .info = snd_hdsp_info_precise_pointer, \
2498  .get = snd_hdsp_get_precise_pointer, \
2499  .put = snd_hdsp_put_precise_pointer \
2500}
2501
2502static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2503{
2504        if (precise)
2505                hdsp->precise_ptr = 1;
2506        else
2507                hdsp->precise_ptr = 0;
2508        return 0;
2509}
2510
2511#define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2512
2513static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2514{
2515        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2516
2517        spin_lock_irq(&hdsp->lock);
2518        ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2519        spin_unlock_irq(&hdsp->lock);
2520        return 0;
2521}
2522
2523static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2524{
2525        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2526        int change;
2527        unsigned int val;
2528
2529        if (!snd_hdsp_use_is_exclusive(hdsp))
2530                return -EBUSY;
2531        val = ucontrol->value.integer.value[0] & 1;
2532        spin_lock_irq(&hdsp->lock);
2533        change = (int)val != hdsp->precise_ptr;
2534        hdsp_set_precise_pointer(hdsp, val);
2535        spin_unlock_irq(&hdsp->lock);
2536        return change;
2537}
2538
2539#define HDSP_USE_MIDI_WORK(xname, xindex) \
2540{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2541  .name = xname, \
2542  .index = xindex, \
2543  .info = snd_hdsp_info_use_midi_work, \
2544  .get = snd_hdsp_get_use_midi_work, \
2545  .put = snd_hdsp_put_use_midi_work \
2546}
2547
2548static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2549{
2550        if (use_work)
2551                hdsp->use_midi_work = 1;
2552        else
2553                hdsp->use_midi_work = 0;
2554        return 0;
2555}
2556
2557#define snd_hdsp_info_use_midi_work             snd_ctl_boolean_mono_info
2558
2559static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2560{
2561        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2562
2563        spin_lock_irq(&hdsp->lock);
2564        ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2565        spin_unlock_irq(&hdsp->lock);
2566        return 0;
2567}
2568
2569static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2570{
2571        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2572        int change;
2573        unsigned int val;
2574
2575        if (!snd_hdsp_use_is_exclusive(hdsp))
2576                return -EBUSY;
2577        val = ucontrol->value.integer.value[0] & 1;
2578        spin_lock_irq(&hdsp->lock);
2579        change = (int)val != hdsp->use_midi_work;
2580        hdsp_set_use_midi_work(hdsp, val);
2581        spin_unlock_irq(&hdsp->lock);
2582        return change;
2583}
2584
2585#define HDSP_MIXER(xname, xindex) \
2586{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2587  .name = xname, \
2588  .index = xindex, \
2589  .device = 0, \
2590  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2591                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2592  .info = snd_hdsp_info_mixer, \
2593  .get = snd_hdsp_get_mixer, \
2594  .put = snd_hdsp_put_mixer \
2595}
2596
2597static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2598{
2599        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2600        uinfo->count = 3;
2601        uinfo->value.integer.min = 0;
2602        uinfo->value.integer.max = 65536;
2603        uinfo->value.integer.step = 1;
2604        return 0;
2605}
2606
2607static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2608{
2609        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2610        int source;
2611        int destination;
2612        int addr;
2613
2614        source = ucontrol->value.integer.value[0];
2615        destination = ucontrol->value.integer.value[1];
2616
2617        if (source >= hdsp->max_channels)
2618                addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2619        else
2620                addr = hdsp_input_to_output_key(hdsp,source, destination);
2621
2622        spin_lock_irq(&hdsp->lock);
2623        ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2624        spin_unlock_irq(&hdsp->lock);
2625        return 0;
2626}
2627
2628static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2629{
2630        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2631        int change;
2632        int source;
2633        int destination;
2634        int gain;
2635        int addr;
2636
2637        if (!snd_hdsp_use_is_exclusive(hdsp))
2638                return -EBUSY;
2639
2640        source = ucontrol->value.integer.value[0];
2641        destination = ucontrol->value.integer.value[1];
2642
2643        if (source >= hdsp->max_channels)
2644                addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2645        else
2646                addr = hdsp_input_to_output_key(hdsp,source, destination);
2647
2648        gain = ucontrol->value.integer.value[2];
2649
2650        spin_lock_irq(&hdsp->lock);
2651        change = gain != hdsp_read_gain(hdsp, addr);
2652        if (change)
2653                hdsp_write_gain(hdsp, addr, gain);
2654        spin_unlock_irq(&hdsp->lock);
2655        return change;
2656}
2657
2658#define HDSP_WC_SYNC_CHECK(xname, xindex) \
2659{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2660  .name = xname, \
2661  .index = xindex, \
2662  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2663  .info = snd_hdsp_info_sync_check, \
2664  .get = snd_hdsp_get_wc_sync_check \
2665}
2666
2667static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2668{
2669        static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2670
2671        return snd_ctl_enum_info(uinfo, 1, 3, texts);
2672}
2673
2674static int hdsp_wc_sync_check(struct hdsp *hdsp)
2675{
2676        int status2 = hdsp_read(hdsp, HDSP_status2Register);
2677        if (status2 & HDSP_wc_lock) {
2678                if (status2 & HDSP_wc_sync)
2679                        return 2;
2680                else
2681                         return 1;
2682        } else
2683                return 0;
2684        return 0;
2685}
2686
2687static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2688{
2689        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2690
2691        ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2692        return 0;
2693}
2694
2695#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2696{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2697  .name = xname, \
2698  .index = xindex, \
2699  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2700  .info = snd_hdsp_info_sync_check, \
2701  .get = snd_hdsp_get_spdif_sync_check \
2702}
2703
2704static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2705{
2706        int status = hdsp_read(hdsp, HDSP_statusRegister);
2707        if (status & HDSP_SPDIFErrorFlag)
2708                return 0;
2709        else {
2710                if (status & HDSP_SPDIFSync)
2711                        return 2;
2712                else
2713                        return 1;
2714        }
2715        return 0;
2716}
2717
2718static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2719{
2720        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2721
2722        ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2723        return 0;
2724}
2725
2726#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2727{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2728  .name = xname, \
2729  .index = xindex, \
2730  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2731  .info = snd_hdsp_info_sync_check, \
2732  .get = snd_hdsp_get_adatsync_sync_check \
2733}
2734
2735static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2736{
2737        int status = hdsp_read(hdsp, HDSP_statusRegister);
2738        if (status & HDSP_TimecodeLock) {
2739                if (status & HDSP_TimecodeSync)
2740                        return 2;
2741                else
2742                        return 1;
2743        } else
2744                return 0;
2745}
2746
2747static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2748{
2749        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2750
2751        ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2752        return 0;
2753}
2754
2755#define HDSP_ADAT_SYNC_CHECK \
2756{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2757  .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2758  .info = snd_hdsp_info_sync_check, \
2759  .get = snd_hdsp_get_adat_sync_check \
2760}
2761
2762static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2763{
2764        int status = hdsp_read(hdsp, HDSP_statusRegister);
2765
2766        if (status & (HDSP_Lock0>>idx)) {
2767                if (status & (HDSP_Sync0>>idx))
2768                        return 2;
2769                else
2770                        return 1;
2771        } else
2772                return 0;
2773}
2774
2775static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2776{
2777        int offset;
2778        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2779
2780        offset = ucontrol->id.index - 1;
2781        if (snd_BUG_ON(offset < 0))
2782                return -EINVAL;
2783
2784        switch (hdsp->io_type) {
2785        case Digiface:
2786        case H9652:
2787                if (offset >= 3)
2788                        return -EINVAL;
2789                break;
2790        case Multiface:
2791        case H9632:
2792                if (offset >= 1)
2793                        return -EINVAL;
2794                break;
2795        default:
2796                return -EIO;
2797        }
2798
2799        ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2800        return 0;
2801}
2802
2803#define HDSP_DDS_OFFSET(xname, xindex) \
2804{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2805  .name = xname, \
2806  .index = xindex, \
2807  .info = snd_hdsp_info_dds_offset, \
2808  .get = snd_hdsp_get_dds_offset, \
2809  .put = snd_hdsp_put_dds_offset \
2810}
2811
2812static int hdsp_dds_offset(struct hdsp *hdsp)
2813{
2814        u64 n;
2815        unsigned int dds_value = hdsp->dds_value;
2816        int system_sample_rate = hdsp->system_sample_rate;
2817
2818        if (!dds_value)
2819                return 0;
2820
2821        n = DDS_NUMERATOR;
2822        /*
2823         * dds_value = n / rate
2824         * rate = n / dds_value
2825         */
2826        n = div_u64(n, dds_value);
2827        if (system_sample_rate >= 112000)
2828                n *= 4;
2829        else if (system_sample_rate >= 56000)
2830                n *= 2;
2831        return ((int)n) - system_sample_rate;
2832}
2833
2834static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2835{
2836        int rate = hdsp->system_sample_rate + offset_hz;
2837        hdsp_set_dds_value(hdsp, rate);
2838        return 0;
2839}
2840
2841static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2842{
2843        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2844        uinfo->count = 1;
2845        uinfo->value.integer.min = -5000;
2846        uinfo->value.integer.max = 5000;
2847        return 0;
2848}
2849
2850static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2851{
2852        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2853
2854        ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2855        return 0;
2856}
2857
2858static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2859{
2860        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2861        int change;
2862        int val;
2863
2864        if (!snd_hdsp_use_is_exclusive(hdsp))
2865                return -EBUSY;
2866        val = ucontrol->value.integer.value[0];
2867        spin_lock_irq(&hdsp->lock);
2868        if (val != hdsp_dds_offset(hdsp))
2869                change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2870        else
2871                change = 0;
2872        spin_unlock_irq(&hdsp->lock);
2873        return change;
2874}
2875
2876static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2877HDSP_DA_GAIN("DA Gain", 0),
2878HDSP_AD_GAIN("AD Gain", 0),
2879HDSP_PHONE_GAIN("Phones Gain", 0),
2880HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2881HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2882};
2883
2884static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2885{
2886        .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2887        .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2888        .info =         snd_hdsp_control_spdif_info,
2889        .get =          snd_hdsp_control_spdif_get,
2890        .put =          snd_hdsp_control_spdif_put,
2891},
2892{
2893        .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2894        .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2895        .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2896        .info =         snd_hdsp_control_spdif_stream_info,
2897        .get =          snd_hdsp_control_spdif_stream_get,
2898        .put =          snd_hdsp_control_spdif_stream_put,
2899},
2900{
2901        .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2902        .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2903        .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2904        .info =         snd_hdsp_control_spdif_mask_info,
2905        .get =          snd_hdsp_control_spdif_mask_get,
2906        .private_value = IEC958_AES0_NONAUDIO |
2907                         IEC958_AES0_PROFESSIONAL |
2908                         IEC958_AES0_CON_EMPHASIS,
2909},
2910{
2911        .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2912        .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2913        .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2914        .info =         snd_hdsp_control_spdif_mask_info,
2915        .get =          snd_hdsp_control_spdif_mask_get,
2916        .private_value = IEC958_AES0_NONAUDIO |
2917                         IEC958_AES0_PROFESSIONAL |
2918                         IEC958_AES0_PRO_EMPHASIS,
2919},
2920HDSP_MIXER("Mixer", 0),
2921HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2922HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2923HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2924HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2925HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2926/* 'Sample Clock Source' complies with the alsa control naming scheme */
2927HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2928{
2929        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2930        .name = "Sample Clock Source Locking",
2931        .info = snd_hdsp_info_clock_source_lock,
2932        .get = snd_hdsp_get_clock_source_lock,
2933        .put = snd_hdsp_put_clock_source_lock,
2934},
2935HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2936HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2937HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2938HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2939HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2940/* 'External Rate' complies with the alsa control naming scheme */
2941HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2942HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2943HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2944HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2945HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2946HDSP_PRECISE_POINTER("Precise Pointer", 0),
2947HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2948};
2949
2950
2951static int hdsp_rpm_input12(struct hdsp *hdsp)
2952{
2953        switch (hdsp->control_register & HDSP_RPM_Inp12) {
2954        case HDSP_RPM_Inp12_Phon_6dB:
2955                return 0;
2956        case HDSP_RPM_Inp12_Phon_n6dB:
2957                return 2;
2958        case HDSP_RPM_Inp12_Line_0dB:
2959                return 3;
2960        case HDSP_RPM_Inp12_Line_n6dB:
2961                return 4;
2962        }
2963        return 1;
2964}
2965
2966
2967static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2968{
2969        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2970
2971        ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2972        return 0;
2973}
2974
2975
2976static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2977{
2978        hdsp->control_register &= ~HDSP_RPM_Inp12;
2979        switch (mode) {
2980        case 0:
2981                hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2982                break;
2983        case 1:
2984                break;
2985        case 2:
2986                hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2987                break;
2988        case 3:
2989                hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2990                break;
2991        case 4:
2992                hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2993                break;
2994        default:
2995                return -1;
2996        }
2997
2998        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2999        return 0;
3000}
3001
3002
3003static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3004{
3005        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3006        int change;
3007        int val;
3008
3009        if (!snd_hdsp_use_is_exclusive(hdsp))
3010                return -EBUSY;
3011        val = ucontrol->value.enumerated.item[0];
3012        if (val < 0)
3013                val = 0;
3014        if (val > 4)
3015                val = 4;
3016        spin_lock_irq(&hdsp->lock);
3017        if (val != hdsp_rpm_input12(hdsp))
3018                change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3019        else
3020                change = 0;
3021        spin_unlock_irq(&hdsp->lock);
3022        return change;
3023}
3024
3025
3026static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3027{
3028        static const char * const texts[] = {
3029                "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3030        };
3031
3032        return snd_ctl_enum_info(uinfo, 1, 5, texts);
3033}
3034
3035
3036static int hdsp_rpm_input34(struct hdsp *hdsp)
3037{
3038        switch (hdsp->control_register & HDSP_RPM_Inp34) {
3039        case HDSP_RPM_Inp34_Phon_6dB:
3040                return 0;
3041        case HDSP_RPM_Inp34_Phon_n6dB:
3042                return 2;
3043        case HDSP_RPM_Inp34_Line_0dB:
3044                return 3;
3045        case HDSP_RPM_Inp34_Line_n6dB:
3046                return 4;
3047        }
3048        return 1;
3049}
3050
3051
3052static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3053{
3054        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3055
3056        ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3057        return 0;
3058}
3059
3060
3061static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3062{
3063        hdsp->control_register &= ~HDSP_RPM_Inp34;
3064        switch (mode) {
3065        case 0:
3066                hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3067                break;
3068        case 1:
3069                break;
3070        case 2:
3071                hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3072                break;
3073        case 3:
3074                hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3075                break;
3076        case 4:
3077                hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3078                break;
3079        default:
3080                return -1;
3081        }
3082
3083        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3084        return 0;
3085}
3086
3087
3088static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3089{
3090        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3091        int change;
3092        int val;
3093
3094        if (!snd_hdsp_use_is_exclusive(hdsp))
3095                return -EBUSY;
3096        val = ucontrol->value.enumerated.item[0];
3097        if (val < 0)
3098                val = 0;
3099        if (val > 4)
3100                val = 4;
3101        spin_lock_irq(&hdsp->lock);
3102        if (val != hdsp_rpm_input34(hdsp))
3103                change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3104        else
3105                change = 0;
3106        spin_unlock_irq(&hdsp->lock);
3107        return change;
3108}
3109
3110
3111/* RPM Bypass switch */
3112static int hdsp_rpm_bypass(struct hdsp *hdsp)
3113{
3114        return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3115}
3116
3117
3118static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3119{
3120        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3121
3122        ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3123        return 0;
3124}
3125
3126
3127static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3128{
3129        if (on)
3130                hdsp->control_register |= HDSP_RPM_Bypass;
3131        else
3132                hdsp->control_register &= ~HDSP_RPM_Bypass;
3133        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3134        return 0;
3135}
3136
3137
3138static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3139{
3140        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3141        int change;
3142        unsigned int val;
3143
3144        if (!snd_hdsp_use_is_exclusive(hdsp))
3145                return -EBUSY;
3146        val = ucontrol->value.integer.value[0] & 1;
3147        spin_lock_irq(&hdsp->lock);
3148        change = (int)val != hdsp_rpm_bypass(hdsp);
3149        hdsp_set_rpm_bypass(hdsp, val);
3150        spin_unlock_irq(&hdsp->lock);
3151        return change;
3152}
3153
3154
3155static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3156{
3157        static const char * const texts[] = {"On", "Off"};
3158
3159        return snd_ctl_enum_info(uinfo, 1, 2, texts);
3160}
3161
3162
3163/* RPM Disconnect switch */
3164static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3165{
3166        return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3167}
3168
3169
3170static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3171{
3172        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3173
3174        ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3175        return 0;
3176}
3177
3178
3179static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3180{
3181        if (on)
3182                hdsp->control_register |= HDSP_RPM_Disconnect;
3183        else
3184                hdsp->control_register &= ~HDSP_RPM_Disconnect;
3185        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3186        return 0;
3187}
3188
3189
3190static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3191{
3192        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3193        int change;
3194        unsigned int val;
3195
3196        if (!snd_hdsp_use_is_exclusive(hdsp))
3197                return -EBUSY;
3198        val = ucontrol->value.integer.value[0] & 1;
3199        spin_lock_irq(&hdsp->lock);
3200        change = (int)val != hdsp_rpm_disconnect(hdsp);
3201        hdsp_set_rpm_disconnect(hdsp, val);
3202        spin_unlock_irq(&hdsp->lock);
3203        return change;
3204}
3205
3206static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3207{
3208        static const char * const texts[] = {"On", "Off"};
3209
3210        return snd_ctl_enum_info(uinfo, 1, 2, texts);
3211}
3212
3213static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3214        {
3215                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3216                .name = "RPM Bypass",
3217                .get = snd_hdsp_get_rpm_bypass,
3218                .put = snd_hdsp_put_rpm_bypass,
3219                .info = snd_hdsp_info_rpm_bypass
3220        },
3221        {
3222                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3223                .name = "RPM Disconnect",
3224                .get = snd_hdsp_get_rpm_disconnect,
3225                .put = snd_hdsp_put_rpm_disconnect,
3226                .info = snd_hdsp_info_rpm_disconnect
3227        },
3228        {
3229                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3230                .name = "Input 1/2",
3231                .get = snd_hdsp_get_rpm_input12,
3232                .put = snd_hdsp_put_rpm_input12,
3233                .info = snd_hdsp_info_rpm_input
3234        },
3235        {
3236                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3237                .name = "Input 3/4",
3238                .get = snd_hdsp_get_rpm_input34,
3239                .put = snd_hdsp_put_rpm_input34,
3240                .info = snd_hdsp_info_rpm_input
3241        },
3242        HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3243        HDSP_MIXER("Mixer", 0)
3244};
3245
3246static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3247        HDSP_TOGGLE_SETTING("Analog Extension Board",
3248                        HDSP_AnalogExtensionBoard);
3249static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3250
3251
3252static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3253{
3254        return hdsp->io_loopback & (1 << channel);
3255}
3256
3257static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3258{
3259        if (hdsp_loopback_get(hdsp, channel) == enable)
3260                return 0;
3261
3262        hdsp->io_loopback ^= (1 << channel);
3263
3264        hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3265
3266        return 1;
3267}
3268
3269static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3270                                 struct snd_ctl_elem_value *const ucontrol)
3271{
3272        struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3273        const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3274
3275        if (channel >= hdsp->max_channels)
3276                return -ENOENT;
3277
3278        ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3279
3280        return 0;
3281}
3282
3283static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3284                                 struct snd_ctl_elem_value *const ucontrol)
3285{
3286        struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3287        const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3288        const bool enable = ucontrol->value.integer.value[0] & 1;
3289
3290        if (channel >= hdsp->max_channels)
3291                return -ENOENT;
3292
3293        return hdsp_loopback_set(hdsp, channel, enable);
3294}
3295
3296static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3297        .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3298        .name = "Output Loopback",
3299        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3300        .info = snd_ctl_boolean_mono_info,
3301        .get = snd_hdsp_loopback_get,
3302        .put = snd_hdsp_loopback_put
3303};
3304
3305static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3306{
3307        unsigned int idx;
3308        int err;
3309        struct snd_kcontrol *kctl;
3310
3311        if (hdsp->io_type == RPM) {
3312                /* RPM Bypass, Disconnect and Input switches */
3313                for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3314                        err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3315                        if (err < 0)
3316                                return err;
3317                }
3318                return 0;
3319        }
3320
3321        for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3322                kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);
3323                err = snd_ctl_add(card, kctl);
3324                if (err < 0)
3325                        return err;
3326                if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3327                        hdsp->spdif_ctl = kctl;
3328        }
3329
3330        /* ADAT SyncCheck status */
3331        snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3332        snd_hdsp_adat_sync_check.index = 1;
3333        kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3334        err = snd_ctl_add(card, kctl);
3335        if (err < 0)
3336                return err;
3337        if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3338                for (idx = 1; idx < 3; ++idx) {
3339                        snd_hdsp_adat_sync_check.index = idx+1;
3340                        kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3341                        err = snd_ctl_add(card, kctl);
3342                        if (err < 0)
3343                                return err;
3344                }
3345        }
3346
3347        /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3348        if (hdsp->io_type == H9632) {
3349                for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3350                        kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);
3351                        err = snd_ctl_add(card, kctl);
3352                        if (err < 0)
3353                                return err;
3354                }
3355        }
3356
3357        /* Output loopback controls for H9632 cards */
3358        if (hdsp->io_type == H9632) {
3359                snd_hdsp_loopback_control.count = hdsp->max_channels;
3360                kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3361                if (kctl == NULL)
3362                        return -ENOMEM;
3363                err = snd_ctl_add(card, kctl);
3364                if (err < 0)
3365                        return err;
3366        }
3367
3368        /* AEB control for H96xx card */
3369        if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3370                kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);
3371                err = snd_ctl_add(card, kctl);
3372                if (err < 0)
3373                        return err;
3374        }
3375
3376        return 0;
3377}
3378
3379/*------------------------------------------------------------
3380   /proc interface
3381 ------------------------------------------------------------*/
3382
3383static void
3384snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3385{
3386        struct hdsp *hdsp = entry->private_data;
3387        unsigned int status;
3388        unsigned int status2;
3389        char *pref_sync_ref;
3390        char *autosync_ref;
3391        char *system_clock_mode;
3392        char *clock_source;
3393        int x;
3394
3395        status = hdsp_read(hdsp, HDSP_statusRegister);
3396        status2 = hdsp_read(hdsp, HDSP_status2Register);
3397
3398        snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3399                    hdsp->card->number + 1);
3400        snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3401                    hdsp->capture_buffer, hdsp->playback_buffer);
3402        snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3403                    hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3404        snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3405        snd_iprintf(buffer, "Control2 register: 0x%x\n",
3406                    hdsp->control2_register);
3407        snd_iprintf(buffer, "Status register: 0x%x\n", status);
3408        snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3409
3410        if (hdsp_check_for_iobox(hdsp)) {
3411                snd_iprintf(buffer, "No I/O box connected.\n"
3412                            "Please connect one and upload firmware.\n");
3413                return;
3414        }
3415
3416        if (hdsp_check_for_firmware(hdsp, 0)) {
3417                if (hdsp->state & HDSP_FirmwareCached) {
3418                        if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3419                                snd_iprintf(buffer, "Firmware loading from "
3420                                            "cache failed, "
3421                                            "please upload manually.\n");
3422                                return;
3423                        }
3424                } else {
3425                        int err;
3426
3427                        err = hdsp_request_fw_loader(hdsp);
3428                        if (err < 0) {
3429                                snd_iprintf(buffer,
3430                                            "No firmware loaded nor cached, "
3431                                            "please upload firmware.\n");
3432                                return;
3433                        }
3434                }
3435        }
3436
3437        snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3438        snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3439        snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3440        snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3441        snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3442        snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3443
3444        snd_iprintf(buffer, "\n");
3445
3446        x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3447
3448        snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3449        snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3450        snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3451        snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3452
3453        snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3454
3455        snd_iprintf(buffer, "\n");
3456
3457        switch (hdsp_clock_source(hdsp)) {
3458        case HDSP_CLOCK_SOURCE_AUTOSYNC:
3459                clock_source = "AutoSync";
3460                break;
3461        case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3462                clock_source = "Internal 32 kHz";
3463                break;
3464        case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3465                clock_source = "Internal 44.1 kHz";
3466                break;
3467        case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3468                clock_source = "Internal 48 kHz";
3469                break;
3470        case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3471                clock_source = "Internal 64 kHz";
3472                break;
3473        case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3474                clock_source = "Internal 88.2 kHz";
3475                break;
3476        case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3477                clock_source = "Internal 96 kHz";
3478                break;
3479        case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3480                clock_source = "Internal 128 kHz";
3481                break;
3482        case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3483                clock_source = "Internal 176.4 kHz";
3484                break;
3485                case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3486                clock_source = "Internal 192 kHz";
3487                break;
3488        default:
3489                clock_source = "Error";
3490        }
3491        snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3492
3493        if (hdsp_system_clock_mode(hdsp))
3494                system_clock_mode = "Slave";
3495        else
3496                system_clock_mode = "Master";
3497
3498        switch (hdsp_pref_sync_ref (hdsp)) {
3499        case HDSP_SYNC_FROM_WORD:
3500                pref_sync_ref = "Word Clock";
3501                break;
3502        case HDSP_SYNC_FROM_ADAT_SYNC:
3503                pref_sync_ref = "ADAT Sync";
3504                break;
3505        case HDSP_SYNC_FROM_SPDIF:
3506                pref_sync_ref = "SPDIF";
3507                break;
3508        case HDSP_SYNC_FROM_ADAT1:
3509                pref_sync_ref = "ADAT1";
3510                break;
3511        case HDSP_SYNC_FROM_ADAT2:
3512                pref_sync_ref = "ADAT2";
3513                break;
3514        case HDSP_SYNC_FROM_ADAT3:
3515                pref_sync_ref = "ADAT3";
3516                break;
3517        default:
3518                pref_sync_ref = "Word Clock";
3519                break;
3520        }
3521        snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3522
3523        switch (hdsp_autosync_ref (hdsp)) {
3524        case HDSP_AUTOSYNC_FROM_WORD:
3525                autosync_ref = "Word Clock";
3526                break;
3527        case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3528                autosync_ref = "ADAT Sync";
3529                break;
3530        case HDSP_AUTOSYNC_FROM_SPDIF:
3531                autosync_ref = "SPDIF";
3532                break;
3533        case HDSP_AUTOSYNC_FROM_NONE:
3534                autosync_ref = "None";
3535                break;
3536        case HDSP_AUTOSYNC_FROM_ADAT1:
3537                autosync_ref = "ADAT1";
3538                break;
3539        case HDSP_AUTOSYNC_FROM_ADAT2:
3540                autosync_ref = "ADAT2";
3541                break;
3542        case HDSP_AUTOSYNC_FROM_ADAT3:
3543                autosync_ref = "ADAT3";
3544                break;
3545        default:
3546                autosync_ref = "---";
3547                break;
3548        }
3549        snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3550
3551        snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3552
3553        snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3554
3555        snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3556        snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3557
3558        snd_iprintf(buffer, "\n");
3559
3560        if (hdsp->io_type != RPM) {
3561                switch (hdsp_spdif_in(hdsp)) {
3562                case HDSP_SPDIFIN_OPTICAL:
3563                        snd_iprintf(buffer, "IEC958 input: Optical\n");
3564                        break;
3565                case HDSP_SPDIFIN_COAXIAL:
3566                        snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3567                        break;
3568                case HDSP_SPDIFIN_INTERNAL:
3569                        snd_iprintf(buffer, "IEC958 input: Internal\n");
3570                        break;
3571                case HDSP_SPDIFIN_AES:
3572                        snd_iprintf(buffer, "IEC958 input: AES\n");
3573                        break;
3574                default:
3575                        snd_iprintf(buffer, "IEC958 input: ???\n");
3576                        break;
3577                }
3578        }
3579
3580        if (RPM == hdsp->io_type) {
3581                if (hdsp->control_register & HDSP_RPM_Bypass)
3582                        snd_iprintf(buffer, "RPM Bypass: disabled\n");
3583                else
3584                        snd_iprintf(buffer, "RPM Bypass: enabled\n");
3585                if (hdsp->control_register & HDSP_RPM_Disconnect)
3586                        snd_iprintf(buffer, "RPM disconnected\n");
3587                else
3588                        snd_iprintf(buffer, "RPM connected\n");
3589
3590                switch (hdsp->control_register & HDSP_RPM_Inp12) {
3591                case HDSP_RPM_Inp12_Phon_6dB:
3592                        snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3593                        break;
3594                case HDSP_RPM_Inp12_Phon_0dB:
3595                        snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3596                        break;
3597                case HDSP_RPM_Inp12_Phon_n6dB:
3598                        snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3599                        break;
3600                case HDSP_RPM_Inp12_Line_0dB:
3601                        snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3602                        break;
3603                case HDSP_RPM_Inp12_Line_n6dB:
3604                        snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3605                        break;
3606                default:
3607                        snd_iprintf(buffer, "Input 1/2: ???\n");
3608                }
3609
3610                switch (hdsp->control_register & HDSP_RPM_Inp34) {
3611                case HDSP_RPM_Inp34_Phon_6dB:
3612                        snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3613                        break;
3614                case HDSP_RPM_Inp34_Phon_0dB:
3615                        snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3616                        break;
3617                case HDSP_RPM_Inp34_Phon_n6dB:
3618                        snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3619                        break;
3620                case HDSP_RPM_Inp34_Line_0dB:
3621                        snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3622                        break;
3623                case HDSP_RPM_Inp34_Line_n6dB:
3624                        snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3625                        break;
3626                default:
3627                        snd_iprintf(buffer, "Input 3/4: ???\n");
3628                }
3629
3630        } else {
3631                if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3632                        snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3633                else
3634                        snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3635
3636                if (hdsp->control_register & HDSP_SPDIFProfessional)
3637                        snd_iprintf(buffer, "IEC958 quality: Professional\n");
3638                else
3639                        snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3640
3641                if (hdsp->control_register & HDSP_SPDIFEmphasis)
3642                        snd_iprintf(buffer, "IEC958 emphasis: on\n");
3643                else
3644                        snd_iprintf(buffer, "IEC958 emphasis: off\n");
3645
3646                if (hdsp->control_register & HDSP_SPDIFNonAudio)
3647                        snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3648                else
3649                        snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3650                x = hdsp_spdif_sample_rate(hdsp);
3651                if (x != 0)
3652                        snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3653                else
3654                        snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3655        }
3656        snd_iprintf(buffer, "\n");
3657
3658        /* Sync Check */
3659        x = status & HDSP_Sync0;
3660        if (status & HDSP_Lock0)
3661                snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3662        else
3663                snd_iprintf(buffer, "ADAT1: No Lock\n");
3664
3665        switch (hdsp->io_type) {
3666        case Digiface:
3667        case H9652:
3668                x = status & HDSP_Sync1;
3669                if (status & HDSP_Lock1)
3670                        snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3671                else
3672                        snd_iprintf(buffer, "ADAT2: No Lock\n");
3673                x = status & HDSP_Sync2;
3674                if (status & HDSP_Lock2)
3675                        snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3676                else
3677                        snd_iprintf(buffer, "ADAT3: No Lock\n");
3678                break;
3679        default:
3680                /* relax */
3681                break;
3682        }
3683
3684        x = status & HDSP_SPDIFSync;
3685        if (status & HDSP_SPDIFErrorFlag)
3686                snd_iprintf (buffer, "SPDIF: No Lock\n");
3687        else
3688                snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3689
3690        x = status2 & HDSP_wc_sync;
3691        if (status2 & HDSP_wc_lock)
3692                snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3693        else
3694                snd_iprintf (buffer, "Word Clock: No Lock\n");
3695
3696        x = status & HDSP_TimecodeSync;
3697        if (status & HDSP_TimecodeLock)
3698                snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3699        else
3700                snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3701
3702        snd_iprintf(buffer, "\n");
3703
3704        /* Informations about H9632 specific controls */
3705        if (hdsp->io_type == H9632) {
3706                char *tmp;
3707
3708                switch (hdsp_ad_gain(hdsp)) {
3709                case 0:
3710                        tmp = "-10 dBV";
3711                        break;
3712                case 1:
3713                        tmp = "+4 dBu";
3714                        break;
3715                default:
3716                        tmp = "Lo Gain";
3717                        break;
3718                }
3719                snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3720
3721                switch (hdsp_da_gain(hdsp)) {
3722                case 0:
3723                        tmp = "Hi Gain";
3724                        break;
3725                case 1:
3726                        tmp = "+4 dBu";
3727                        break;
3728                default:
3729                        tmp = "-10 dBV";
3730                        break;
3731                }
3732                snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3733
3734                switch (hdsp_phone_gain(hdsp)) {
3735                case 0:
3736                        tmp = "0 dB";
3737                        break;
3738                case 1:
3739                        tmp = "-6 dB";
3740                        break;
3741                default:
3742                        tmp = "-12 dB";
3743                        break;
3744                }
3745                snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3746
3747                snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3748                        hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3749                        "yes" : "no");
3750
3751                if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3752                        snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3753                else
3754                        snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3755                snd_iprintf(buffer, "\n");
3756        }
3757
3758}
3759
3760static void snd_hdsp_proc_init(struct hdsp *hdsp)
3761{
3762        snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3763}
3764
3765static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3766{
3767        unsigned long pb_bus, cb_bus;
3768
3769        hdsp->capture_dma_buf =
3770                snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3771        hdsp->playback_dma_buf =
3772                snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3773        if (!hdsp->capture_dma_buf || !hdsp->playback_dma_buf) {
3774                dev_err(hdsp->card->dev,
3775                        "%s: no buffers available\n", hdsp->card_name);
3776                return -ENOMEM;
3777        }
3778
3779        /* Align to bus-space 64K boundary */
3780
3781        cb_bus = ALIGN(hdsp->capture_dma_buf->addr, 0x10000ul);
3782        pb_bus = ALIGN(hdsp->playback_dma_buf->addr, 0x10000ul);
3783
3784        /* Tell the card where it is */
3785
3786        hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3787        hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3788
3789        hdsp->capture_buffer = hdsp->capture_dma_buf->area + (cb_bus - hdsp->capture_dma_buf->addr);
3790        hdsp->playback_buffer = hdsp->playback_dma_buf->area + (pb_bus - hdsp->playback_dma_buf->addr);
3791
3792        return 0;
3793}
3794
3795static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3796{
3797        unsigned int i;
3798
3799        /* ASSUMPTION: hdsp->lock is either held, or
3800           there is no need to hold it (e.g. during module
3801           initialization).
3802         */
3803
3804        /* set defaults:
3805
3806           SPDIF Input via Coax
3807           Master clock mode
3808           maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3809                            which implies 2 4096 sample, 32Kbyte periods).
3810           Enable line out.
3811         */
3812
3813        hdsp->control_register = HDSP_ClockModeMaster |
3814                                 HDSP_SPDIFInputCoaxial |
3815                                 hdsp_encode_latency(7) |
3816                                 HDSP_LineOut;
3817
3818
3819        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3820
3821#ifdef SNDRV_BIG_ENDIAN
3822        hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3823#else
3824        hdsp->control2_register = 0;
3825#endif
3826        if (hdsp->io_type == H9652)
3827                snd_hdsp_9652_enable_mixer (hdsp);
3828        else
3829                hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3830
3831        hdsp_reset_hw_pointer(hdsp);
3832        hdsp_compute_period_size(hdsp);
3833
3834        /* silence everything */
3835
3836        for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3837                hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3838
3839        for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3840                if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3841                        return -EIO;
3842        }
3843
3844        /* H9632 specific defaults */
3845        if (hdsp->io_type == H9632) {
3846                hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3847                hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3848        }
3849
3850        /* set a default rate so that the channel map is set up.
3851         */
3852
3853        hdsp_set_rate(hdsp, 48000, 1);
3854
3855        return 0;
3856}
3857
3858static void hdsp_midi_work(struct work_struct *work)
3859{
3860        struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3861
3862        if (hdsp->midi[0].pending)
3863                snd_hdsp_midi_input_read (&hdsp->midi[0]);
3864        if (hdsp->midi[1].pending)
3865                snd_hdsp_midi_input_read (&hdsp->midi[1]);
3866}
3867
3868static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3869{
3870        struct hdsp *hdsp = (struct hdsp *) dev_id;
3871        unsigned int status;
3872        int audio;
3873        int midi0;
3874        int midi1;
3875        unsigned int midi0status;
3876        unsigned int midi1status;
3877        int schedule = 0;
3878
3879        status = hdsp_read(hdsp, HDSP_statusRegister);
3880
3881        audio = status & HDSP_audioIRQPending;
3882        midi0 = status & HDSP_midi0IRQPending;
3883        midi1 = status & HDSP_midi1IRQPending;
3884
3885        if (!audio && !midi0 && !midi1)
3886                return IRQ_NONE;
3887
3888        hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3889
3890        midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3891        midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3892
3893        if (!(hdsp->state & HDSP_InitializationComplete))
3894                return IRQ_HANDLED;
3895
3896        if (audio) {
3897                if (hdsp->capture_substream)
3898                        snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3899
3900                if (hdsp->playback_substream)
3901                        snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3902        }
3903
3904        if (midi0 && midi0status) {
3905                if (hdsp->use_midi_work) {
3906                        /* we disable interrupts for this input until processing is done */
3907                        hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3908                        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3909                        hdsp->midi[0].pending = 1;
3910                        schedule = 1;
3911                } else {
3912                        snd_hdsp_midi_input_read (&hdsp->midi[0]);
3913                }
3914        }
3915        if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3916                if (hdsp->use_midi_work) {
3917                        /* we disable interrupts for this input until processing is done */
3918                        hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3919                        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3920                        hdsp->midi[1].pending = 1;
3921                        schedule = 1;
3922                } else {
3923                        snd_hdsp_midi_input_read (&hdsp->midi[1]);
3924                }
3925        }
3926        if (hdsp->use_midi_work && schedule)
3927                queue_work(system_highpri_wq, &hdsp->midi_work);
3928        return IRQ_HANDLED;
3929}
3930
3931static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3932{
3933        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3934        return hdsp_hw_pointer(hdsp);
3935}
3936
3937static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3938                                             int stream,
3939                                             int channel)
3940
3941{
3942        int mapped_channel;
3943
3944        if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3945                return NULL;
3946
3947        mapped_channel = hdsp->channel_map[channel];
3948        if (mapped_channel < 0)
3949                return NULL;
3950
3951        if (stream == SNDRV_PCM_STREAM_CAPTURE)
3952                return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3953        else
3954                return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3955}
3956
3957static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3958                                  int channel, unsigned long pos,
3959                                  void __user *src, unsigned long count)
3960{
3961        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3962        char *channel_buf;
3963
3964        if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3965                return -EINVAL;
3966
3967        channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3968        if (snd_BUG_ON(!channel_buf))
3969                return -EIO;
3970        if (copy_from_user(channel_buf + pos, src, count))
3971                return -EFAULT;
3972        return 0;
3973}
3974
3975static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3976                                         int channel, unsigned long pos,
3977                                         void *src, unsigned long count)
3978{
3979        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3980        char *channel_buf;
3981
3982        channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3983        if (snd_BUG_ON(!channel_buf))
3984                return -EIO;
3985        memcpy(channel_buf + pos, src, count);
3986        return 0;
3987}
3988
3989static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3990                                 int channel, unsigned long pos,
3991                                 void __user *dst, unsigned long count)
3992{
3993        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3994        char *channel_buf;
3995
3996        if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3997                return -EINVAL;
3998
3999        channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4000        if (snd_BUG_ON(!channel_buf))
4001                return -EIO;
4002        if (copy_to_user(dst, channel_buf + pos, count))
4003                return -EFAULT;
4004        return 0;
4005}
4006
4007static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
4008                                        int channel, unsigned long pos,
4009                                        void *dst, unsigned long count)
4010{
4011        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4012        char *channel_buf;
4013
4014        channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
4015        if (snd_BUG_ON(!channel_buf))
4016                return -EIO;
4017        memcpy(dst, channel_buf + pos, count);
4018        return 0;
4019}
4020
4021static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
4022                               int channel, unsigned long pos,
4023                               unsigned long count)
4024{
4025        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4026        char *channel_buf;
4027
4028        channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4029        if (snd_BUG_ON(!channel_buf))
4030                return -EIO;
4031        memset(channel_buf + pos, 0, count);
4032        return 0;
4033}
4034
4035static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4036{
4037        struct snd_pcm_runtime *runtime = substream->runtime;
4038        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4039        struct snd_pcm_substream *other;
4040        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4041                other = hdsp->capture_substream;
4042        else
4043                other = hdsp->playback_substream;
4044        if (hdsp->running)
4045                runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4046        else
4047                runtime->status->hw_ptr = 0;
4048        if (other) {
4049                struct snd_pcm_substream *s;
4050                struct snd_pcm_runtime *oruntime = other->runtime;
4051                snd_pcm_group_for_each_entry(s, substream) {
4052                        if (s == other) {
4053                                oruntime->status->hw_ptr = runtime->status->hw_ptr;
4054                                break;
4055                        }
4056                }
4057        }
4058        return 0;
4059}
4060
4061static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4062                                 struct snd_pcm_hw_params *params)
4063{
4064        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4065        int err;
4066        pid_t this_pid;
4067        pid_t other_pid;
4068
4069        if (hdsp_check_for_iobox (hdsp))
4070                return -EIO;
4071
4072        if (hdsp_check_for_firmware(hdsp, 1))
4073                return -EIO;
4074
4075        spin_lock_irq(&hdsp->lock);
4076
4077        if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4078                hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4079                hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4080                this_pid = hdsp->playback_pid;
4081                other_pid = hdsp->capture_pid;
4082        } else {
4083                this_pid = hdsp->capture_pid;
4084                other_pid = hdsp->playback_pid;
4085        }
4086
4087        if ((other_pid > 0) && (this_pid != other_pid)) {
4088
4089                /* The other stream is open, and not by the same
4090                   task as this one. Make sure that the parameters
4091                   that matter are the same.
4092                 */
4093
4094                if (params_rate(params) != hdsp->system_sample_rate) {
4095                        spin_unlock_irq(&hdsp->lock);
4096                        _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4097                        return -EBUSY;
4098                }
4099
4100                if (params_period_size(params) != hdsp->period_bytes / 4) {
4101                        spin_unlock_irq(&hdsp->lock);
4102                        _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4103                        return -EBUSY;
4104                }
4105
4106                /* We're fine. */
4107
4108                spin_unlock_irq(&hdsp->lock);
4109                return 0;
4110
4111        } else {
4112                spin_unlock_irq(&hdsp->lock);
4113        }
4114
4115        /* how to make sure that the rate matches an externally-set one ?
4116         */
4117
4118        spin_lock_irq(&hdsp->lock);
4119        if (! hdsp->clock_source_locked) {
4120                err = hdsp_set_rate(hdsp, params_rate(params), 0);
4121                if (err < 0) {
4122                        spin_unlock_irq(&hdsp->lock);
4123                        _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4124                        return err;
4125                }
4126        }
4127        spin_unlock_irq(&hdsp->lock);
4128
4129        err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));
4130        if (err < 0) {
4131                _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4132                return err;
4133        }
4134
4135        return 0;
4136}
4137
4138static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4139                                    struct snd_pcm_channel_info *info)
4140{
4141        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4142        unsigned int channel = info->channel;
4143
4144        if (snd_BUG_ON(channel >= hdsp->max_channels))
4145                return -EINVAL;
4146        channel = array_index_nospec(channel, hdsp->max_channels);
4147
4148        if (hdsp->channel_map[channel] < 0)
4149                return -EINVAL;
4150
4151        info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4152        info->first = 0;
4153        info->step = 32;
4154        return 0;
4155}
4156
4157static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4158                             unsigned int cmd, void *arg)
4159{
4160        switch (cmd) {
4161        case SNDRV_PCM_IOCTL1_RESET:
4162                return snd_hdsp_reset(substream);
4163        case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4164                return snd_hdsp_channel_info(substream, arg);
4165        default:
4166                break;
4167        }
4168
4169        return snd_pcm_lib_ioctl(substream, cmd, arg);
4170}
4171
4172static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4173{
4174        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4175        struct snd_pcm_substream *other;
4176        int running;
4177
4178        if (hdsp_check_for_iobox (hdsp))
4179                return -EIO;
4180
4181        if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4182                return -EIO;
4183
4184        spin_lock(&hdsp->lock);
4185        running = hdsp->running;
4186        switch (cmd) {
4187        case SNDRV_PCM_TRIGGER_START:
4188                running |= 1 << substream->stream;
4189                break;
4190        case SNDRV_PCM_TRIGGER_STOP:
4191                running &= ~(1 << substream->stream);
4192                break;
4193        default:
4194                snd_BUG();
4195                spin_unlock(&hdsp->lock);
4196                return -EINVAL;
4197        }
4198        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4199                other = hdsp->capture_substream;
4200        else
4201                other = hdsp->playback_substream;
4202
4203        if (other) {
4204                struct snd_pcm_substream *s;
4205                snd_pcm_group_for_each_entry(s, substream) {
4206                        if (s == other) {
4207                                snd_pcm_trigger_done(s, substream);
4208                                if (cmd == SNDRV_PCM_TRIGGER_START)
4209                                        running |= 1 << s->stream;
4210                                else
4211                                        running &= ~(1 << s->stream);
4212                                goto _ok;
4213                        }
4214                }
4215                if (cmd == SNDRV_PCM_TRIGGER_START) {
4216                        if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4217                            substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4218                                hdsp_silence_playback(hdsp);
4219                } else {
4220                        if (running &&
4221                            substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4222                                hdsp_silence_playback(hdsp);
4223                }
4224        } else {
4225                if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4226                                hdsp_silence_playback(hdsp);
4227        }
4228 _ok:
4229        snd_pcm_trigger_done(substream, substream);
4230        if (!hdsp->running && running)
4231                hdsp_start_audio(hdsp);
4232        else if (hdsp->running && !running)
4233                hdsp_stop_audio(hdsp);
4234        hdsp->running = running;
4235        spin_unlock(&hdsp->lock);
4236
4237        return 0;
4238}
4239
4240static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4241{
4242        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4243        int result = 0;
4244
4245        if (hdsp_check_for_iobox (hdsp))
4246                return -EIO;
4247
4248        if (hdsp_check_for_firmware(hdsp, 1))
4249                return -EIO;
4250
4251        spin_lock_irq(&hdsp->lock);
4252        if (!hdsp->running)
4253                hdsp_reset_hw_pointer(hdsp);
4254        spin_unlock_irq(&hdsp->lock);
4255        return result;
4256}
4257
4258static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4259{
4260        .info =                 (SNDRV_PCM_INFO_MMAP |
4261                                 SNDRV_PCM_INFO_MMAP_VALID |
4262                                 SNDRV_PCM_INFO_NONINTERLEAVED |
4263                                 SNDRV_PCM_INFO_SYNC_START |
4264                                 SNDRV_PCM_INFO_DOUBLE),
4265#ifdef SNDRV_BIG_ENDIAN
4266        .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4267#else
4268        .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4269#endif
4270        .rates =                (SNDRV_PCM_RATE_32000 |
4271                                 SNDRV_PCM_RATE_44100 |
4272                                 SNDRV_PCM_RATE_48000 |
4273                                 SNDRV_PCM_RATE_64000 |
4274                                 SNDRV_PCM_RATE_88200 |
4275                                 SNDRV_PCM_RATE_96000),
4276        .rate_min =             32000,
4277        .rate_max =             96000,
4278        .channels_min =         6,
4279        .channels_max =         HDSP_MAX_CHANNELS,
4280        .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4281        .period_bytes_min =     (64 * 4) * 10,
4282        .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4283        .periods_min =          2,
4284        .periods_max =          2,
4285        .fifo_size =            0
4286};
4287
4288static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4289{
4290        .info =                 (SNDRV_PCM_INFO_MMAP |
4291                                 SNDRV_PCM_INFO_MMAP_VALID |
4292                                 SNDRV_PCM_INFO_NONINTERLEAVED |
4293                                 SNDRV_PCM_INFO_SYNC_START),
4294#ifdef SNDRV_BIG_ENDIAN
4295        .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4296#else
4297        .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4298#endif
4299        .rates =                (SNDRV_PCM_RATE_32000 |
4300                                 SNDRV_PCM_RATE_44100 |
4301                                 SNDRV_PCM_RATE_48000 |
4302                                 SNDRV_PCM_RATE_64000 |
4303                                 SNDRV_PCM_RATE_88200 |
4304                                 SNDRV_PCM_RATE_96000),
4305        .rate_min =             32000,
4306        .rate_max =             96000,
4307        .channels_min =         5,
4308        .channels_max =         HDSP_MAX_CHANNELS,
4309        .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4310        .period_bytes_min =     (64 * 4) * 10,
4311        .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4312        .periods_min =          2,
4313        .periods_max =          2,
4314        .fifo_size =            0
4315};
4316
4317static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4318
4319static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4320        .count = ARRAY_SIZE(hdsp_period_sizes),
4321        .list = hdsp_period_sizes,
4322        .mask = 0
4323};
4324
4325static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4326
4327static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4328        .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4329        .list = hdsp_9632_sample_rates,
4330        .mask = 0
4331};
4332
4333static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4334                                        struct snd_pcm_hw_rule *rule)
4335{
4336        struct hdsp *hdsp = rule->private;
4337        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4338        if (hdsp->io_type == H9632) {
4339                unsigned int list[3];
4340                list[0] = hdsp->qs_in_channels;
4341                list[1] = hdsp->ds_in_channels;
4342                list[2] = hdsp->ss_in_channels;
4343                return snd_interval_list(c, 3, list, 0);
4344        } else {
4345                unsigned int list[2];
4346                list[0] = hdsp->ds_in_channels;
4347                list[1] = hdsp->ss_in_channels;
4348                return snd_interval_list(c, 2, list, 0);
4349        }
4350}
4351
4352static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4353                                        struct snd_pcm_hw_rule *rule)
4354{
4355        unsigned int list[3];
4356        struct hdsp *hdsp = rule->private;
4357        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4358        if (hdsp->io_type == H9632) {
4359                list[0] = hdsp->qs_out_channels;
4360                list[1] = hdsp->ds_out_channels;
4361                list[2] = hdsp->ss_out_channels;
4362                return snd_interval_list(c, 3, list, 0);
4363        } else {
4364                list[0] = hdsp->ds_out_channels;
4365                list[1] = hdsp->ss_out_channels;
4366        }
4367        return snd_interval_list(c, 2, list, 0);
4368}
4369
4370static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4371                                             struct snd_pcm_hw_rule *rule)
4372{
4373        struct hdsp *hdsp = rule->private;
4374        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4375        struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4376        if (r->min > 96000 && hdsp->io_type == H9632) {
4377                struct snd_interval t = {
4378                        .min = hdsp->qs_in_channels,
4379                        .max = hdsp->qs_in_channels,
4380                        .integer = 1,
4381                };
4382                return snd_interval_refine(c, &t);
4383        } else if (r->min > 48000 && r->max <= 96000) {
4384                struct snd_interval t = {
4385                        .min = hdsp->ds_in_channels,
4386                        .max = hdsp->ds_in_channels,
4387                        .integer = 1,
4388                };
4389                return snd_interval_refine(c, &t);
4390        } else if (r->max < 64000) {
4391                struct snd_interval t = {
4392                        .min = hdsp->ss_in_channels,
4393                        .max = hdsp->ss_in_channels,
4394                        .integer = 1,
4395                };
4396                return snd_interval_refine(c, &t);
4397        }
4398        return 0;
4399}
4400
4401static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4402                                             struct snd_pcm_hw_rule *rule)
4403{
4404        struct hdsp *hdsp = rule->private;
4405        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4406        struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4407        if (r->min > 96000 && hdsp->io_type == H9632) {
4408                struct snd_interval t = {
4409                        .min = hdsp->qs_out_channels,
4410                        .max = hdsp->qs_out_channels,
4411                        .integer = 1,
4412                };
4413                return snd_interval_refine(c, &t);
4414        } else if (r->min > 48000 && r->max <= 96000) {
4415                struct snd_interval t = {
4416                        .min = hdsp->ds_out_channels,
4417                        .max = hdsp->ds_out_channels,
4418                        .integer = 1,
4419                };
4420                return snd_interval_refine(c, &t);
4421        } else if (r->max < 64000) {
4422                struct snd_interval t = {
4423                        .min = hdsp->ss_out_channels,
4424                        .max = hdsp->ss_out_channels,
4425                        .integer = 1,
4426                };
4427                return snd_interval_refine(c, &t);
4428        }
4429        return 0;
4430}
4431
4432static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4433                                             struct snd_pcm_hw_rule *rule)
4434{
4435        struct hdsp *hdsp = rule->private;
4436        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4437        struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4438        if (c->min >= hdsp->ss_out_channels) {
4439                struct snd_interval t = {
4440                        .min = 32000,
4441                        .max = 48000,
4442                        .integer = 1,
4443                };
4444                return snd_interval_refine(r, &t);
4445        } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4446                struct snd_interval t = {
4447                        .min = 128000,
4448                        .max = 192000,
4449                        .integer = 1,
4450                };
4451                return snd_interval_refine(r, &t);
4452        } else if (c->max <= hdsp->ds_out_channels) {
4453                struct snd_interval t = {
4454                        .min = 64000,
4455                        .max = 96000,
4456                        .integer = 1,
4457                };
4458                return snd_interval_refine(r, &t);
4459        }
4460        return 0;
4461}
4462
4463static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4464                                             struct snd_pcm_hw_rule *rule)
4465{
4466        struct hdsp *hdsp = rule->private;
4467        struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4468        struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4469        if (c->min >= hdsp->ss_in_channels) {
4470                struct snd_interval t = {
4471                        .min = 32000,
4472                        .max = 48000,
4473                        .integer = 1,
4474                };
4475                return snd_interval_refine(r, &t);
4476        } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4477                struct snd_interval t = {
4478                        .min = 128000,
4479                        .max = 192000,
4480                        .integer = 1,
4481                };
4482                return snd_interval_refine(r, &t);
4483        } else if (c->max <= hdsp->ds_in_channels) {
4484                struct snd_interval t = {
4485                        .min = 64000,
4486                        .max = 96000,
4487                        .integer = 1,
4488                };
4489                return snd_interval_refine(r, &t);
4490        }
4491        return 0;
4492}
4493
4494static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4495{
4496        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4497        struct snd_pcm_runtime *runtime = substream->runtime;
4498
4499        if (hdsp_check_for_iobox (hdsp))
4500                return -EIO;
4501
4502        if (hdsp_check_for_firmware(hdsp, 1))
4503                return -EIO;
4504
4505        spin_lock_irq(&hdsp->lock);
4506
4507        snd_pcm_set_sync(substream);
4508
4509        runtime->hw = snd_hdsp_playback_subinfo;
4510        snd_pcm_set_runtime_buffer(substream, hdsp->playback_dma_buf);
4511
4512        hdsp->playback_pid = current->pid;
4513        hdsp->playback_substream = substream;
4514
4515        spin_unlock_irq(&hdsp->lock);
4516
4517        snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4518        snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4519        if (hdsp->clock_source_locked) {
4520                runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4521        } else if (hdsp->io_type == H9632) {
4522                runtime->hw.rate_max = 192000;
4523                runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4524                snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4525        }
4526        if (hdsp->io_type == H9632) {
4527                runtime->hw.channels_min = hdsp->qs_out_channels;
4528                runtime->hw.channels_max = hdsp->ss_out_channels;
4529        }
4530
4531        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4532                             snd_hdsp_hw_rule_out_channels, hdsp,
4533                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4534        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4535                             snd_hdsp_hw_rule_out_channels_rate, hdsp,
4536                             SNDRV_PCM_HW_PARAM_RATE, -1);
4537        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4538                             snd_hdsp_hw_rule_rate_out_channels, hdsp,
4539                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4540
4541        if (RPM != hdsp->io_type) {
4542                hdsp->creg_spdif_stream = hdsp->creg_spdif;
4543                hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4544                snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4545                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4546        }
4547        return 0;
4548}
4549
4550static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4551{
4552        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4553
4554        spin_lock_irq(&hdsp->lock);
4555
4556        hdsp->playback_pid = -1;
4557        hdsp->playback_substream = NULL;
4558
4559        spin_unlock_irq(&hdsp->lock);
4560
4561        if (RPM != hdsp->io_type) {
4562                hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4563                snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4564                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4565        }
4566        return 0;
4567}
4568
4569
4570static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4571{
4572        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4573        struct snd_pcm_runtime *runtime = substream->runtime;
4574
4575        if (hdsp_check_for_iobox (hdsp))
4576                return -EIO;
4577
4578        if (hdsp_check_for_firmware(hdsp, 1))
4579                return -EIO;
4580
4581        spin_lock_irq(&hdsp->lock);
4582
4583        snd_pcm_set_sync(substream);
4584
4585        runtime->hw = snd_hdsp_capture_subinfo;
4586        snd_pcm_set_runtime_buffer(substream, hdsp->capture_dma_buf);
4587
4588        hdsp->capture_pid = current->pid;
4589        hdsp->capture_substream = substream;
4590
4591        spin_unlock_irq(&hdsp->lock);
4592
4593        snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4594        snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4595        if (hdsp->io_type == H9632) {
4596                runtime->hw.channels_min = hdsp->qs_in_channels;
4597                runtime->hw.channels_max = hdsp->ss_in_channels;
4598                runtime->hw.rate_max = 192000;
4599                runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4600                snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4601        }
4602        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4603                             snd_hdsp_hw_rule_in_channels, hdsp,
4604                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4605        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4606                             snd_hdsp_hw_rule_in_channels_rate, hdsp,
4607                             SNDRV_PCM_HW_PARAM_RATE, -1);
4608        snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4609                             snd_hdsp_hw_rule_rate_in_channels, hdsp,
4610                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4611        return 0;
4612}
4613
4614static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4615{
4616        struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4617
4618        spin_lock_irq(&hdsp->lock);
4619
4620        hdsp->capture_pid = -1;
4621        hdsp->capture_substream = NULL;
4622
4623        spin_unlock_irq(&hdsp->lock);
4624        return 0;
4625}
4626
4627/* helper functions for copying meter values */
4628static inline int copy_u32_le(void __user *dest, void __iomem *src)
4629{
4630        u32 val = readl(src);
4631        return copy_to_user(dest, &val, 4);
4632}
4633
4634static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4635{
4636        u32 rms_low, rms_high;
4637        u64 rms;
4638        rms_low = readl(src_low);
4639        rms_high = readl(src_high);
4640        rms = ((u64)rms_high << 32) | rms_low;
4641        return copy_to_user(dest, &rms, 8);
4642}
4643
4644static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4645{
4646        u32 rms_low, rms_high;
4647        u64 rms;
4648        rms_low = readl(src_low) & 0xffffff00;
4649        rms_high = readl(src_high) & 0xffffff00;
4650        rms = ((u64)rms_high << 32) | rms_low;
4651        return copy_to_user(dest, &rms, 8);
4652}
4653
4654static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4655{
4656        int doublespeed = 0;
4657        int i, j, channels, ofs;
4658
4659        if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4660                doublespeed = 1;
4661        channels = doublespeed ? 14 : 26;
4662        for (i = 0, j = 0; i < 26; ++i) {
4663                if (doublespeed && (i & 4))
4664                        continue;
4665                ofs = HDSP_9652_peakBase - j * 4;
4666                if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4667                        return -EFAULT;
4668                ofs -= channels * 4;
4669                if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4670                        return -EFAULT;
4671                ofs -= channels * 4;
4672                if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4673                        return -EFAULT;
4674                ofs = HDSP_9652_rmsBase + j * 8;
4675                if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4676                                hdsp->iobase + ofs + 4))
4677                        return -EFAULT;
4678                ofs += channels * 8;
4679                if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4680                                hdsp->iobase + ofs + 4))
4681                        return -EFAULT;
4682                ofs += channels * 8;
4683                if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4684                                hdsp->iobase + ofs + 4))
4685                        return -EFAULT;
4686                j++;
4687        }
4688        return 0;
4689}
4690
4691static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4692{
4693        int i, j;
4694        struct hdsp_9632_meters __iomem *m;
4695        int doublespeed = 0;
4696
4697        if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4698                doublespeed = 1;
4699        m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4700        for (i = 0, j = 0; i < 16; ++i, ++j) {
4701                if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4702                        return -EFAULT;
4703                if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4704                        return -EFAULT;
4705                if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4706                        return -EFAULT;
4707                if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4708                                &m->input_rms_high[j]))
4709                        return -EFAULT;
4710                if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4711                                &m->playback_rms_high[j]))
4712                        return -EFAULT;
4713                if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4714                                &m->output_rms_high[j]))
4715                        return -EFAULT;
4716                if (doublespeed && i == 3) i += 4;
4717        }
4718        return 0;
4719}
4720
4721static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4722{
4723        int i;
4724
4725        for (i = 0; i < 26; i++) {
4726                if (copy_u32_le(&peak_rms->playback_peaks[i],
4727                                hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4728                        return -EFAULT;
4729                if (copy_u32_le(&peak_rms->input_peaks[i],
4730                                hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4731                        return -EFAULT;
4732        }
4733        for (i = 0; i < 28; i++) {
4734                if (copy_u32_le(&peak_rms->output_peaks[i],
4735                                hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4736                        return -EFAULT;
4737        }
4738        for (i = 0; i < 26; ++i) {
4739                if (copy_u64_le(&peak_rms->playback_rms[i],
4740                                hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4741                                hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4742                        return -EFAULT;
4743                if (copy_u64_le(&peak_rms->input_rms[i],
4744                                hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4745                                hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4746                        return -EFAULT;
4747        }
4748        return 0;
4749}
4750
4751static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4752{
4753        struct hdsp *hdsp = hw->private_data;
4754        void __user *argp = (void __user *)arg;
4755        int err;
4756
4757        switch (cmd) {
4758        case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4759                struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4760
4761                err = hdsp_check_for_iobox(hdsp);
4762                if (err < 0)
4763                        return err;
4764
4765                err = hdsp_check_for_firmware(hdsp, 1);
4766                if (err < 0)
4767                        return err;
4768
4769                if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4770                        dev_err(hdsp->card->dev,
4771                                "firmware needs to be uploaded to the card.\n");
4772                        return -EINVAL;
4773                }
4774
4775                switch (hdsp->io_type) {
4776                case H9652:
4777                        return hdsp_9652_get_peak(hdsp, peak_rms);
4778                case H9632:
4779                        return hdsp_9632_get_peak(hdsp, peak_rms);
4780                default:
4781                        return hdsp_get_peak(hdsp, peak_rms);
4782                }
4783        }
4784        case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4785                struct hdsp_config_info info;
4786                unsigned long flags;
4787                int i;
4788
4789                err = hdsp_check_for_iobox(hdsp);
4790                if (err < 0)
4791                        return err;
4792
4793                err = hdsp_check_for_firmware(hdsp, 1);
4794                if (err < 0)
4795                        return err;
4796
4797                memset(&info, 0, sizeof(info));
4798                spin_lock_irqsave(&hdsp->lock, flags);
4799                info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4800                info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4801                if (hdsp->io_type != H9632)
4802                    info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4803                info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4804                for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4805                        info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4806                info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4807                info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4808                                HDSP_SPDIFOpticalOut);
4809                info.spdif_professional = (unsigned char)
4810                        hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4811                info.spdif_emphasis = (unsigned char)
4812                        hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4813                info.spdif_nonaudio = (unsigned char)
4814                        hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4815                info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4816                info.system_sample_rate = hdsp->system_sample_rate;
4817                info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4818                info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4819                info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4820                info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4821                info.line_out = (unsigned char)
4822                        hdsp_toggle_setting(hdsp, HDSP_LineOut);
4823                if (hdsp->io_type == H9632) {
4824                        info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4825                        info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4826                        info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4827                        info.xlr_breakout_cable =
4828                                (unsigned char)hdsp_toggle_setting(hdsp,
4829                                        HDSP_XLRBreakoutCable);
4830
4831                } else if (hdsp->io_type == RPM) {
4832                        info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4833                        info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4834                }
4835                if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4836                        info.analog_extension_board =
4837                                (unsigned char)hdsp_toggle_setting(hdsp,
4838                                            HDSP_AnalogExtensionBoard);
4839                spin_unlock_irqrestore(&hdsp->lock, flags);
4840                if (copy_to_user(argp, &info, sizeof(info)))
4841                        return -EFAULT;
4842                break;
4843        }
4844        case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4845                struct hdsp_9632_aeb h9632_aeb;
4846
4847                if (hdsp->io_type != H9632) return -EINVAL;
4848                h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4849                h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4850                if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4851                        return -EFAULT;
4852                break;
4853        }
4854        case SNDRV_HDSP_IOCTL_GET_VERSION: {
4855                struct hdsp_version hdsp_version;
4856                int err;
4857
4858                if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4859                if (hdsp->io_type == Undefined) {
4860                        err = hdsp_get_iobox_version(hdsp);
4861                        if (err < 0)
4862                                return err;
4863                }
4864                memset(&hdsp_version, 0, sizeof(hdsp_version));
4865                hdsp_version.io_type = hdsp->io_type;
4866                hdsp_version.firmware_rev = hdsp->firmware_rev;
4867                if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))
4868                        return -EFAULT;
4869                break;
4870        }
4871        case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4872                struct hdsp_firmware firmware;
4873                u32 __user *firmware_data;
4874                int err;
4875
4876                if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4877                /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4878                if (hdsp->io_type == Undefined) return -EINVAL;
4879
4880                if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4881                        return -EBUSY;
4882
4883                dev_info(hdsp->card->dev,
4884                         "initializing firmware upload\n");
4885                if (copy_from_user(&firmware, argp, sizeof(firmware)))
4886                        return -EFAULT;
4887                firmware_data = (u32 __user *)firmware.firmware_data;
4888
4889                if (hdsp_check_for_iobox (hdsp))
4890                        return -EIO;
4891
4892                if (!hdsp->fw_uploaded) {
4893                        hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4894                        if (!hdsp->fw_uploaded)
4895                                return -ENOMEM;
4896                }
4897
4898                if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4899                                   HDSP_FIRMWARE_SIZE)) {
4900                        vfree(hdsp->fw_uploaded);
4901                        hdsp->fw_uploaded = NULL;
4902                        return -EFAULT;
4903                }
4904
4905                hdsp->state |= HDSP_FirmwareCached;
4906
4907                err = snd_hdsp_load_firmware_from_cache(hdsp);
4908                if (err < 0)
4909                        return err;
4910
4911                if (!(hdsp->state & HDSP_InitializationComplete)) {
4912                        err = snd_hdsp_enable_io(hdsp);
4913                        if (err < 0)
4914                                return err;
4915
4916                        snd_hdsp_initialize_channels(hdsp);
4917                        snd_hdsp_initialize_midi_flush(hdsp);
4918
4919                        err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
4920                        if (err < 0) {
4921                                dev_err(hdsp->card->dev,
4922                                        "error creating alsa devices\n");
4923                                return err;
4924                        }
4925                }
4926                break;
4927        }
4928        case SNDRV_HDSP_IOCTL_GET_MIXER: {
4929                struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4930                if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4931                        return -EFAULT;
4932                break;
4933        }
4934        default:
4935                return -EINVAL;
4936        }
4937        return 0;
4938}
4939
4940static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4941        .open =         snd_hdsp_playback_open,
4942        .close =        snd_hdsp_playback_release,
4943        .ioctl =        snd_hdsp_ioctl,
4944        .hw_params =    snd_hdsp_hw_params,
4945        .prepare =      snd_hdsp_prepare,
4946        .trigger =      snd_hdsp_trigger,
4947        .pointer =      snd_hdsp_hw_pointer,
4948        .copy_user =    snd_hdsp_playback_copy,
4949        .copy_kernel =  snd_hdsp_playback_copy_kernel,
4950        .fill_silence = snd_hdsp_hw_silence,
4951};
4952
4953static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4954        .open =         snd_hdsp_capture_open,
4955        .close =        snd_hdsp_capture_release,
4956        .ioctl =        snd_hdsp_ioctl,
4957        .hw_params =    snd_hdsp_hw_params,
4958        .prepare =      snd_hdsp_prepare,
4959        .trigger =      snd_hdsp_trigger,
4960        .pointer =      snd_hdsp_hw_pointer,
4961        .copy_user =    snd_hdsp_capture_copy,
4962        .copy_kernel =  snd_hdsp_capture_copy_kernel,
4963};
4964
4965static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4966{
4967        struct snd_hwdep *hw;
4968        int err;
4969
4970        err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);
4971        if (err < 0)
4972                return err;
4973
4974        hdsp->hwdep = hw;
4975        hw->private_data = hdsp;
4976        strcpy(hw->name, "HDSP hwdep interface");
4977
4978        hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4979        hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4980
4981        return 0;
4982}
4983
4984static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4985{
4986        struct snd_pcm *pcm;
4987        int err;
4988
4989        err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);
4990        if (err < 0)
4991                return err;
4992
4993        hdsp->pcm = pcm;
4994        pcm->private_data = hdsp;
4995        strcpy(pcm->name, hdsp->card_name);
4996
4997        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4998        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4999
5000        pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
5001
5002        return 0;
5003}
5004
5005static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
5006{
5007        hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
5008        hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5009}
5010
5011static int snd_hdsp_enable_io (struct hdsp *hdsp)
5012{
5013        int i;
5014
5015        if (hdsp_fifo_wait (hdsp, 0, 100)) {
5016                dev_err(hdsp->card->dev,
5017                        "enable_io fifo_wait failed\n");
5018                return -EIO;
5019        }
5020
5021        for (i = 0; i < hdsp->max_channels; ++i) {
5022                hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5023                hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5024        }
5025
5026        return 0;
5027}
5028
5029static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5030{
5031        int status, aebi_channels, aebo_channels, i;
5032
5033        switch (hdsp->io_type) {
5034        case Digiface:
5035                hdsp->card_name = "RME Hammerfall DSP + Digiface";
5036                hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5037                hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5038                break;
5039
5040        case H9652:
5041                hdsp->card_name = "RME Hammerfall HDSP 9652";
5042                hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5043                hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5044                break;
5045
5046        case H9632:
5047                status = hdsp_read(hdsp, HDSP_statusRegister);
5048                /* HDSP_AEBx bits are low when AEB are connected */
5049                aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5050                aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5051                hdsp->card_name = "RME Hammerfall HDSP 9632";
5052                hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5053                hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5054                hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5055                hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5056                hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5057                hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5058                /* Disable loopback of output channels, as the set function
5059                 * only sets on a change we fake all bits (channels) as enabled.
5060                 */
5061                hdsp->io_loopback = 0xffffffff;
5062                for (i = 0; i < hdsp->max_channels; ++i)
5063                        hdsp_loopback_set(hdsp, i, false);
5064                break;
5065
5066        case Multiface:
5067                hdsp->card_name = "RME Hammerfall DSP + Multiface";
5068                hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5069                hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5070                break;
5071
5072        case RPM:
5073                hdsp->card_name = "RME Hammerfall DSP + RPM";
5074                hdsp->ss_in_channels = RPM_CHANNELS-1;
5075                hdsp->ss_out_channels = RPM_CHANNELS;
5076                hdsp->ds_in_channels = RPM_CHANNELS-1;
5077                hdsp->ds_out_channels = RPM_CHANNELS;
5078                break;
5079
5080        default:
5081                /* should never get here */
5082                break;
5083        }
5084}
5085
5086static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5087{
5088        snd_hdsp_flush_midi_input (hdsp, 0);
5089        snd_hdsp_flush_midi_input (hdsp, 1);
5090}
5091
5092static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5093{
5094        int err;
5095
5096        err = snd_hdsp_create_pcm(card, hdsp);
5097        if (err < 0) {
5098                dev_err(card->dev,
5099                        "Error creating pcm interface\n");
5100                return err;
5101        }
5102
5103
5104        err = snd_hdsp_create_midi(card, hdsp, 0);
5105        if (err < 0) {
5106                dev_err(card->dev,
5107                        "Error creating first midi interface\n");
5108                return err;
5109        }
5110
5111        if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5112                err = snd_hdsp_create_midi(card, hdsp, 1);
5113                if (err < 0) {
5114                        dev_err(card->dev,
5115                                "Error creating second midi interface\n");
5116                        return err;
5117                }
5118        }
5119
5120        err = snd_hdsp_create_controls(card, hdsp);
5121        if (err < 0) {
5122                dev_err(card->dev,
5123                        "Error creating ctl interface\n");
5124                return err;
5125        }
5126
5127        snd_hdsp_proc_init(hdsp);
5128
5129        hdsp->system_sample_rate = -1;
5130        hdsp->playback_pid = -1;
5131        hdsp->capture_pid = -1;
5132        hdsp->capture_substream = NULL;
5133        hdsp->playback_substream = NULL;
5134
5135        err = snd_hdsp_set_defaults(hdsp);
5136        if (err < 0) {
5137                dev_err(card->dev,
5138                        "Error setting default values\n");
5139                return err;
5140        }
5141
5142        if (!(hdsp->state & HDSP_InitializationComplete)) {
5143                strcpy(card->shortname, "Hammerfall DSP");
5144                sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5145                        hdsp->port, hdsp->irq);
5146
5147                err = snd_card_register(card);
5148                if (err < 0) {
5149                        dev_err(card->dev,
5150                                "error registering card\n");
5151                        return err;
5152                }
5153                hdsp->state |= HDSP_InitializationComplete;
5154        }
5155
5156        return 0;
5157}
5158
5159/* load firmware via hotplug fw loader */
5160static int hdsp_request_fw_loader(struct hdsp *hdsp)
5161{
5162        const char *fwfile;
5163        const struct firmware *fw;
5164        int err;
5165
5166        if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5167                return 0;
5168        if (hdsp->io_type == Undefined) {
5169                err = hdsp_get_iobox_version(hdsp);
5170                if (err < 0)
5171                        return err;
5172                if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5173                        return 0;
5174        }
5175
5176        /* caution: max length of firmware filename is 30! */
5177        switch (hdsp->io_type) {
5178        case RPM:
5179                fwfile = "rpm_firmware.bin";
5180                break;
5181        case Multiface:
5182                if (hdsp->firmware_rev == 0xa)
5183                        fwfile = "multiface_firmware.bin";
5184                else
5185                        fwfile = "multiface_firmware_rev11.bin";
5186                break;
5187        case Digiface:
5188                if (hdsp->firmware_rev == 0xa)
5189                        fwfile = "digiface_firmware.bin";
5190                else
5191                        fwfile = "digiface_firmware_rev11.bin";
5192                break;
5193        default:
5194                dev_err(hdsp->card->dev,
5195                        "invalid io_type %d\n", hdsp->io_type);
5196                return -EINVAL;
5197        }
5198
5199        if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5200                dev_err(hdsp->card->dev,
5201                        "cannot load firmware %s\n", fwfile);
5202                return -ENOENT;
5203        }
5204        if (fw->size < HDSP_FIRMWARE_SIZE) {
5205                dev_err(hdsp->card->dev,
5206                        "too short firmware size %d (expected %d)\n",
5207                           (int)fw->size, HDSP_FIRMWARE_SIZE);
5208                release_firmware(fw);
5209                return -EINVAL;
5210        }
5211
5212        hdsp->firmware = fw;
5213
5214        hdsp->state |= HDSP_FirmwareCached;
5215
5216        err = snd_hdsp_load_firmware_from_cache(hdsp);
5217        if (err < 0)
5218                return err;
5219
5220        if (!(hdsp->state & HDSP_InitializationComplete)) {
5221                err = snd_hdsp_enable_io(hdsp);
5222                if (err < 0)
5223                        return err;
5224
5225                err = snd_hdsp_create_hwdep(hdsp->card, hdsp);
5226                if (err < 0) {
5227                        dev_err(hdsp->card->dev,
5228                                "error creating hwdep device\n");
5229                        return err;
5230                }
5231                snd_hdsp_initialize_channels(hdsp);
5232                snd_hdsp_initialize_midi_flush(hdsp);
5233                err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
5234                if (err < 0) {
5235                        dev_err(hdsp->card->dev,
5236                                "error creating alsa devices\n");
5237                        return err;
5238                }
5239        }
5240        return 0;
5241}
5242
5243static int snd_hdsp_create(struct snd_card *card,
5244                           struct hdsp *hdsp)
5245{
5246        struct pci_dev *pci = hdsp->pci;
5247        int err;
5248        int is_9652 = 0;
5249        int is_9632 = 0;
5250
5251        hdsp->irq = -1;
5252        hdsp->state = 0;
5253        hdsp->midi[0].rmidi = NULL;
5254        hdsp->midi[1].rmidi = NULL;
5255        hdsp->midi[0].input = NULL;
5256        hdsp->midi[1].input = NULL;
5257        hdsp->midi[0].output = NULL;
5258        hdsp->midi[1].output = NULL;
5259        hdsp->midi[0].pending = 0;
5260        hdsp->midi[1].pending = 0;
5261        spin_lock_init(&hdsp->midi[0].lock);
5262        spin_lock_init(&hdsp->midi[1].lock);
5263        hdsp->iobase = NULL;
5264        hdsp->control_register = 0;
5265        hdsp->control2_register = 0;
5266        hdsp->io_type = Undefined;
5267        hdsp->max_channels = 26;
5268
5269        hdsp->card = card;
5270
5271        spin_lock_init(&hdsp->lock);
5272
5273        INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5274
5275        pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5276        hdsp->firmware_rev &= 0xff;
5277
5278        /* From Martin Bjoernsen :
5279            "It is important that the card's latency timer register in
5280            the PCI configuration space is set to a value much larger
5281            than 0 by the computer's BIOS or the driver.
5282            The windows driver always sets this 8 bit register [...]
5283            to its maximum 255 to avoid problems with some computers."
5284        */
5285        pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5286
5287        strcpy(card->driver, "H-DSP");
5288        strcpy(card->mixername, "Xilinx FPGA");
5289
5290        if (hdsp->firmware_rev < 0xa)
5291                return -ENODEV;
5292        else if (hdsp->firmware_rev < 0x64)
5293                hdsp->card_name = "RME Hammerfall DSP";
5294        else if (hdsp->firmware_rev < 0x96) {
5295                hdsp->card_name = "RME HDSP 9652";
5296                is_9652 = 1;
5297        } else {
5298                hdsp->card_name = "RME HDSP 9632";
5299                hdsp->max_channels = 16;
5300                is_9632 = 1;
5301        }
5302
5303        err = pcim_enable_device(pci);
5304        if (err < 0)
5305                return err;
5306
5307        pci_set_master(hdsp->pci);
5308
5309        err = pci_request_regions(pci, "hdsp");
5310        if (err < 0)
5311                return err;
5312        hdsp->port = pci_resource_start(pci, 0);
5313        hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);
5314        if (!hdsp->iobase) {
5315                dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5316                        hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5317                return -EBUSY;
5318        }
5319
5320        if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,
5321                             IRQF_SHARED, KBUILD_MODNAME, hdsp)) {
5322                dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5323                return -EBUSY;
5324        }
5325
5326        hdsp->irq = pci->irq;
5327        card->sync_irq = hdsp->irq;
5328        hdsp->precise_ptr = 0;
5329        hdsp->use_midi_work = 1;
5330        hdsp->dds_value = 0;
5331
5332        err = snd_hdsp_initialize_memory(hdsp);
5333        if (err < 0)
5334                return err;
5335
5336        if (!is_9652 && !is_9632) {
5337                /* we wait a maximum of 10 seconds to let freshly
5338                 * inserted cardbus cards do their hardware init */
5339                err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5340
5341                if (err < 0)
5342                        return err;
5343
5344                if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5345                        err = hdsp_request_fw_loader(hdsp);
5346                        if (err < 0)
5347                                /* we don't fail as this can happen
5348                                   if userspace is not ready for
5349                                   firmware upload
5350                                */
5351                                dev_err(hdsp->card->dev,
5352                                        "couldn't get firmware from userspace. try using hdsploader\n");
5353                        else
5354                                /* init is complete, we return */
5355                                return 0;
5356                        /* we defer initialization */
5357                        dev_info(hdsp->card->dev,
5358                                 "card initialization pending : waiting for firmware\n");
5359                        err = snd_hdsp_create_hwdep(card, hdsp);
5360                        if (err < 0)
5361                                return err;
5362                        return 0;
5363                } else {
5364                        dev_info(hdsp->card->dev,
5365                                 "Firmware already present, initializing card.\n");
5366                        if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5367                                hdsp->io_type = RPM;
5368                        else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5369                                hdsp->io_type = Multiface;
5370                        else
5371                                hdsp->io_type = Digiface;
5372                }
5373        }
5374
5375        err = snd_hdsp_enable_io(hdsp);
5376        if (err)
5377                return err;
5378
5379        if (is_9652)
5380                hdsp->io_type = H9652;
5381
5382        if (is_9632)
5383                hdsp->io_type = H9632;
5384
5