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9
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/firmware.h>
13#include <linux/mutex.h>
14#include <linux/io.h>
15
16#include <sound/core.h>
17#include <sound/control.h>
18#include <sound/tlv.h>
19#include "vx222.h"
20
21
22static const int vx2_reg_offset[VX_REG_MAX] = {
23 [VX_ICR] = 0x00,
24 [VX_CVR] = 0x04,
25 [VX_ISR] = 0x08,
26 [VX_IVR] = 0x0c,
27 [VX_RXH] = 0x14,
28 [VX_RXM] = 0x18,
29 [VX_RXL] = 0x1c,
30 [VX_DMA] = 0x10,
31 [VX_CDSP] = 0x20,
32 [VX_CFG] = 0x24,
33 [VX_RUER] = 0x28,
34 [VX_DATA] = 0x2c,
35 [VX_STATUS] = 0x30,
36 [VX_LOFREQ] = 0x34,
37 [VX_HIFREQ] = 0x38,
38 [VX_CSUER] = 0x3c,
39 [VX_SELMIC] = 0x40,
40 [VX_COMPOT] = 0x44,
41 [VX_SCOMPR] = 0x48,
42 [VX_GLIMIT] = 0x4c,
43 [VX_INTCSR] = 0x4c,
44 [VX_CNTRL] = 0x50,
45 [VX_GPIOC] = 0x54,
46};
47
48static const int vx2_reg_index[VX_REG_MAX] = {
49 [VX_ICR] = 1,
50 [VX_CVR] = 1,
51 [VX_ISR] = 1,
52 [VX_IVR] = 1,
53 [VX_RXH] = 1,
54 [VX_RXM] = 1,
55 [VX_RXL] = 1,
56 [VX_DMA] = 1,
57 [VX_CDSP] = 1,
58 [VX_CFG] = 1,
59 [VX_RUER] = 1,
60 [VX_DATA] = 1,
61 [VX_STATUS] = 1,
62 [VX_LOFREQ] = 1,
63 [VX_HIFREQ] = 1,
64 [VX_CSUER] = 1,
65 [VX_SELMIC] = 1,
66 [VX_COMPOT] = 1,
67 [VX_SCOMPR] = 1,
68 [VX_GLIMIT] = 1,
69 [VX_INTCSR] = 0,
70 [VX_CNTRL] = 0,
71 [VX_GPIOC] = 0,
72};
73
74static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg)
75{
76 struct snd_vx222 *chip = to_vx222(_chip);
77 return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
78}
79
80
81
82
83
84
85static unsigned char vx2_inb(struct vx_core *chip, int offset)
86{
87 return inb(vx2_reg_addr(chip, offset));
88}
89
90
91
92
93
94
95
96static void vx2_outb(struct vx_core *chip, int offset, unsigned char val)
97{
98 outb(val, vx2_reg_addr(chip, offset));
99
100
101
102}
103
104
105
106
107
108
109static unsigned int vx2_inl(struct vx_core *chip, int offset)
110{
111 return inl(vx2_reg_addr(chip, offset));
112}
113
114
115
116
117
118
119
120static void vx2_outl(struct vx_core *chip, int offset, unsigned int val)
121{
122
123
124
125 outl(val, vx2_reg_addr(chip, offset));
126}
127
128
129
130
131#undef vx_inb
132#define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg)
133#undef vx_outb
134#define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val)
135#undef vx_inl
136#define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg)
137#undef vx_outl
138#define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val)
139
140
141
142
143
144
145#define XX_DSP_RESET_WAIT_TIME 2
146
147static void vx2_reset_dsp(struct vx_core *_chip)
148{
149 struct snd_vx222 *chip = to_vx222(_chip);
150
151
152 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
153
154 mdelay(XX_DSP_RESET_WAIT_TIME);
155
156 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
157
158 vx_outl(chip, CDSP, chip->regCDSP);
159}
160
161
162static int vx2_test_xilinx(struct vx_core *_chip)
163{
164 struct snd_vx222 *chip = to_vx222(_chip);
165 unsigned int data;
166
167 dev_dbg(_chip->card->dev, "testing xilinx...\n");
168
169
170
171
172
173 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
174 vx_inl(chip, ISR);
175 data = vx_inl(chip, STATUS);
176 if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
177 dev_dbg(_chip->card->dev, "bad!\n");
178 return -ENODEV;
179 }
180
181
182 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
183 vx_inl(chip, ISR);
184 data = vx_inl(chip, STATUS);
185 if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
186 dev_dbg(_chip->card->dev, "bad! #2\n");
187 return -ENODEV;
188 }
189
190 if (_chip->type == VX_TYPE_BOARD) {
191
192
193 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
194 vx_inl(chip, ISR);
195 data = vx_inl(chip, STATUS);
196 if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
197 dev_dbg(_chip->card->dev, "bad! #3\n");
198 return -ENODEV;
199 }
200
201
202 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
203 vx_inl(chip, ISR);
204 data = vx_inl(chip, STATUS);
205 if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
206 dev_dbg(_chip->card->dev, "bad! #4\n");
207 return -ENODEV;
208 }
209 }
210 dev_dbg(_chip->card->dev, "ok, xilinx fine.\n");
211 return 0;
212}
213
214
215
216
217
218
219
220static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
221{
222
223
224
225 vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
226
227
228
229
230 vx_outl(chip, RESET_DMA, 0);
231}
232
233
234
235
236static inline void vx2_release_pseudo_dma(struct vx_core *chip)
237{
238
239 vx_outl(chip, ICR, 0);
240}
241
242
243
244
245static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
246 struct vx_pipe *pipe, int count)
247{
248 unsigned long port = vx2_reg_addr(chip, VX_DMA);
249 int offset = pipe->hw_ptr;
250 u32 *addr = (u32 *)(runtime->dma_area + offset);
251
252 if (snd_BUG_ON(count % 4))
253 return;
254
255 vx2_setup_pseudo_dma(chip, 1);
256
257
258
259 if (offset + count >= pipe->buffer_bytes) {
260 int length = pipe->buffer_bytes - offset;
261 count -= length;
262 length >>= 2;
263
264 for (; length > 0; length--) {
265 outl(*addr, port);
266 addr++;
267 }
268 addr = (u32 *)runtime->dma_area;
269 pipe->hw_ptr = 0;
270 }
271 pipe->hw_ptr += count;
272 count >>= 2;
273
274 for (; count > 0; count--) {
275 outl(*addr, port);
276 addr++;
277 }
278
279 vx2_release_pseudo_dma(chip);
280}
281
282
283
284static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
285 struct vx_pipe *pipe, int count)
286{
287 int offset = pipe->hw_ptr;
288 u32 *addr = (u32 *)(runtime->dma_area + offset);
289 unsigned long port = vx2_reg_addr(chip, VX_DMA);
290
291 if (snd_BUG_ON(count % 4))
292 return;
293
294 vx2_setup_pseudo_dma(chip, 0);
295
296
297 if (offset + count >= pipe->buffer_bytes) {
298 int length = pipe->buffer_bytes - offset;
299 count -= length;
300 length >>= 2;
301
302 for (; length > 0; length--)
303 *addr++ = inl(port);
304 addr = (u32 *)runtime->dma_area;
305 pipe->hw_ptr = 0;
306 }
307 pipe->hw_ptr += count;
308 count >>= 2;
309
310 for (; count > 0; count--)
311 *addr++ = inl(port);
312
313 vx2_release_pseudo_dma(chip);
314}
315
316#define VX_XILINX_RESET_MASK 0x40000000
317#define VX_USERBIT0_MASK 0x00000004
318#define VX_USERBIT1_MASK 0x00000020
319#define VX_CNTRL_REGISTER_VALUE 0x00172012
320
321
322
323
324static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data)
325{
326 unsigned int i;
327
328 for (i = 0; i < counts; i++) {
329 unsigned int val;
330
331
332 val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK;
333 vx2_outl(chip, port, val);
334 vx2_inl(chip, port);
335 udelay(1);
336
337 if (data & (1 << i))
338 val |= VX_USERBIT1_MASK;
339 else
340 val &= ~VX_USERBIT1_MASK;
341 vx2_outl(chip, port, val);
342 vx2_inl(chip, port);
343
344
345 val |= VX_USERBIT0_MASK;
346 vx2_outl(chip, port, val);
347 vx2_inl(chip, port);
348 udelay(1);
349 }
350 return 0;
351}
352
353
354
355
356static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx)
357{
358 unsigned int i;
359 unsigned int port;
360 const unsigned char *image;
361
362
363 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
364 vx_inl(chip, CNTRL);
365 msleep(10);
366 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
367 vx_inl(chip, CNTRL);
368 msleep(10);
369
370 if (chip->type == VX_TYPE_BOARD)
371 port = VX_CNTRL;
372 else
373 port = VX_GPIOC;
374
375 image = xilinx->data;
376 for (i = 0; i < xilinx->size; i++, image++) {
377 if (put_xilinx_data(chip, port, 8, *image) < 0)
378 return -EINVAL;
379
380 cond_resched();
381 }
382 put_xilinx_data(chip, port, 4, 0xff);
383
384 msleep(200);
385
386
387 if (chip->type != VX_TYPE_BOARD) {
388
389 i = vx_inl(chip, GPIOC);
390 if (i & 0x0100)
391 return 0;
392 dev_err(chip->card->dev,
393 "xilinx test failed after load, GPIOC=0x%x\n", i);
394 return -EINVAL;
395 }
396
397 return 0;
398}
399
400
401
402
403
404static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp)
405{
406 int err;
407
408 switch (index) {
409 case 1:
410
411 err = vx2_load_xilinx_binary(vx, dsp);
412 if (err < 0)
413 return err;
414 err = vx2_test_xilinx(vx);
415 if (err < 0)
416 return err;
417 return 0;
418 case 2:
419
420 return snd_vx_dsp_boot(vx, dsp);
421 case 3:
422
423 return snd_vx_dsp_load(vx, dsp);
424 default:
425 snd_BUG();
426 return -EINVAL;
427 }
428}
429
430
431
432
433
434
435
436
437
438static int vx2_test_and_ack(struct vx_core *chip)
439{
440
441 if (! (chip->chip_status & VX_STAT_XILINX_LOADED))
442 return -ENXIO;
443
444 if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK))
445 return -EIO;
446
447
448
449 vx_outl(chip, STATUS, 0);
450
451
452
453 vx_inl(chip, STATUS);
454
455 vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
456
457
458 vx_inl(chip, STATUS);
459
460 vx_outl(chip, STATUS, 0);
461
462 return 0;
463}
464
465
466
467
468
469static void vx2_validate_irq(struct vx_core *_chip, int enable)
470{
471 struct snd_vx222 *chip = to_vx222(_chip);
472
473
474 if (enable) {
475
476 vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
477 chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK;
478 } else {
479
480 vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
481 chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK;
482 }
483 vx_outl(chip, CDSP, chip->regCDSP);
484}
485
486
487
488
489
490static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data)
491{
492 unsigned int i;
493
494 vx_inl(chip, HIFREQ);
495
496
497 for (i = 0; i < 24; i++, data <<= 1)
498 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
499
500 vx_inl(chip, RUER);
501}
502
503
504#define AKM_CODEC_POWER_CONTROL_CMD 0xA007
505#define AKM_CODEC_RESET_ON_CMD 0xA100
506#define AKM_CODEC_RESET_OFF_CMD 0xA103
507#define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240
508#define AKM_CODEC_MUTE_CMD 0xA38D
509#define AKM_CODEC_UNMUTE_CMD 0xA30D
510#define AKM_CODEC_LEFT_LEVEL_CMD 0xA400
511#define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500
512
513static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = {
514 0x7f,
515 0x7d,
516 0x7c,
517 0x7a,
518 0x79,
519 0x77,
520 0x76,
521 0x75,
522 0x73,
523 0x72,
524 0x71,
525 0x70,
526 0x6f,
527 0x6d,
528 0x6c,
529 0x6a,
530 0x69,
531 0x67,
532 0x66,
533 0x65,
534 0x64,
535 0x62,
536 0x61,
537 0x60,
538 0x5f,
539 0x5e,
540 0x5c,
541 0x5b,
542 0x59,
543 0x58,
544 0x56,
545 0x55,
546 0x54,
547 0x53,
548 0x52,
549 0x51,
550 0x50,
551 0x4e,
552 0x4d,
553 0x4b,
554 0x4a,
555 0x48,
556 0x47,
557 0x46,
558 0x44,
559 0x43,
560 0x42,
561 0x41,
562 0x40,
563 0x3f,
564 0x3e,
565 0x3c,
566 0x3b,
567 0x39,
568 0x38,
569 0x37,
570 0x36,
571 0x34,
572 0x33,
573 0x32,
574 0x31,
575 0x31,
576 0x30,
577 0x2e,
578 0x2d,
579 0x2b,
580 0x2a,
581 0x29,
582 0x28,
583 0x27,
584 0x25,
585 0x24,
586 0x24,
587 0x23,
588 0x22,
589 0x21,
590 0x20,
591 0x1f,
592 0x1e,
593 0x1d,
594 0x1c,
595 0x1b,
596 0x1a,
597 0x19,
598 0x18,
599 0x17,
600 0x16,
601 0x15,
602 0x14,
603 0x14,
604 0x13,
605 0x12,
606 0x12,
607 0x11,
608 0x11,
609 0x10,
610 0x10,
611 0x0f,
612 0x0e,
613 0x0d,
614 0x0d,
615 0x0c,
616 0x0b,
617 0x0b,
618 0x0a,
619 0x0a,
620 0x09,
621 0x09,
622 0x08,
623 0x08,
624 0x07,
625 0x07,
626 0x06,
627 0x06,
628 0x06,
629 0x05,
630 0x05,
631 0x05,
632 0x05,
633 0x04,
634 0x04,
635 0x04,
636 0x04,
637 0x03,
638 0x03,
639 0x03,
640 0x03,
641 0x03,
642 0x03,
643 0x02,
644 0x02,
645 0x02,
646 0x02,
647 0x02,
648 0x02,
649 0x02,
650 0x02,
651 0x02,
652 0x02,
653 0x01,
654 0x01,
655 0x01,
656 0x01,
657 0x01,
658 0x01,
659 0x01,
660 0x01,
661 0x00};
662
663
664
665
666static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data)
667{
668 unsigned int val;
669
670 if (reg == XX_CODEC_DAC_CONTROL_REGISTER) {
671 vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD);
672 return;
673 }
674
675
676
677
678
679 if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut)))
680 return;
681
682 switch (reg) {
683 case XX_CODEC_LEVEL_LEFT_REGISTER:
684 val = AKM_CODEC_LEFT_LEVEL_CMD;
685 break;
686 case XX_CODEC_LEVEL_RIGHT_REGISTER:
687 val = AKM_CODEC_RIGHT_LEVEL_CMD;
688 break;
689 default:
690 snd_BUG();
691 return;
692 }
693 val |= vx2_akm_gains_lut[data];
694
695 vx2_write_codec_reg(chip, val);
696}
697
698
699
700
701
702static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data)
703{
704 int i;
705
706
707 vx_inl(chip, HIFREQ);
708
709 for (i = 0; i < 24; i++, data <<= 1)
710 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
711
712
713 vx_inl(chip, RUER);
714}
715
716
717
718
719
720static void vx2_reset_codec(struct vx_core *_chip)
721{
722 struct snd_vx222 *chip = to_vx222(_chip);
723
724
725 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
726 vx_inl(chip, CDSP);
727 msleep(10);
728
729 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
730 vx_outl(chip, CDSP, chip->regCDSP);
731 vx_inl(chip, CDSP);
732 if (_chip->type == VX_TYPE_BOARD) {
733 msleep(1);
734 return;
735 }
736
737 msleep(5);
738
739 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD);
740
741 vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD);
742 vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD);
743 vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD);
744
745 if (_chip->type == VX_TYPE_MIC) {
746
747 chip->regSELMIC = MICRO_SELECT_INPUT_NORM |
748 MICRO_SELECT_PREAMPLI_G_0 |
749 MICRO_SELECT_NOISE_T_52DB;
750
751
752 chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM;
753
754 vx_outl(_chip, SELMIC, chip->regSELMIC);
755 }
756}
757
758
759
760
761
762static void vx2_change_audio_source(struct vx_core *_chip, int src)
763{
764 struct snd_vx222 *chip = to_vx222(_chip);
765
766 switch (src) {
767 case VX_AUDIO_SRC_DIGITAL:
768 chip->regCFG |= VX_CFG_DATAIN_SEL_MASK;
769 break;
770 default:
771 chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK;
772 break;
773 }
774 vx_outl(chip, CFG, chip->regCFG);
775}
776
777
778
779
780
781static void vx2_set_clock_source(struct vx_core *_chip, int source)
782{
783 struct snd_vx222 *chip = to_vx222(_chip);
784
785 if (source == INTERNAL_QUARTZ)
786 chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK;
787 else
788 chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK;
789 vx_outl(chip, CFG, chip->regCFG);
790}
791
792
793
794
795static void vx2_reset_board(struct vx_core *_chip, int cold_reset)
796{
797 struct snd_vx222 *chip = to_vx222(_chip);
798
799
800 chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ;
801 chip->regCFG = 0;
802}
803
804
805
806
807
808
809
810
811
812
813
814#define V2_MICRO_LEVEL_RANGE (318 - 255)
815
816static void vx2_set_input_level(struct snd_vx222 *chip)
817{
818 int i, miclevel, preamp;
819 unsigned int data;
820
821 miclevel = chip->mic_level;
822 miclevel += V2_MICRO_LEVEL_RANGE;
823 preamp = 0;
824 while (miclevel > 210) {
825 preamp++;
826 miclevel -= (18 * 2);
827 }
828 if (snd_BUG_ON(preamp >= 4))
829 return;
830
831
832 chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK;
833 chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK;
834 vx_outl(chip, SELMIC, chip->regSELMIC);
835
836 data = (unsigned int)miclevel << 16 |
837 (unsigned int)chip->input_level[1] << 8 |
838 (unsigned int)chip->input_level[0];
839 vx_inl(chip, DATA);
840
841
842 for (i = 0; i < 32; i++, data <<= 1)
843 vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));
844
845 vx_inl(chip, RUER);
846}
847
848
849#define MIC_LEVEL_MAX 0xff
850
851static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0);
852
853
854
855
856
857
858static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
859{
860 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
861 uinfo->count = 2;
862 uinfo->value.integer.min = 0;
863 uinfo->value.integer.max = MIC_LEVEL_MAX;
864 return 0;
865}
866
867static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
868{
869 struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
870 struct snd_vx222 *chip = to_vx222(_chip);
871 mutex_lock(&_chip->mixer_mutex);
872 ucontrol->value.integer.value[0] = chip->input_level[0];
873 ucontrol->value.integer.value[1] = chip->input_level[1];
874 mutex_unlock(&_chip->mixer_mutex);
875 return 0;
876}
877
878static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
879{
880 struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
881 struct snd_vx222 *chip = to_vx222(_chip);
882 if (ucontrol->value.integer.value[0] < 0 ||
883 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
884 return -EINVAL;
885 if (ucontrol->value.integer.value[1] < 0 ||
886 ucontrol->value.integer.value[1] > MIC_LEVEL_MAX)
887 return -EINVAL;
888 mutex_lock(&_chip->mixer_mutex);
889 if (chip->input_level[0] != ucontrol->value.integer.value[0] ||
890 chip->input_level[1] != ucontrol->value.integer.value[1]) {
891 chip->input_level[0] = ucontrol->value.integer.value[0];
892 chip->input_level[1] = ucontrol->value.integer.value[1];
893 vx2_set_input_level(chip);
894 mutex_unlock(&_chip->mixer_mutex);
895 return 1;
896 }
897 mutex_unlock(&_chip->mixer_mutex);
898 return 0;
899}
900
901
902static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
903{
904 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
905 uinfo->count = 1;
906 uinfo->value.integer.min = 0;
907 uinfo->value.integer.max = MIC_LEVEL_MAX;
908 return 0;
909}
910
911static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
912{
913 struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
914 struct snd_vx222 *chip = to_vx222(_chip);
915 ucontrol->value.integer.value[0] = chip->mic_level;
916 return 0;
917}
918
919static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
920{
921 struct vx_core *_chip = snd_kcontrol_chip(kcontrol);
922 struct snd_vx222 *chip = to_vx222(_chip);
923 if (ucontrol->value.integer.value[0] < 0 ||
924 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX)
925 return -EINVAL;
926 mutex_lock(&_chip->mixer_mutex);
927 if (chip->mic_level != ucontrol->value.integer.value[0]) {
928 chip->mic_level = ucontrol->value.integer.value[0];
929 vx2_set_input_level(chip);
930 mutex_unlock(&_chip->mixer_mutex);
931 return 1;
932 }
933 mutex_unlock(&_chip->mixer_mutex);
934 return 0;
935}
936
937static const struct snd_kcontrol_new vx_control_input_level = {
938 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
939 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
940 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
941 .name = "Capture Volume",
942 .info = vx_input_level_info,
943 .get = vx_input_level_get,
944 .put = vx_input_level_put,
945 .tlv = { .p = db_scale_mic },
946};
947
948static const struct snd_kcontrol_new vx_control_mic_level = {
949 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
950 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
951 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
952 .name = "Mic Capture Volume",
953 .info = vx_mic_level_info,
954 .get = vx_mic_level_get,
955 .put = vx_mic_level_put,
956 .tlv = { .p = db_scale_mic },
957};
958
959
960
961
962
963static int vx2_add_mic_controls(struct vx_core *_chip)
964{
965 struct snd_vx222 *chip = to_vx222(_chip);
966 int err;
967
968 if (_chip->type != VX_TYPE_MIC)
969 return 0;
970
971
972 chip->input_level[0] = chip->input_level[1] = 0;
973 chip->mic_level = 0;
974 vx2_set_input_level(chip);
975
976
977 err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip));
978 if (err < 0)
979 return err;
980 err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip));
981 if (err < 0)
982 return err;
983
984 return 0;
985}
986
987
988
989
990
991const struct snd_vx_ops vx222_ops = {
992 .in8 = vx2_inb,
993 .in32 = vx2_inl,
994 .out8 = vx2_outb,
995 .out32 = vx2_outl,
996 .test_and_ack = vx2_test_and_ack,
997 .validate_irq = vx2_validate_irq,
998 .akm_write = vx2_write_akm,
999 .reset_codec = vx2_reset_codec,
1000 .change_audio_source = vx2_change_audio_source,
1001 .set_clock_source = vx2_set_clock_source,
1002 .load_dsp = vx2_load_dsp,
1003 .reset_dsp = vx2_reset_dsp,
1004 .reset_board = vx2_reset_board,
1005 .dma_write = vx2_dma_write,
1006 .dma_read = vx2_dma_read,
1007 .add_controls = vx2_add_mic_controls,
1008};
1009
1010
1011const struct snd_vx_ops vx222_old_ops = {
1012 .in8 = vx2_inb,
1013 .in32 = vx2_inl,
1014 .out8 = vx2_outb,
1015 .out32 = vx2_outl,
1016 .test_and_ack = vx2_test_and_ack,
1017 .validate_irq = vx2_validate_irq,
1018 .write_codec = vx2_old_write_codec_bit,
1019 .reset_codec = vx2_reset_codec,
1020 .change_audio_source = vx2_change_audio_source,
1021 .set_clock_source = vx2_set_clock_source,
1022 .load_dsp = vx2_load_dsp,
1023 .reset_dsp = vx2_reset_dsp,
1024 .reset_board = vx2_reset_board,
1025 .dma_write = vx2_dma_write,
1026 .dma_read = vx2_dma_read,
1027};
1028
1029