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9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gcd.h>
12#include <linux/gpio/consumer.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/pm.h>
16#include <linux/slab.h>
17
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/tlv.h>
22#include <sound/soc.h>
23
24#include "adau1372.h"
25#include "adau-utils.h"
26
27struct adau1372 {
28 struct clk *clk;
29 struct regmap *regmap;
30 void (*switch_mode)(struct device *dev);
31 bool use_pll;
32 bool enabled;
33 bool master;
34
35 struct snd_pcm_hw_constraint_list rate_constraints;
36 unsigned int slot_width;
37
38 struct clk *mclk;
39 struct gpio_desc *pd_gpio;
40 struct device *dev;
41};
42
43#define ADAU1372_REG_CLK_CTRL 0x00
44#define ADAU1372_REG_PLL(x) (0x01 + (x))
45#define ADAU1372_REG_DAC_SOURCE 0x11
46#define ADAU1372_REG_SOUT_SOURCE_0_1 0x13
47#define ADAU1372_REG_SOUT_SOURCE_2_3 0x14
48#define ADAU1372_REG_SOUT_SOURCE_4_5 0x15
49#define ADAU1372_REG_SOUT_SOURCE_6_7 0x16
50#define ADAU1372_REG_ADC_SDATA_CH 0x17
51#define ADAU1372_REG_ASRCO_SOURCE_0_1 0x18
52#define ADAU1372_REG_ASRCO_SOURCE_2_3 0x19
53#define ADAU1372_REG_ASRC_MODE 0x1a
54#define ADAU1372_REG_ADC_CTRL0 0x1b
55#define ADAU1372_REG_ADC_CTRL1 0x1c
56#define ADAU1372_REG_ADC_CTRL2 0x1d
57#define ADAU1372_REG_ADC_CTRL3 0x1e
58#define ADAU1372_REG_ADC_VOL(x) (0x1f + (x))
59#define ADAU1372_REG_PGA_CTRL(x) (0x23 + (x))
60#define ADAU1372_REG_PGA_BOOST 0x28
61#define ADAU1372_REG_MICBIAS 0x2d
62#define ADAU1372_REG_DAC_CTRL 0x2e
63#define ADAU1372_REG_DAC_VOL(x) (0x2f + (x))
64#define ADAU1372_REG_OP_STAGE_MUTE 0x31
65#define ADAU1372_REG_SAI0 0x32
66#define ADAU1372_REG_SAI1 0x33
67#define ADAU1372_REG_SOUT_CTRL 0x34
68#define ADAU1372_REG_MODE_MP(x) (0x38 + (x))
69#define ADAU1372_REG_OP_STAGE_CTRL 0x43
70#define ADAU1372_REG_DECIM_PWR 0x44
71#define ADAU1372_REG_INTERP_PWR 0x45
72#define ADAU1372_REG_BIAS_CTRL0 0x46
73#define ADAU1372_REG_BIAS_CTRL1 0x47
74
75#define ADAU1372_CLK_CTRL_PLL_EN BIT(7)
76#define ADAU1372_CLK_CTRL_XTAL_DIS BIT(4)
77#define ADAU1372_CLK_CTRL_CLKSRC BIT(3)
78#define ADAU1372_CLK_CTRL_CC_MDIV BIT(1)
79#define ADAU1372_CLK_CTRL_MCLK_EN BIT(0)
80
81#define ADAU1372_SAI0_DELAY1 (0x0 << 6)
82#define ADAU1372_SAI0_DELAY0 (0x1 << 6)
83#define ADAU1372_SAI0_DELAY_MASK (0x3 << 6)
84#define ADAU1372_SAI0_SAI_I2S (0x0 << 4)
85#define ADAU1372_SAI0_SAI_TDM2 (0x1 << 4)
86#define ADAU1372_SAI0_SAI_TDM4 (0x2 << 4)
87#define ADAU1372_SAI0_SAI_TDM8 (0x3 << 4)
88#define ADAU1372_SAI0_SAI_MASK (0x3 << 4)
89#define ADAU1372_SAI0_FS_48 0x0
90#define ADAU1372_SAI0_FS_8 0x1
91#define ADAU1372_SAI0_FS_12 0x2
92#define ADAU1372_SAI0_FS_16 0x3
93#define ADAU1372_SAI0_FS_24 0x4
94#define ADAU1372_SAI0_FS_32 0x5
95#define ADAU1372_SAI0_FS_96 0x6
96#define ADAU1372_SAI0_FS_192 0x7
97#define ADAU1372_SAI0_FS_MASK 0xf
98
99#define ADAU1372_SAI1_TDM_TS BIT(7)
100#define ADAU1372_SAI1_BCLK_TDMC BIT(6)
101#define ADAU1372_SAI1_LR_MODE BIT(5)
102#define ADAU1372_SAI1_LR_POL BIT(4)
103#define ADAU1372_SAI1_BCLKRATE BIT(2)
104#define ADAU1372_SAI1_BCLKEDGE BIT(1)
105#define ADAU1372_SAI1_MS BIT(0)
106
107static const unsigned int adau1372_rates[] = {
108 [ADAU1372_SAI0_FS_8] = 8000,
109 [ADAU1372_SAI0_FS_12] = 12000,
110 [ADAU1372_SAI0_FS_16] = 16000,
111 [ADAU1372_SAI0_FS_24] = 24000,
112 [ADAU1372_SAI0_FS_32] = 32000,
113 [ADAU1372_SAI0_FS_48] = 48000,
114 [ADAU1372_SAI0_FS_96] = 96000,
115 [ADAU1372_SAI0_FS_192] = 192000,
116};
117
118
119#define ADAU1372_RATE_MASK_TDM8 0x17
120
121#define ADAU1372_RATE_MASK_TDM4_MASTER (ADAU1372_RATE_MASK_TDM8 | 0x48 | 0x20)
122
123#define ADAU1372_RATE_MASK_TDM4 (ADAU1372_RATE_MASK_TDM4_MASTER | 0x20)
124
125#define ADAU1372_RATE_MASK_TDM2 (ADAU1372_RATE_MASK_TDM4 | 0x80)
126
127static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
128static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
129static const DECLARE_TLV_DB_SCALE(adau1372_pga_boost_tlv, 0, 1000, 0);
130
131static const char * const adau1372_bias_text[] = {
132 "Normal operation", "Extreme power saving", "Enhanced performance",
133 "Power saving",
134};
135
136static const unsigned int adau1372_bias_adc_values[] = {
137 0, 2, 3,
138};
139
140static const char * const adau1372_bias_adc_text[] = {
141 "Normal operation", "Enhanced performance", "Power saving",
142};
143
144static const char * const adau1372_bias_dac_text[] = {
145 "Normal operation", "Power saving", "Superior performance",
146 "Enhanced performance",
147};
148
149static SOC_ENUM_SINGLE_DECL(adau1372_bias_hp_enum,
150 ADAU1372_REG_BIAS_CTRL0, 6, adau1372_bias_text);
151static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe0_1_enum,
152 ADAU1372_REG_BIAS_CTRL0, 4, adau1372_bias_text);
153static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc2_3_enum,
154 ADAU1372_REG_BIAS_CTRL0, 2, 0x3, adau1372_bias_adc_text,
155 adau1372_bias_adc_values);
156static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_bias_adc0_1_enum,
157 ADAU1372_REG_BIAS_CTRL0, 0, 0x3, adau1372_bias_adc_text,
158 adau1372_bias_adc_values);
159static SOC_ENUM_SINGLE_DECL(adau1372_bias_afe2_3_enum,
160 ADAU1372_REG_BIAS_CTRL1, 4, adau1372_bias_text);
161static SOC_ENUM_SINGLE_DECL(adau1372_bias_mic_enum,
162 ADAU1372_REG_BIAS_CTRL1, 2, adau1372_bias_text);
163static SOC_ENUM_SINGLE_DECL(adau1372_bias_dac_enum,
164 ADAU1372_REG_BIAS_CTRL1, 0, adau1372_bias_dac_text);
165
166static const char * const adau1372_hpf_text[] = {
167 "Off",
168 "1 Hz",
169 "4 Hz",
170 "8 Hz",
171};
172
173static SOC_ENUM_SINGLE_DECL(adau1372_hpf0_1_enum, ADAU1372_REG_ADC_CTRL2, 5,
174 adau1372_hpf_text);
175static SOC_ENUM_SINGLE_DECL(adau1372_hpf2_3_enum, ADAU1372_REG_ADC_CTRL3, 5,
176 adau1372_hpf_text);
177static const struct snd_kcontrol_new adau1372_controls[] = {
178 SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
179 0, 0xff, 1, adau1372_digital_tlv),
180 SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
181 0, 0xff, 1, adau1372_digital_tlv),
182 SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
183 0, 0xff, 1, adau1372_digital_tlv),
184 SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
185 0, 0xff, 1, adau1372_digital_tlv),
186 SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
187 SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
188 SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
189 SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
190
191 SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
192 SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
193
194 SOC_SINGLE_TLV("PGA 0 Capture Volume", ADAU1372_REG_PGA_CTRL(0),
195 0, 0x3f, 0, adau1372_pga_tlv),
196 SOC_SINGLE_TLV("PGA 1 Capture Volume", ADAU1372_REG_PGA_CTRL(1),
197 0, 0x3f, 0, adau1372_pga_tlv),
198 SOC_SINGLE_TLV("PGA 2 Capture Volume", ADAU1372_REG_PGA_CTRL(2),
199 0, 0x3f, 0, adau1372_pga_tlv),
200 SOC_SINGLE_TLV("PGA 3 Capture Volume", ADAU1372_REG_PGA_CTRL(3),
201 0, 0x3f, 0, adau1372_pga_tlv),
202 SOC_SINGLE_TLV("PGA 0 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
203 0, 1, 0, adau1372_pga_boost_tlv),
204 SOC_SINGLE_TLV("PGA 1 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
205 1, 1, 0, adau1372_pga_boost_tlv),
206 SOC_SINGLE_TLV("PGA 2 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
207 2, 1, 0, adau1372_pga_boost_tlv),
208 SOC_SINGLE_TLV("PGA 3 Boost Capture Volume", ADAU1372_REG_PGA_BOOST,
209 3, 1, 0, adau1372_pga_boost_tlv),
210 SOC_SINGLE("PGA 0 Capture Switch", ADAU1372_REG_PGA_CTRL(0), 7, 1, 1),
211 SOC_SINGLE("PGA 1 Capture Switch", ADAU1372_REG_PGA_CTRL(1), 7, 1, 1),
212 SOC_SINGLE("PGA 2 Capture Switch", ADAU1372_REG_PGA_CTRL(2), 7, 1, 1),
213 SOC_SINGLE("PGA 3 Capture Switch", ADAU1372_REG_PGA_CTRL(3), 7, 1, 1),
214
215 SOC_SINGLE_TLV("DAC 0 Playback Volume", ADAU1372_REG_DAC_VOL(0),
216 0, 0xff, 1, adau1372_digital_tlv),
217 SOC_SINGLE_TLV("DAC 1 Playback Volume", ADAU1372_REG_DAC_VOL(1),
218 0, 0xff, 1, adau1372_digital_tlv),
219 SOC_SINGLE("DAC 0 Playback Switch", ADAU1372_REG_DAC_CTRL, 3, 1, 1),
220 SOC_SINGLE("DAC 1 Playback Switch", ADAU1372_REG_DAC_CTRL, 4, 1, 1),
221
222 SOC_ENUM("Headphone Bias", adau1372_bias_hp_enum),
223 SOC_ENUM("Microphone Bias", adau1372_bias_mic_enum),
224 SOC_ENUM("AFE 0+1 Bias", adau1372_bias_afe0_1_enum),
225 SOC_ENUM("AFE 2+3 Bias", adau1372_bias_afe2_3_enum),
226 SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
227 SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
228 SOC_ENUM("DAC 0+1 Bias", adau1372_bias_dac_enum),
229};
230
231static const char * const adau1372_decimator_mux_text[] = {
232 "ADC",
233 "DMIC",
234};
235
236static SOC_ENUM_SINGLE_DECL(adau1372_decimator0_1_mux_enum, ADAU1372_REG_ADC_CTRL2,
237 2, adau1372_decimator_mux_text);
238
239static const struct snd_kcontrol_new adau1372_decimator0_1_mux_control =
240 SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
241
242static SOC_ENUM_SINGLE_DECL(adau1372_decimator2_3_mux_enum, ADAU1372_REG_ADC_CTRL3,
243 2, adau1372_decimator_mux_text);
244
245static const struct snd_kcontrol_new adau1372_decimator2_3_mux_control =
246 SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
247
248static const unsigned int adau1372_asrco_mux_values[] = {
249 4, 5, 6, 7,
250};
251
252static const char * const adau1372_asrco_mux_text[] = {
253 "Decimator0",
254 "Decimator1",
255 "Decimator2",
256 "Decimator3",
257};
258
259static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco0_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
260 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
261static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco1_mux_enum, ADAU1372_REG_ASRCO_SOURCE_0_1,
262 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
263static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco2_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
264 0, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
265static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_asrco3_mux_enum, ADAU1372_REG_ASRCO_SOURCE_2_3,
266 4, 0xf, adau1372_asrco_mux_text, adau1372_asrco_mux_values);
267
268static const struct snd_kcontrol_new adau1372_asrco0_mux_control =
269 SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
270static const struct snd_kcontrol_new adau1372_asrco1_mux_control =
271 SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
272static const struct snd_kcontrol_new adau1372_asrco2_mux_control =
273 SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
274static const struct snd_kcontrol_new adau1372_asrco3_mux_control =
275 SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
276
277static const unsigned int adau1372_sout_mux_values[] = {
278 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
279};
280
281static const char * const adau1372_sout_mux_text[] = {
282 "Output ASRC0",
283 "Output ASRC1",
284 "Output ASRC2",
285 "Output ASRC3",
286 "Serial Input 0",
287 "Serial Input 1",
288 "Serial Input 2",
289 "Serial Input 3",
290 "Serial Input 4",
291 "Serial Input 5",
292 "Serial Input 6",
293 "Serial Input 7",
294};
295
296static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout0_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
297 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
298static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout1_mux_enum, ADAU1372_REG_SOUT_SOURCE_0_1,
299 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
300static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout2_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
301 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
302static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout3_mux_enum, ADAU1372_REG_SOUT_SOURCE_2_3,
303 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
304static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout4_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
305 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
306static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout5_mux_enum, ADAU1372_REG_SOUT_SOURCE_4_5,
307 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
308static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout6_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
309 0, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
310static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_sout7_mux_enum, ADAU1372_REG_SOUT_SOURCE_6_7,
311 4, 0xf, adau1372_sout_mux_text, adau1372_sout_mux_values);
312
313static const struct snd_kcontrol_new adau1372_sout0_mux_control =
314 SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
315static const struct snd_kcontrol_new adau1372_sout1_mux_control =
316 SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
317static const struct snd_kcontrol_new adau1372_sout2_mux_control =
318 SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
319static const struct snd_kcontrol_new adau1372_sout3_mux_control =
320 SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
321static const struct snd_kcontrol_new adau1372_sout4_mux_control =
322 SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
323static const struct snd_kcontrol_new adau1372_sout5_mux_control =
324 SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
325static const struct snd_kcontrol_new adau1372_sout6_mux_control =
326 SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
327static const struct snd_kcontrol_new adau1372_sout7_mux_control =
328 SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
329
330static const char * const adau1372_asrci_mux_text[] = {
331 "Serial Input 0+1",
332 "Serial Input 2+3",
333 "Serial Input 4+5",
334 "Serial Input 6+7",
335};
336
337static SOC_ENUM_SINGLE_DECL(adau1372_asrci_mux_enum,
338 ADAU1372_REG_ASRC_MODE, 2, adau1372_asrci_mux_text);
339
340static const struct snd_kcontrol_new adau1372_asrci_mux_control =
341 SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
342
343static const unsigned int adau1372_dac_mux_values[] = {
344 12, 13
345};
346
347static const char * const adau1372_dac_mux_text[] = {
348 "Input ASRC0",
349 "Input ASRC1",
350};
351
352static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac0_mux_enum, ADAU1372_REG_DAC_SOURCE,
353 0, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
354static SOC_VALUE_ENUM_SINGLE_DECL(adau1372_dac1_mux_enum, ADAU1372_REG_DAC_SOURCE,
355 4, 0xf, adau1372_dac_mux_text, adau1372_dac_mux_values);
356
357static const struct snd_kcontrol_new adau1372_dac0_mux_control =
358 SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
359static const struct snd_kcontrol_new adau1372_dac1_mux_control =
360 SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
361
362static const struct snd_soc_dapm_widget adau1372_dapm_widgets[] = {
363 SND_SOC_DAPM_INPUT("AIN0"),
364 SND_SOC_DAPM_INPUT("AIN1"),
365 SND_SOC_DAPM_INPUT("AIN2"),
366 SND_SOC_DAPM_INPUT("AIN3"),
367 SND_SOC_DAPM_INPUT("DMIC0_1"),
368 SND_SOC_DAPM_INPUT("DMIC2_3"),
369
370 SND_SOC_DAPM_SUPPLY("MICBIAS0", ADAU1372_REG_MICBIAS, 4, 0, NULL, 0),
371 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1372_REG_MICBIAS, 5, 0, NULL, 0),
372
373 SND_SOC_DAPM_PGA("PGA0", ADAU1372_REG_PGA_CTRL(0), 6, 0, NULL, 0),
374 SND_SOC_DAPM_PGA("PGA1", ADAU1372_REG_PGA_CTRL(1), 6, 0, NULL, 0),
375 SND_SOC_DAPM_PGA("PGA2", ADAU1372_REG_PGA_CTRL(2), 6, 0, NULL, 0),
376 SND_SOC_DAPM_PGA("PGA3", ADAU1372_REG_PGA_CTRL(3), 6, 0, NULL, 0),
377 SND_SOC_DAPM_ADC("ADC0", NULL, ADAU1372_REG_ADC_CTRL2, 0, 0),
378 SND_SOC_DAPM_ADC("ADC1", NULL, ADAU1372_REG_ADC_CTRL2, 1, 0),
379 SND_SOC_DAPM_ADC("ADC2", NULL, ADAU1372_REG_ADC_CTRL3, 0, 0),
380 SND_SOC_DAPM_ADC("ADC3", NULL, ADAU1372_REG_ADC_CTRL3, 1, 0),
381
382 SND_SOC_DAPM_SUPPLY("ADC0 Filter", ADAU1372_REG_DECIM_PWR, 0, 0, NULL, 0),
383 SND_SOC_DAPM_SUPPLY("ADC1 Filter", ADAU1372_REG_DECIM_PWR, 1, 0, NULL, 0),
384 SND_SOC_DAPM_SUPPLY("ADC2 Filter", ADAU1372_REG_DECIM_PWR, 2, 0, NULL, 0),
385 SND_SOC_DAPM_SUPPLY("ADC3 Filter", ADAU1372_REG_DECIM_PWR, 3, 0, NULL, 0),
386 SND_SOC_DAPM_SUPPLY("Output ASRC0 Decimator", ADAU1372_REG_DECIM_PWR, 4, 0, NULL, 0),
387 SND_SOC_DAPM_SUPPLY("Output ASRC1 Decimator", ADAU1372_REG_DECIM_PWR, 5, 0, NULL, 0),
388 SND_SOC_DAPM_SUPPLY("Output ASRC2 Decimator", ADAU1372_REG_DECIM_PWR, 6, 0, NULL, 0),
389 SND_SOC_DAPM_SUPPLY("Output ASRC3 Decimator", ADAU1372_REG_DECIM_PWR, 7, 0, NULL, 0),
390
391 SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
392 SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
393 SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
394 SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
395
396 SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
397 SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
398 SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
399 SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
400 SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
401 &adau1372_sout0_mux_control),
402 SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
403 &adau1372_sout1_mux_control),
404 SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
405 &adau1372_sout2_mux_control),
406 SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
407 &adau1372_sout3_mux_control),
408 SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
409 &adau1372_sout4_mux_control),
410 SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
411 &adau1372_sout5_mux_control),
412 SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
413 &adau1372_sout6_mux_control),
414 SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
415 &adau1372_sout7_mux_control),
416
417 SND_SOC_DAPM_AIF_IN("Serial Input 0", NULL, 0, SND_SOC_NOPM, 0, 0),
418 SND_SOC_DAPM_AIF_IN("Serial Input 1", NULL, 1, SND_SOC_NOPM, 0, 0),
419 SND_SOC_DAPM_AIF_IN("Serial Input 2", NULL, 2, SND_SOC_NOPM, 0, 0),
420 SND_SOC_DAPM_AIF_IN("Serial Input 3", NULL, 3, SND_SOC_NOPM, 0, 0),
421 SND_SOC_DAPM_AIF_IN("Serial Input 4", NULL, 4, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_AIF_IN("Serial Input 5", NULL, 5, SND_SOC_NOPM, 0, 0),
423 SND_SOC_DAPM_AIF_IN("Serial Input 6", NULL, 6, SND_SOC_NOPM, 0, 0),
424 SND_SOC_DAPM_AIF_IN("Serial Input 7", NULL, 7, SND_SOC_NOPM, 0, 0),
425
426 SND_SOC_DAPM_AIF_OUT("Serial Output 0", NULL, 0, SND_SOC_NOPM, 0, 0),
427 SND_SOC_DAPM_AIF_OUT("Serial Output 1", NULL, 1, SND_SOC_NOPM, 0, 0),
428 SND_SOC_DAPM_AIF_OUT("Serial Output 2", NULL, 2, SND_SOC_NOPM, 0, 0),
429 SND_SOC_DAPM_AIF_OUT("Serial Output 3", NULL, 3, SND_SOC_NOPM, 0, 0),
430 SND_SOC_DAPM_AIF_OUT("Serial Output 4", NULL, 4, SND_SOC_NOPM, 0, 0),
431 SND_SOC_DAPM_AIF_OUT("Serial Output 5", NULL, 5, SND_SOC_NOPM, 0, 0),
432 SND_SOC_DAPM_AIF_OUT("Serial Output 6", NULL, 6, SND_SOC_NOPM, 0, 0),
433 SND_SOC_DAPM_AIF_OUT("Serial Output 7", NULL, 7, SND_SOC_NOPM, 0, 0),
434
435 SND_SOC_DAPM_SUPPLY("Output ASRC Supply", ADAU1372_REG_ASRC_MODE, 1, 0, NULL, 0),
436 SND_SOC_DAPM_SUPPLY("Input ASRC Supply", ADAU1372_REG_ASRC_MODE, 0, 0, NULL, 0),
437
438 SND_SOC_DAPM_SUPPLY("DAC1 Modulator", ADAU1372_REG_INTERP_PWR, 3, 0, NULL, 0),
439 SND_SOC_DAPM_SUPPLY("DAC0 Modulator", ADAU1372_REG_INTERP_PWR, 2, 0, NULL, 0),
440 SND_SOC_DAPM_SUPPLY("Input ASRC1 Interpolator", ADAU1372_REG_INTERP_PWR, 1, 0, NULL, 0),
441 SND_SOC_DAPM_SUPPLY("Input ASRC0 Interpolator", ADAU1372_REG_INTERP_PWR, 0, 0, NULL, 0),
442
443 SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
444 SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
445
446 SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
447 SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
448
449 SND_SOC_DAPM_DAC("DAC0", NULL, ADAU1372_REG_DAC_CTRL, 0, 0),
450 SND_SOC_DAPM_DAC("DAC1", NULL, ADAU1372_REG_DAC_CTRL, 1, 0),
451
452 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LP", ADAU1372_REG_OP_STAGE_CTRL, 0, 1, NULL, 0),
453 SND_SOC_DAPM_OUT_DRV("OP_STAGE_LN", ADAU1372_REG_OP_STAGE_CTRL, 1, 1, NULL, 0),
454 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RP", ADAU1372_REG_OP_STAGE_CTRL, 2, 1, NULL, 0),
455 SND_SOC_DAPM_OUT_DRV("OP_STAGE_RN", ADAU1372_REG_OP_STAGE_CTRL, 3, 1, NULL, 0),
456
457 SND_SOC_DAPM_OUTPUT("HPOUTL"),
458 SND_SOC_DAPM_OUTPUT("HPOUTR"),
459};
460
461#define ADAU1372_SOUT_ROUTES(x) \
462 { "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
463 { "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
464 { "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
465 { "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
466 { "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
467 { "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
468 { "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
469 { "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
470 { "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
471 { "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
472 { "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
473 { "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
474 { "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
475 { "Capture", NULL, "Serial Output " #x }
476
477#define ADAU1372_ASRCO_ROUTES(x) \
478 { "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
479 { "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
480 { "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
481 { "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
482
483static const struct snd_soc_dapm_route adau1372_dapm_routes[] = {
484 { "PGA0", NULL, "AIN0" },
485 { "PGA1", NULL, "AIN1" },
486 { "PGA2", NULL, "AIN2" },
487 { "PGA3", NULL, "AIN3" },
488
489 { "ADC0", NULL, "PGA0" },
490 { "ADC1", NULL, "PGA1" },
491 { "ADC2", NULL, "PGA2" },
492 { "ADC3", NULL, "PGA3" },
493
494 { "Decimator0 Mux", "ADC", "ADC0" },
495 { "Decimator1 Mux", "ADC", "ADC1" },
496 { "Decimator2 Mux", "ADC", "ADC2" },
497 { "Decimator3 Mux", "ADC", "ADC3" },
498
499 { "Decimator0 Mux", "DMIC", "DMIC0_1" },
500 { "Decimator1 Mux", "DMIC", "DMIC0_1" },
501 { "Decimator2 Mux", "DMIC", "DMIC2_3" },
502 { "Decimator3 Mux", "DMIC", "DMIC2_3" },
503
504 { "Decimator0 Mux", NULL, "ADC0 Filter" },
505 { "Decimator1 Mux", NULL, "ADC1 Filter" },
506 { "Decimator2 Mux", NULL, "ADC2 Filter" },
507 { "Decimator3 Mux", NULL, "ADC3 Filter" },
508
509 { "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
510 { "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
511 { "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
512 { "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
513 { "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
514 { "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
515 { "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
516 { "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
517
518 ADAU1372_ASRCO_ROUTES(0),
519 ADAU1372_ASRCO_ROUTES(1),
520 ADAU1372_ASRCO_ROUTES(2),
521 ADAU1372_ASRCO_ROUTES(3),
522
523 ADAU1372_SOUT_ROUTES(0),
524 ADAU1372_SOUT_ROUTES(1),
525 ADAU1372_SOUT_ROUTES(2),
526 ADAU1372_SOUT_ROUTES(3),
527 ADAU1372_SOUT_ROUTES(4),
528 ADAU1372_SOUT_ROUTES(5),
529 ADAU1372_SOUT_ROUTES(6),
530 ADAU1372_SOUT_ROUTES(7),
531
532 { "Serial Input 0", NULL, "Playback" },
533 { "Serial Input 1", NULL, "Playback" },
534 { "Serial Input 2", NULL, "Playback" },
535 { "Serial Input 3", NULL, "Playback" },
536 { "Serial Input 4", NULL, "Playback" },
537 { "Serial Input 5", NULL, "Playback" },
538 { "Serial Input 6", NULL, "Playback" },
539 { "Serial Input 7", NULL, "Playback" },
540
541 { "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
542 { "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
543 { "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
544 { "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
545 { "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
546 { "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
547 { "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
548 { "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
549 { "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
550 { "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
551 { "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
552 { "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
553
554 { "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
555 { "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
556 { "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
557 { "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
558
559 { "DAC0", NULL, "DAC 0 Mux" },
560 { "DAC1", NULL, "DAC 1 Mux" },
561 { "DAC0", NULL, "DAC0 Modulator" },
562 { "DAC1", NULL, "DAC1 Modulator" },
563
564 { "OP_STAGE_LP", NULL, "DAC0" },
565 { "OP_STAGE_LN", NULL, "DAC0" },
566 { "OP_STAGE_RP", NULL, "DAC1" },
567 { "OP_STAGE_RN", NULL, "DAC1" },
568
569 { "HPOUTL", NULL, "OP_STAGE_LP" },
570 { "HPOUTL", NULL, "OP_STAGE_LN" },
571 { "HPOUTR", NULL, "OP_STAGE_RP" },
572 { "HPOUTR", NULL, "OP_STAGE_RN" },
573};
574
575static int adau1372_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
576{
577 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
578 unsigned int sai0 = 0, sai1 = 0;
579 bool invert_lrclk = false;
580
581 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
582 case SND_SOC_DAIFMT_CBM_CFM:
583 adau1372->master = true;
584 sai1 |= ADAU1372_SAI1_MS;
585 break;
586 case SND_SOC_DAIFMT_CBS_CFS:
587 adau1372->master = false;
588 break;
589 default:
590 return -EINVAL;
591 }
592
593 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
594 case SND_SOC_DAIFMT_NB_NF:
595 invert_lrclk = false;
596 break;
597 case SND_SOC_DAIFMT_NB_IF:
598 invert_lrclk = true;
599 break;
600 case SND_SOC_DAIFMT_IB_NF:
601 invert_lrclk = false;
602 sai1 |= ADAU1372_SAI1_BCLKEDGE;
603 break;
604 case SND_SOC_DAIFMT_IB_IF:
605 invert_lrclk = true;
606 sai1 |= ADAU1372_SAI1_BCLKEDGE;
607 break;
608 }
609
610 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
611 case SND_SOC_DAIFMT_I2S:
612 sai0 |= ADAU1372_SAI0_DELAY1;
613 break;
614 case SND_SOC_DAIFMT_LEFT_J:
615 sai0 |= ADAU1372_SAI0_DELAY0;
616 invert_lrclk = !invert_lrclk;
617 break;
618 case SND_SOC_DAIFMT_DSP_A:
619 sai0 |= ADAU1372_SAI0_DELAY1;
620 sai1 |= ADAU1372_SAI1_LR_MODE;
621 break;
622 case SND_SOC_DAIFMT_DSP_B:
623 sai0 |= ADAU1372_SAI0_DELAY0;
624 sai1 |= ADAU1372_SAI1_LR_MODE;
625 break;
626 }
627
628 if (invert_lrclk)
629 sai1 |= ADAU1372_SAI1_LR_POL;
630
631 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
632 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
633 ADAU1372_SAI1_MS | ADAU1372_SAI1_BCLKEDGE |
634 ADAU1372_SAI1_LR_MODE | ADAU1372_SAI1_LR_POL, sai1);
635
636 return 0;
637}
638
639static int adau1372_hw_params(struct snd_pcm_substream *substream,
640 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
641{
642 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
643 unsigned int rate = params_rate(params);
644 unsigned int slot_width;
645 unsigned int sai0, sai1;
646 unsigned int i;
647
648 for (i = 0; i < ARRAY_SIZE(adau1372_rates); i++) {
649 if (rate == adau1372_rates[i])
650 break;
651 }
652
653 if (i == ARRAY_SIZE(adau1372_rates))
654 return -EINVAL;
655
656 sai0 = i;
657
658 slot_width = adau1372->slot_width;
659 if (slot_width == 0)
660 slot_width = params_width(params);
661
662 switch (slot_width) {
663 case 16:
664 sai1 = ADAU1372_SAI1_BCLKRATE;
665 break;
666 case 32:
667 sai1 = 0;
668 break;
669 default:
670 return -EINVAL;
671 }
672
673 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
674 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
675
676 return 0;
677}
678
679static int adau1372_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
680 unsigned int rx_mask, int slots, int width)
681{
682 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
683 unsigned int sai0, sai1;
684
685
686 if (slots == 0) {
687
688 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
689 ADAU1372_SAI0_SAI_MASK, ADAU1372_SAI0_SAI_I2S);
690 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
691 adau1372->slot_width = 0;
692 return 0;
693 }
694
695
696 if ((tx_mask & ~0xff) != 0 || (rx_mask & ~0xff) != 0)
697 return -EINVAL;
698
699 switch (width) {
700 case 16:
701 sai1 = ADAU1372_SAI1_BCLK_TDMC;
702 break;
703 case 32:
704 sai1 = 0;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 switch (slots) {
711 case 2:
712 sai0 = ADAU1372_SAI0_SAI_TDM2;
713 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
714 break;
715 case 4:
716 sai0 = ADAU1372_SAI0_SAI_TDM4;
717 if (adau1372->master)
718 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
719 else
720 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
721 break;
722 case 8:
723 sai0 = ADAU1372_SAI0_SAI_TDM8;
724 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
725 break;
726 default:
727 return -EINVAL;
728 }
729
730 adau1372->slot_width = width;
731
732 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
733 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
734
735
736 regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
737
738 return 0;
739}
740
741static int adau1372_set_tristate(struct snd_soc_dai *dai, int tristate)
742{
743 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
744 unsigned int sai1;
745
746 if (tristate)
747 sai1 = ADAU1372_SAI1_TDM_TS;
748 else
749 sai1 = 0;
750
751 return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
752}
753
754static int adau1372_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
755{
756 struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
757
758 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
759 &adau1372->rate_constraints);
760
761 return 0;
762}
763
764static void adau1372_enable_pll(struct adau1372 *adau1372)
765{
766 unsigned int val, timeout = 0;
767 int ret;
768
769 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
770 ADAU1372_CLK_CTRL_PLL_EN, ADAU1372_CLK_CTRL_PLL_EN);
771 do {
772
773 usleep_range(1000, 2000);
774 ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
775 if (ret)
776 break;
777 timeout++;
778 } while (!(val & 1) && timeout < 3);
779
780 if (ret < 0 || !(val & 1))
781 dev_err(adau1372->dev, "Failed to lock PLL\n");
782}
783
784static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
785{
786 if (adau1372->enabled == enable)
787 return;
788
789 if (enable) {
790 unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN;
791
792 clk_prepare_enable(adau1372->mclk);
793 if (adau1372->pd_gpio)
794 gpiod_set_value(adau1372->pd_gpio, 0);
795
796 if (adau1372->switch_mode)
797 adau1372->switch_mode(adau1372->dev);
798
799 regcache_cache_only(adau1372->regmap, false);
800
801
802
803
804
805 if (adau1372->use_pll) {
806 adau1372_enable_pll(adau1372);
807 clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC;
808 }
809
810 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
811 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl);
812 regcache_sync(adau1372->regmap);
813 } else {
814 if (adau1372->pd_gpio) {
815
816
817
818
819
820 gpiod_set_value(adau1372->pd_gpio, 1);
821 regcache_mark_dirty(adau1372->regmap);
822 } else {
823 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
824 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_PLL_EN, 0);
825 }
826 clk_disable_unprepare(adau1372->mclk);
827 regcache_cache_only(adau1372->regmap, true);
828 }
829
830 adau1372->enabled = enable;
831}
832
833static int adau1372_set_bias_level(struct snd_soc_component *component,
834 enum snd_soc_bias_level level)
835{
836 struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
837
838 switch (level) {
839 case SND_SOC_BIAS_ON:
840 break;
841 case SND_SOC_BIAS_PREPARE:
842 break;
843 case SND_SOC_BIAS_STANDBY:
844 adau1372_set_power(adau1372, true);
845 break;
846 case SND_SOC_BIAS_OFF:
847 adau1372_set_power(adau1372, false);
848 break;
849 }
850
851 return 0;
852}
853
854static const struct snd_soc_component_driver adau1372_driver = {
855 .set_bias_level = adau1372_set_bias_level,
856 .controls = adau1372_controls,
857 .num_controls = ARRAY_SIZE(adau1372_controls),
858 .dapm_widgets = adau1372_dapm_widgets,
859 .num_dapm_widgets = ARRAY_SIZE(adau1372_dapm_widgets),
860 .dapm_routes = adau1372_dapm_routes,
861 .num_dapm_routes = ARRAY_SIZE(adau1372_dapm_routes),
862};
863
864static const struct snd_soc_dai_ops adau1372_dai_ops = {
865 .set_fmt = adau1372_set_dai_fmt,
866 .set_tdm_slot = adau1372_set_tdm_slot,
867 .set_tristate = adau1372_set_tristate,
868 .hw_params = adau1372_hw_params,
869 .startup = adau1372_startup,
870};
871
872#define ADAU1372_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
873
874static struct snd_soc_dai_driver adau1372_dai_driver = {
875 .name = "adau1372",
876 .playback = {
877 .stream_name = "Playback",
878 .channels_min = 2,
879 .channels_max = 8,
880 .rates = SNDRV_PCM_RATE_KNOT,
881 .formats = ADAU1372_FORMATS,
882 .sig_bits = 24,
883 },
884 .capture = {
885 .stream_name = "Capture",
886 .channels_min = 2,
887 .channels_max = 8,
888 .rates = SNDRV_PCM_RATE_KNOT,
889 .formats = ADAU1372_FORMATS,
890 .sig_bits = 24,
891 },
892 .ops = &adau1372_dai_ops,
893 .symmetric_rate = 1,
894};
895
896static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
897{
898 u8 regs[5];
899 unsigned int i;
900 int ret;
901
902 ret = adau_calc_pll_cfg(rate, 49152000, regs);
903 if (ret < 0)
904 return ret;
905
906 for (i = 0; i < ARRAY_SIZE(regs); i++)
907 regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
908
909 return 0;
910}
911
912int adau1372_probe(struct device *dev, struct regmap *regmap,
913 void (*switch_mode)(struct device *dev))
914{
915 struct adau1372 *adau1372;
916 unsigned int clk_ctrl;
917 unsigned long rate;
918 int ret;
919
920 if (IS_ERR(regmap))
921 return PTR_ERR(regmap);
922
923 adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
924 if (!adau1372)
925 return -ENOMEM;
926
927 adau1372->clk = devm_clk_get(dev, "mclk");
928 if (IS_ERR(adau1372->clk))
929 return PTR_ERR(adau1372->clk);
930
931 adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
932 if (IS_ERR(adau1372->pd_gpio))
933 return PTR_ERR(adau1372->pd_gpio);
934
935 adau1372->regmap = regmap;
936 adau1372->switch_mode = switch_mode;
937 adau1372->dev = dev;
938 adau1372->rate_constraints.list = adau1372_rates;
939 adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
940 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
941
942 dev_set_drvdata(dev, adau1372);
943
944
945
946
947
948
949 rate = clk_get_rate(adau1372->clk);
950
951 switch (rate) {
952 case 12288000:
953 clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV;
954 break;
955 case 24576000:
956 clk_ctrl = 0;
957 break;
958 default:
959 clk_ctrl = 0;
960 ret = adau1372_setup_pll(adau1372, rate);
961 if (ret < 0)
962 return ret;
963 adau1372->use_pll = true;
964 break;
965 }
966
967
968
969
970
971 regcache_cache_only(regmap, true);
972
973 regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl);
974
975
976
977
978
979 regmap_write(regmap, ADAU1372_REG_MODE_MP(1), 0x00);
980 regmap_write(regmap, ADAU1372_REG_MODE_MP(6), 0x12);
981
982 regmap_write(regmap, ADAU1372_REG_OP_STAGE_MUTE, 0x0);
983
984 regmap_write(regmap, 0x7, 0x01);
985
986 return devm_snd_soc_register_component(dev, &adau1372_driver, &adau1372_dai_driver, 1);
987}
988EXPORT_SYMBOL(adau1372_probe);
989
990static const struct reg_default adau1372_reg_defaults[] = {
991 { ADAU1372_REG_CLK_CTRL, 0x00 },
992 { ADAU1372_REG_PLL(0), 0x00 },
993 { ADAU1372_REG_PLL(1), 0x00 },
994 { ADAU1372_REG_PLL(2), 0x00 },
995 { ADAU1372_REG_PLL(3), 0x00 },
996 { ADAU1372_REG_PLL(4), 0x00 },
997 { ADAU1372_REG_PLL(5), 0x00 },
998 { ADAU1372_REG_DAC_SOURCE, 0x10 },
999 { ADAU1372_REG_SOUT_SOURCE_0_1, 0x54 },
1000 { ADAU1372_REG_SOUT_SOURCE_2_3, 0x76 },
1001 { ADAU1372_REG_SOUT_SOURCE_4_5, 0x54 },
1002 { ADAU1372_REG_SOUT_SOURCE_6_7, 0x76 },
1003 { ADAU1372_REG_ADC_SDATA_CH, 0x04 },
1004 { ADAU1372_REG_ASRCO_SOURCE_0_1, 0x10 },
1005 { ADAU1372_REG_ASRCO_SOURCE_2_3, 0x32 },
1006 { ADAU1372_REG_ASRC_MODE, 0x00 },
1007 { ADAU1372_REG_ADC_CTRL0, 0x19 },
1008 { ADAU1372_REG_ADC_CTRL1, 0x19 },
1009 { ADAU1372_REG_ADC_CTRL2, 0x00 },
1010 { ADAU1372_REG_ADC_CTRL3, 0x00 },
1011 { ADAU1372_REG_ADC_VOL(0), 0x00 },
1012 { ADAU1372_REG_ADC_VOL(1), 0x00 },
1013 { ADAU1372_REG_ADC_VOL(2), 0x00 },
1014 { ADAU1372_REG_ADC_VOL(3), 0x00 },
1015 { ADAU1372_REG_PGA_CTRL(0), 0x40 },
1016 { ADAU1372_REG_PGA_CTRL(1), 0x40 },
1017 { ADAU1372_REG_PGA_CTRL(2), 0x40 },
1018 { ADAU1372_REG_PGA_CTRL(3), 0x40 },
1019 { ADAU1372_REG_PGA_BOOST, 0x00 },
1020 { ADAU1372_REG_MICBIAS, 0x00 },
1021 { ADAU1372_REG_DAC_CTRL, 0x18 },
1022 { ADAU1372_REG_DAC_VOL(0), 0x00 },
1023 { ADAU1372_REG_DAC_VOL(1), 0x00 },
1024 { ADAU1372_REG_OP_STAGE_MUTE, 0x0f },
1025 { ADAU1372_REG_SAI0, 0x00 },
1026 { ADAU1372_REG_SAI1, 0x00 },
1027 { ADAU1372_REG_SOUT_CTRL, 0x00 },
1028 { ADAU1372_REG_MODE_MP(0), 0x00 },
1029 { ADAU1372_REG_MODE_MP(1), 0x10 },
1030 { ADAU1372_REG_MODE_MP(4), 0x00 },
1031 { ADAU1372_REG_MODE_MP(5), 0x00 },
1032 { ADAU1372_REG_MODE_MP(6), 0x11 },
1033 { ADAU1372_REG_OP_STAGE_CTRL, 0x0f },
1034 { ADAU1372_REG_DECIM_PWR, 0x00 },
1035 { ADAU1372_REG_INTERP_PWR, 0x00 },
1036 { ADAU1372_REG_BIAS_CTRL0, 0x00 },
1037 { ADAU1372_REG_BIAS_CTRL1, 0x00 },
1038};
1039
1040static bool adau1372_volatile_register(struct device *dev, unsigned int reg)
1041{
1042 if (reg == ADAU1372_REG_PLL(5))
1043 return true;
1044
1045 return false;
1046}
1047
1048const struct regmap_config adau1372_regmap_config = {
1049 .val_bits = 8,
1050 .reg_bits = 16,
1051 .max_register = 0x4d,
1052
1053 .reg_defaults = adau1372_reg_defaults,
1054 .num_reg_defaults = ARRAY_SIZE(adau1372_reg_defaults),
1055 .volatile_reg = adau1372_volatile_register,
1056 .cache_type = REGCACHE_RBTREE,
1057};
1058EXPORT_SYMBOL_GPL(adau1372_regmap_config);
1059
1060MODULE_DESCRIPTION("ASoC ADAU1372 CODEC driver");
1061MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1062MODULE_LICENSE("GPL v2");
1063
