1
2#ifndef __ADAU17X1_H__
3#define __ADAU17X1_H__
4
5#include <linux/regmap.h>
6#include <linux/platform_data/adau17x1.h>
7
8#include "sigmadsp.h"
9
10enum adau17x1_type {
11 ADAU1361,
12 ADAU1761,
13 ADAU1381,
14 ADAU1781,
15};
16
17enum adau17x1_pll {
18 ADAU17X1_PLL,
19};
20
21enum adau17x1_pll_src {
22 ADAU17X1_PLL_SRC_MCLK,
23};
24
25enum adau17x1_clk_src {
26
27 ADAU17X1_CLK_SRC_PLL_AUTO,
28 ADAU17X1_CLK_SRC_MCLK,
29 ADAU17X1_CLK_SRC_PLL,
30};
31
32struct clk;
33
34struct adau {
35 unsigned int sysclk;
36 unsigned int pll_freq;
37 struct clk *mclk;
38
39 enum adau17x1_clk_src clk_src;
40 enum adau17x1_type type;
41 void (*switch_mode)(struct device *dev);
42
43 unsigned int dai_fmt;
44
45 uint8_t pll_regs[6];
46
47 bool master;
48
49 unsigned int tdm_slot[2];
50 bool dsp_bypass[2];
51
52 struct regmap *regmap;
53 struct sigmadsp *sigmadsp;
54};
55
56int adau17x1_add_widgets(struct snd_soc_component *component);
57int adau17x1_add_routes(struct snd_soc_component *component);
58int adau17x1_probe(struct device *dev, struct regmap *regmap,
59 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
60 const char *firmware_name);
61void adau17x1_remove(struct device *dev);
62int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
63 enum adau17x1_micbias_voltage micbias);
64bool adau17x1_readable_register(struct device *dev, unsigned int reg);
65bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
66bool adau17x1_precious_register(struct device *dev, unsigned int reg);
67int adau17x1_resume(struct snd_soc_component *component);
68
69extern const struct snd_soc_dai_ops adau17x1_dai_ops;
70
71#define ADAU17X1_CLOCK_CONTROL 0x4000
72#define ADAU17X1_PLL_CONTROL 0x4002
73#define ADAU17X1_REC_POWER_MGMT 0x4009
74#define ADAU17X1_MICBIAS 0x4010
75#define ADAU17X1_SERIAL_PORT0 0x4015
76#define ADAU17X1_SERIAL_PORT1 0x4016
77#define ADAU17X1_CONVERTER0 0x4017
78#define ADAU17X1_CONVERTER1 0x4018
79#define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a
80#define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b
81#define ADAU17X1_ADC_CONTROL 0x4019
82#define ADAU17X1_PLAY_POWER_MGMT 0x4029
83#define ADAU17X1_DAC_CONTROL0 0x402a
84#define ADAU17X1_DAC_CONTROL1 0x402b
85#define ADAU17X1_DAC_CONTROL2 0x402c
86#define ADAU17X1_SERIAL_PORT_PAD 0x402d
87#define ADAU17X1_CONTROL_PORT_PAD0 0x402f
88#define ADAU17X1_CONTROL_PORT_PAD1 0x4030
89#define ADAU17X1_DSP_SAMPLING_RATE 0x40eb
90#define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2
91#define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3
92#define ADAU17X1_DSP_ENABLE 0x40f5
93#define ADAU17X1_DSP_RUN 0x40f6
94#define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8
95
96#define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4)
97#define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3)
98#define ADAU17X1_SERIAL_PORT0_MASTER BIT(0)
99
100#define ADAU17X1_SERIAL_PORT1_DELAY1 0x00
101#define ADAU17X1_SERIAL_PORT1_DELAY0 0x01
102#define ADAU17X1_SERIAL_PORT1_DELAY8 0x02
103#define ADAU17X1_SERIAL_PORT1_DELAY16 0x03
104#define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03
105
106#define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6
107#define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3)
108#define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0)
109
110#define ADAU17X1_SERIAL_PORT1_BCLK64 (0x0 << 5)
111#define ADAU17X1_SERIAL_PORT1_BCLK32 (0x1 << 5)
112#define ADAU17X1_SERIAL_PORT1_BCLK48 (0x2 << 5)
113#define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5)
114#define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5)
115#define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5)
116
117#define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1)
118#define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1)
119#define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1)
120#define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1)
121#define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5)
122
123#define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5)
124#define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5)
125#define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1)
126#define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3
127
128#define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7
129
130#define ADAU17X1_CONVERTER0_ADOSR BIT(3)
131
132
133#endif
134
