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10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17#include <linux/workqueue.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/regulator/machine.h>
21#include <linux/pm_runtime.h>
22#include <linux/of_device.h>
23#include <linux/of_gpio.h>
24#include <linux/of_irq.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34#include <sound/cs35l34.h>
35
36#include "cs35l34.h"
37#include "cirrus_legacy.h"
38
39#define PDN_DONE_ATTEMPTS 10
40#define CS35L34_START_DELAY 50
41
42struct cs35l34_private {
43 struct snd_soc_component *component;
44 struct cs35l34_platform_data pdata;
45 struct regmap *regmap;
46 struct regulator_bulk_data core_supplies[2];
47 int num_core_supplies;
48 int mclk_int;
49 bool tdm_mode;
50 struct gpio_desc *reset_gpio;
51};
52
53static const struct reg_default cs35l34_reg[] = {
54 {CS35L34_PWRCTL1, 0x01},
55 {CS35L34_PWRCTL2, 0x19},
56 {CS35L34_PWRCTL3, 0x01},
57 {CS35L34_ADSP_CLK_CTL, 0x08},
58 {CS35L34_MCLK_CTL, 0x11},
59 {CS35L34_AMP_INP_DRV_CTL, 0x01},
60 {CS35L34_AMP_DIG_VOL_CTL, 0x12},
61 {CS35L34_AMP_DIG_VOL, 0x00},
62 {CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
63 {CS35L34_PROTECT_CTL, 0x06},
64 {CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
65 {CS35L34_BST_CVTR_V_CTL, 0x00},
66 {CS35L34_BST_PEAK_I, 0x10},
67 {CS35L34_BST_RAMP_CTL, 0x87},
68 {CS35L34_BST_CONV_COEF_1, 0x24},
69 {CS35L34_BST_CONV_COEF_2, 0x24},
70 {CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
71 {CS35L34_BST_CONV_SW_FREQ, 0x08},
72 {CS35L34_CLASS_H_CTL, 0x0D},
73 {CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
74 {CS35L34_CLASS_H_RELEASE_RATE, 0x08},
75 {CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
76 {CS35L34_CLASS_H_STATUS, 0x05},
77 {CS35L34_VPBR_CTL, 0x0A},
78 {CS35L34_VPBR_VOL_CTL, 0x90},
79 {CS35L34_VPBR_TIMING_CTL, 0x6A},
80 {CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
81 {CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
82 {CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
83 {CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
84 {CS35L34_PRED_WAIT_CTL, 0x10},
85 {CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
86 {CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
87 {CS35L34_VPBR_ATTEN_STATUS, 0x00},
88 {CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
89 {CS35L34_SPKR_MON_CTL, 0xC6},
90 {CS35L34_ADSP_I2S_CTL, 0x00},
91 {CS35L34_ADSP_TDM_CTL, 0x00},
92 {CS35L34_TDM_TX_CTL_1_VMON, 0x00},
93 {CS35L34_TDM_TX_CTL_2_IMON, 0x04},
94 {CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
95 {CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
96 {CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
97 {CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
98 {CS35L34_TDM_TX_SLOT_EN_1, 0x00},
99 {CS35L34_TDM_TX_SLOT_EN_2, 0x00},
100 {CS35L34_TDM_TX_SLOT_EN_3, 0x00},
101 {CS35L34_TDM_TX_SLOT_EN_4, 0x00},
102 {CS35L34_TDM_RX_CTL_1_AUDIN, 0x40},
103 {CS35L34_TDM_RX_CTL_3_ALIVE, 0x04},
104 {CS35L34_MULT_DEV_SYNCH1, 0x00},
105 {CS35L34_MULT_DEV_SYNCH2, 0x80},
106 {CS35L34_PROT_RELEASE_CTL, 0x00},
107 {CS35L34_DIAG_MODE_REG_LOCK, 0x00},
108 {CS35L34_DIAG_MODE_CTL_1, 0x00},
109 {CS35L34_DIAG_MODE_CTL_2, 0x00},
110 {CS35L34_INT_MASK_1, 0xFF},
111 {CS35L34_INT_MASK_2, 0xFF},
112 {CS35L34_INT_MASK_3, 0xFF},
113 {CS35L34_INT_MASK_4, 0xFF},
114 {CS35L34_INT_STATUS_1, 0x30},
115 {CS35L34_INT_STATUS_2, 0x05},
116 {CS35L34_INT_STATUS_3, 0x00},
117 {CS35L34_INT_STATUS_4, 0x00},
118 {CS35L34_OTP_TRIM_STATUS, 0x00},
119};
120
121static bool cs35l34_volatile_register(struct device *dev, unsigned int reg)
122{
123 switch (reg) {
124 case CS35L34_DEVID_AB:
125 case CS35L34_DEVID_CD:
126 case CS35L34_DEVID_E:
127 case CS35L34_FAB_ID:
128 case CS35L34_REV_ID:
129 case CS35L34_INT_STATUS_1:
130 case CS35L34_INT_STATUS_2:
131 case CS35L34_INT_STATUS_3:
132 case CS35L34_INT_STATUS_4:
133 case CS35L34_CLASS_H_STATUS:
134 case CS35L34_VPBR_ATTEN_STATUS:
135 case CS35L34_OTP_TRIM_STATUS:
136 return true;
137 default:
138 return false;
139 }
140}
141
142static bool cs35l34_readable_register(struct device *dev, unsigned int reg)
143{
144 switch (reg) {
145 case CS35L34_DEVID_AB:
146 case CS35L34_DEVID_CD:
147 case CS35L34_DEVID_E:
148 case CS35L34_FAB_ID:
149 case CS35L34_REV_ID:
150 case CS35L34_PWRCTL1:
151 case CS35L34_PWRCTL2:
152 case CS35L34_PWRCTL3:
153 case CS35L34_ADSP_CLK_CTL:
154 case CS35L34_MCLK_CTL:
155 case CS35L34_AMP_INP_DRV_CTL:
156 case CS35L34_AMP_DIG_VOL_CTL:
157 case CS35L34_AMP_DIG_VOL:
158 case CS35L34_AMP_ANLG_GAIN_CTL:
159 case CS35L34_PROTECT_CTL:
160 case CS35L34_AMP_KEEP_ALIVE_CTL:
161 case CS35L34_BST_CVTR_V_CTL:
162 case CS35L34_BST_PEAK_I:
163 case CS35L34_BST_RAMP_CTL:
164 case CS35L34_BST_CONV_COEF_1:
165 case CS35L34_BST_CONV_COEF_2:
166 case CS35L34_BST_CONV_SLOPE_COMP:
167 case CS35L34_BST_CONV_SW_FREQ:
168 case CS35L34_CLASS_H_CTL:
169 case CS35L34_CLASS_H_HEADRM_CTL:
170 case CS35L34_CLASS_H_RELEASE_RATE:
171 case CS35L34_CLASS_H_FET_DRIVE_CTL:
172 case CS35L34_CLASS_H_STATUS:
173 case CS35L34_VPBR_CTL:
174 case CS35L34_VPBR_VOL_CTL:
175 case CS35L34_VPBR_TIMING_CTL:
176 case CS35L34_PRED_MAX_ATTEN_SPK_LOAD:
177 case CS35L34_PRED_BROWNOUT_THRESH:
178 case CS35L34_PRED_BROWNOUT_VOL_CTL:
179 case CS35L34_PRED_BROWNOUT_RATE_CTL:
180 case CS35L34_PRED_WAIT_CTL:
181 case CS35L34_PRED_ZVP_INIT_IMP_CTL:
182 case CS35L34_PRED_MAN_SAFE_VPI_CTL:
183 case CS35L34_VPBR_ATTEN_STATUS:
184 case CS35L34_PRED_BRWNOUT_ATT_STATUS:
185 case CS35L34_SPKR_MON_CTL:
186 case CS35L34_ADSP_I2S_CTL:
187 case CS35L34_ADSP_TDM_CTL:
188 case CS35L34_TDM_TX_CTL_1_VMON:
189 case CS35L34_TDM_TX_CTL_2_IMON:
190 case CS35L34_TDM_TX_CTL_3_VPMON:
191 case CS35L34_TDM_TX_CTL_4_VBSTMON:
192 case CS35L34_TDM_TX_CTL_5_FLAG1:
193 case CS35L34_TDM_TX_CTL_6_FLAG2:
194 case CS35L34_TDM_TX_SLOT_EN_1:
195 case CS35L34_TDM_TX_SLOT_EN_2:
196 case CS35L34_TDM_TX_SLOT_EN_3:
197 case CS35L34_TDM_TX_SLOT_EN_4:
198 case CS35L34_TDM_RX_CTL_1_AUDIN:
199 case CS35L34_TDM_RX_CTL_3_ALIVE:
200 case CS35L34_MULT_DEV_SYNCH1:
201 case CS35L34_MULT_DEV_SYNCH2:
202 case CS35L34_PROT_RELEASE_CTL:
203 case CS35L34_DIAG_MODE_REG_LOCK:
204 case CS35L34_DIAG_MODE_CTL_1:
205 case CS35L34_DIAG_MODE_CTL_2:
206 case CS35L34_INT_MASK_1:
207 case CS35L34_INT_MASK_2:
208 case CS35L34_INT_MASK_3:
209 case CS35L34_INT_MASK_4:
210 case CS35L34_INT_STATUS_1:
211 case CS35L34_INT_STATUS_2:
212 case CS35L34_INT_STATUS_3:
213 case CS35L34_INT_STATUS_4:
214 case CS35L34_OTP_TRIM_STATUS:
215 return true;
216 default:
217 return false;
218 }
219}
220
221static bool cs35l34_precious_register(struct device *dev, unsigned int reg)
222{
223 switch (reg) {
224 case CS35L34_INT_STATUS_1:
225 case CS35L34_INT_STATUS_2:
226 case CS35L34_INT_STATUS_3:
227 case CS35L34_INT_STATUS_4:
228 return true;
229 default:
230 return false;
231 }
232}
233
234static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
235 struct snd_kcontrol *kcontrol, int event)
236{
237 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
238 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
239 int ret;
240
241 switch (event) {
242 case SND_SOC_DAPM_PRE_PMU:
243 if (priv->tdm_mode)
244 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
245 CS35L34_PDN_TDM, 0x00);
246
247 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
248 CS35L34_PDN_ALL, 0);
249 if (ret < 0) {
250 dev_err(component->dev, "Cannot set Power bits %d\n", ret);
251 return ret;
252 }
253 usleep_range(5000, 5100);
254 break;
255 case SND_SOC_DAPM_POST_PMD:
256 if (priv->tdm_mode) {
257 regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
258 CS35L34_PDN_TDM, CS35L34_PDN_TDM);
259 }
260 ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
261 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
262 break;
263 default:
264 pr_err("Invalid event = 0x%x\n", event);
265 }
266 return 0;
267}
268
269static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
270 unsigned int rx_mask, int slots, int slot_width)
271{
272 struct snd_soc_component *component = dai->component;
273 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
274 unsigned int reg, bit_pos;
275 int slot, slot_num;
276
277 if (slot_width != 8)
278 return -EINVAL;
279
280 priv->tdm_mode = true;
281
282 slot = ffs(rx_mask) - 1;
283 if (slot >= 0)
284 snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN,
285 CS35L34_X_LOC, slot);
286
287
288
289
290 slot = ffs(tx_mask) - 1;
291 slot_num = 0;
292
293
294 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
295 CS35L34_X_STATE | CS35L34_X_LOC,
296 CS35L34_X_STATE | CS35L34_X_LOC);
297 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON,
298 CS35L34_X_STATE | CS35L34_X_LOC,
299 CS35L34_X_STATE | CS35L34_X_LOC);
300
301
302 while (slot >= 0) {
303
304 if (slot_num == 0)
305 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON,
306 CS35L34_X_STATE | CS35L34_X_LOC, slot);
307
308
309 if (slot_num == 4) {
310 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON,
311 CS35L34_X_STATE | CS35L34_X_LOC, slot);
312 }
313
314 if (slot_num == 3) {
315 snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
316 CS35L34_X_STATE | CS35L34_X_LOC, slot);
317 }
318
319 if (slot_num == 7) {
320 snd_soc_component_update_bits(component,
321 CS35L34_TDM_TX_CTL_4_VBSTMON,
322 CS35L34_X_STATE | CS35L34_X_LOC, slot);
323 }
324
325
326 reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8);
327 bit_pos = slot - ((slot / 8) * (8));
328 snd_soc_component_update_bits(component, reg,
329 1 << bit_pos, 1 << bit_pos);
330
331 tx_mask &= ~(1 << slot);
332 slot = ffs(tx_mask) - 1;
333 slot_num++;
334 }
335
336 return 0;
337}
338
339static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w,
340 struct snd_kcontrol *kcontrol, int event)
341{
342 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
343 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
344
345 switch (event) {
346 case SND_SOC_DAPM_POST_PMU:
347 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
348 CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge);
349 usleep_range(5000, 5100);
350 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
351 CS35L34_MUTE, 0);
352 break;
353 case SND_SOC_DAPM_POST_PMD:
354 regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
355 CS35L34_BST_CVTL_MASK, 0);
356 regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
357 CS35L34_MUTE, CS35L34_MUTE);
358 usleep_range(5000, 5100);
359 break;
360 default:
361 pr_err("Invalid event = 0x%x\n", event);
362 }
363 return 0;
364}
365
366static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
367
368static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0);
369
370
371static const struct snd_kcontrol_new cs35l34_snd_controls[] = {
372 SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL,
373 0, 0x34, 0xE4, dig_vol_tlv),
374 SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL,
375 0, 0xF, 0, amp_gain_tlv),
376};
377
378
379static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w,
380 struct snd_kcontrol *kcontrol, int event)
381{
382 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
383 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
384 int ret, i;
385 unsigned int reg;
386
387 switch (event) {
388 case SND_SOC_DAPM_PRE_PMD:
389 ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL,
390 ®);
391 if (ret != 0) {
392 pr_err("%s regmap read failure %d\n", __func__, ret);
393 return ret;
394 }
395 if (reg & CS35L34_AMP_DIGSFT)
396 msleep(40);
397 else
398 usleep_range(2000, 2100);
399
400 for (i = 0; i < PDN_DONE_ATTEMPTS; i++) {
401 ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2,
402 ®);
403 if (ret != 0) {
404 pr_err("%s regmap read failure %d\n",
405 __func__, ret);
406 return ret;
407 }
408 if (reg & CS35L34_PDN_DONE)
409 break;
410
411 usleep_range(5000, 5100);
412 }
413 if (i == PDN_DONE_ATTEMPTS)
414 pr_err("%s Device did not power down properly\n",
415 __func__);
416 break;
417 default:
418 pr_err("Invalid event = 0x%x\n", event);
419 break;
420 }
421 return 0;
422}
423
424static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = {
425 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3,
426 1, 1, cs35l34_sdin_event,
427 SND_SOC_DAPM_PRE_PMU |
428 SND_SOC_DAPM_POST_PMD),
429 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1),
430
431 SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1,
432 cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD),
433
434 SND_SOC_DAPM_OUTPUT("SPK"),
435
436 SND_SOC_DAPM_INPUT("VP"),
437 SND_SOC_DAPM_INPUT("VPST"),
438 SND_SOC_DAPM_INPUT("ISENSE"),
439 SND_SOC_DAPM_INPUT("VSENSE"),
440
441 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1),
442 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1),
443 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1),
444 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1),
445 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1),
446 SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1),
447
448 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0,
449 cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU |
450 SND_SOC_DAPM_POST_PMD),
451};
452
453static const struct snd_soc_dapm_route cs35l34_audio_map[] = {
454 {"SDIN", NULL, "AMP Playback"},
455 {"BOOST", NULL, "SDIN"},
456 {"CLASS H", NULL, "BOOST"},
457 {"Main AMP", NULL, "CLASS H"},
458 {"SPK", NULL, "Main AMP"},
459
460 {"VPMON ADC", NULL, "CLASS H"},
461 {"VBSTMON ADC", NULL, "CLASS H"},
462 {"SPK", NULL, "VPMON ADC"},
463 {"SPK", NULL, "VBSTMON ADC"},
464
465 {"IMON ADC", NULL, "ISENSE"},
466 {"VMON ADC", NULL, "VSENSE"},
467 {"SDOUT", NULL, "IMON ADC"},
468 {"SDOUT", NULL, "VMON ADC"},
469 {"AMP Capture", NULL, "SDOUT"},
470
471 {"SDIN", NULL, "EXTCLK"},
472 {"SDOUT", NULL, "EXTCLK"},
473};
474
475struct cs35l34_mclk_div {
476 int mclk;
477 int srate;
478 u8 adsp_rate;
479};
480
481static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = {
482
483
484
485 {5644800, 11025, 0x1},
486 {5644800, 22050, 0x4},
487 {5644800, 44100, 0x7},
488
489 {6000000, 8000, 0x0},
490 {6000000, 11025, 0x1},
491 {6000000, 12000, 0x2},
492 {6000000, 16000, 0x3},
493 {6000000, 22050, 0x4},
494 {6000000, 24000, 0x5},
495 {6000000, 32000, 0x6},
496 {6000000, 44100, 0x7},
497 {6000000, 48000, 0x8},
498
499 {6144000, 8000, 0x0},
500 {6144000, 11025, 0x1},
501 {6144000, 12000, 0x2},
502 {6144000, 16000, 0x3},
503 {6144000, 22050, 0x4},
504 {6144000, 24000, 0x5},
505 {6144000, 32000, 0x6},
506 {6144000, 44100, 0x7},
507 {6144000, 48000, 0x8},
508};
509
510static int cs35l34_get_mclk_coeff(int mclk, int srate)
511{
512 int i;
513
514 for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) {
515 if (cs35l34_mclk_coeffs[i].mclk == mclk &&
516 cs35l34_mclk_coeffs[i].srate == srate)
517 return i;
518 }
519 return -EINVAL;
520}
521
522static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
523{
524 struct snd_soc_component *component = codec_dai->component;
525 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
526
527 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
528 case SND_SOC_DAIFMT_CBM_CFM:
529 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
530 0x80, 0x80);
531 break;
532 case SND_SOC_DAIFMT_CBS_CFS:
533 regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
534 0x80, 0x00);
535 break;
536 default:
537 return -EINVAL;
538 }
539 return 0;
540}
541
542static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream,
543 struct snd_pcm_hw_params *params,
544 struct snd_soc_dai *dai)
545{
546 struct snd_soc_component *component = dai->component;
547 struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
548 int srate = params_rate(params);
549 int ret;
550
551 int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate);
552
553 if (coeff < 0) {
554 dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n",
555 priv->mclk_int, srate);
556 return coeff;
557 }
558
559 ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
560 CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate);
561 if (ret != 0)
562 dev_err(component->dev, "Failed to set clock state %d\n", ret);
563
564 return ret;
565}
566
567static const unsigned int cs35l34_src_rates[] = {
568 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
569};
570
571
572static const struct snd_pcm_hw_constraint_list cs35l34_constraints = {
573 .count = ARRAY_SIZE(cs35l34_src_rates),
574 .list = cs35l34_src_rates,
575};
576
577static int cs35l34_pcm_startup(struct snd_pcm_substream *substream,
578 struct snd_soc_dai *dai)
579{
580
581 snd_pcm_hw_constraint_list(substream->runtime, 0,
582 SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints);
583 return 0;
584}
585
586
587static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate)
588{
589
590 struct snd_soc_component *component = dai->component;
591
592 if (tristate)
593 snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
594 CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT);
595 else
596 snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
597 CS35L34_PDN_SDOUT, 0);
598 return 0;
599}
600
601static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai,
602 int clk_id, unsigned int freq, int dir)
603{
604 struct snd_soc_component *component = dai->component;
605 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
606 unsigned int value;
607
608 switch (freq) {
609 case CS35L34_MCLK_5644:
610 value = CS35L34_MCLK_RATE_5P6448;
611 cs35l34->mclk_int = freq;
612 break;
613 case CS35L34_MCLK_6:
614 value = CS35L34_MCLK_RATE_6P0000;
615 cs35l34->mclk_int = freq;
616 break;
617 case CS35L34_MCLK_6144:
618 value = CS35L34_MCLK_RATE_6P1440;
619 cs35l34->mclk_int = freq;
620 break;
621 case CS35L34_MCLK_11289:
622 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448;
623 cs35l34->mclk_int = freq / 2;
624 break;
625 case CS35L34_MCLK_12:
626 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000;
627 cs35l34->mclk_int = freq / 2;
628 break;
629 case CS35L34_MCLK_12288:
630 value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440;
631 cs35l34->mclk_int = freq / 2;
632 break;
633 default:
634 dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq);
635 cs35l34->mclk_int = 0;
636 return -EINVAL;
637 }
638 regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL,
639 CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value);
640 return 0;
641}
642
643static const struct snd_soc_dai_ops cs35l34_ops = {
644 .startup = cs35l34_pcm_startup,
645 .set_tristate = cs35l34_set_tristate,
646 .set_fmt = cs35l34_set_dai_fmt,
647 .hw_params = cs35l34_pcm_hw_params,
648 .set_sysclk = cs35l34_dai_set_sysclk,
649 .set_tdm_slot = cs35l34_set_tdm_slot,
650};
651
652static struct snd_soc_dai_driver cs35l34_dai = {
653 .name = "cs35l34",
654 .id = 0,
655 .playback = {
656 .stream_name = "AMP Playback",
657 .channels_min = 1,
658 .channels_max = 8,
659 .rates = CS35L34_RATES,
660 .formats = CS35L34_FORMATS,
661 },
662 .capture = {
663 .stream_name = "AMP Capture",
664 .channels_min = 1,
665 .channels_max = 8,
666 .rates = CS35L34_RATES,
667 .formats = CS35L34_FORMATS,
668 },
669 .ops = &cs35l34_ops,
670 .symmetric_rate = 1,
671};
672
673static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34,
674 unsigned int inductor)
675{
676 struct snd_soc_component *component = cs35l34->component;
677
678 switch (inductor) {
679 case 1000:
680 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24);
681 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24);
682 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
683 0x4E);
684 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0);
685 break;
686 case 1200:
687 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
688 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
689 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
690 0x47);
691 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1);
692 break;
693 case 1500:
694 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
695 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
696 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
697 0x3C);
698 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2);
699 break;
700 case 2200:
701 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19);
702 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25);
703 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
704 0x23);
705 regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3);
706 break;
707 default:
708 dev_err(component->dev, "%s Invalid Inductor Value %d uH\n",
709 __func__, inductor);
710 return -EINVAL;
711 }
712 return 0;
713}
714
715static int cs35l34_probe(struct snd_soc_component *component)
716{
717 int ret = 0;
718 struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
719
720 pm_runtime_get_sync(component->dev);
721
722
723 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
724 CS35L34_OTW_ATTN_MASK, 0x8);
725
726
727
728
729 regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD);
730 regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F);
731
732
733 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
734 CS35L34_MUTE, CS35L34_MUTE);
735
736
737 if (cs35l34->pdata.boost_peak)
738 regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I,
739 CS35L34_BST_PEAK_MASK,
740 cs35l34->pdata.boost_peak);
741
742 if (cs35l34->pdata.gain_zc_disable)
743 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
744 CS35L34_GAIN_ZC_MASK, 0);
745 else
746 regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
747 CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK);
748
749 if (cs35l34->pdata.aif_half_drv)
750 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL,
751 CS35L34_ADSP_DRIVE, 0);
752
753 if (cs35l34->pdata.digsft_disable)
754 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
755 CS35L34_AMP_DIGSFT, 0);
756
757 if (cs35l34->pdata.amp_inv)
758 regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
759 CS35L34_INV, CS35L34_INV);
760
761 if (cs35l34->pdata.boost_ind)
762 ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind);
763
764 if (cs35l34->pdata.i2s_sdinloc)
765 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL,
766 CS35L34_I2S_LOC_MASK,
767 cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT);
768
769 if (cs35l34->pdata.tdm_rising_edge)
770 regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL,
771 1, 1);
772
773 pm_runtime_put_sync(component->dev);
774
775 return ret;
776}
777
778
779static const struct snd_soc_component_driver soc_component_dev_cs35l34 = {
780 .probe = cs35l34_probe,
781 .dapm_widgets = cs35l34_dapm_widgets,
782 .num_dapm_widgets = ARRAY_SIZE(cs35l34_dapm_widgets),
783 .dapm_routes = cs35l34_audio_map,
784 .num_dapm_routes = ARRAY_SIZE(cs35l34_audio_map),
785 .controls = cs35l34_snd_controls,
786 .num_controls = ARRAY_SIZE(cs35l34_snd_controls),
787 .idle_bias_on = 1,
788 .use_pmdown_time = 1,
789 .endianness = 1,
790 .non_legacy_dai_naming = 1,
791};
792
793static struct regmap_config cs35l34_regmap = {
794 .reg_bits = 8,
795 .val_bits = 8,
796
797 .max_register = CS35L34_MAX_REGISTER,
798 .reg_defaults = cs35l34_reg,
799 .num_reg_defaults = ARRAY_SIZE(cs35l34_reg),
800 .volatile_reg = cs35l34_volatile_register,
801 .readable_reg = cs35l34_readable_register,
802 .precious_reg = cs35l34_precious_register,
803 .cache_type = REGCACHE_RBTREE,
804
805 .use_single_read = true,
806 .use_single_write = true,
807};
808
809static int cs35l34_handle_of_data(struct i2c_client *i2c_client,
810 struct cs35l34_platform_data *pdata)
811{
812 struct device_node *np = i2c_client->dev.of_node;
813 unsigned int val;
814
815 if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt",
816 &val) >= 0) {
817
818 if (val > 8000 || (val < 3300 && val > 0)) {
819 dev_err(&i2c_client->dev,
820 "Invalid Boost Voltage %d mV\n", val);
821 return -EINVAL;
822 }
823 if (val == 0)
824 pdata->boost_vtge = 0;
825 else
826 pdata->boost_vtge = ((val - 3300)/100) + 1;
827 } else {
828 dev_warn(&i2c_client->dev,
829 "Boost Voltage not specified. Using VP\n");
830 }
831
832 if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
833 pdata->boost_ind = val;
834 } else {
835 dev_err(&i2c_client->dev, "Inductor not specified.\n");
836 return -EINVAL;
837 }
838
839 if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) {
840 if (val > 3840 || val < 1200) {
841 dev_err(&i2c_client->dev,
842 "Invalid Boost Peak Current %d mA\n", val);
843 return -EINVAL;
844 }
845 pdata->boost_peak = ((val - 1200)/80) + 1;
846 }
847
848 pdata->aif_half_drv = of_property_read_bool(np,
849 "cirrus,aif-half-drv");
850 pdata->digsft_disable = of_property_read_bool(np,
851 "cirrus,digsft-disable");
852
853 pdata->gain_zc_disable = of_property_read_bool(np,
854 "cirrus,gain-zc-disable");
855 pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv");
856
857 if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0)
858 pdata->i2s_sdinloc = val;
859 if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0)
860 pdata->tdm_rising_edge = val;
861
862 return 0;
863}
864
865static irqreturn_t cs35l34_irq_thread(int irq, void *data)
866{
867 struct cs35l34_private *cs35l34 = data;
868 struct snd_soc_component *component = cs35l34->component;
869 unsigned int sticky1, sticky2, sticky3, sticky4;
870 unsigned int mask1, mask2, mask3, mask4, current1;
871
872
873
874 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4);
875 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3);
876 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2);
877 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1);
878
879 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4);
880 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3);
881 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2);
882 regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1);
883
884 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
885 && !(sticky4 & ~mask4))
886 return IRQ_NONE;
887
888 regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, ¤t1);
889
890 if (sticky1 & CS35L34_CAL_ERR) {
891 dev_err(component->dev, "Cal error\n");
892
893
894 if (!(current1 & CS35L34_CAL_ERR)) {
895 dev_dbg(component->dev, "Cal error release\n");
896 regmap_update_bits(cs35l34->regmap,
897 CS35L34_PROT_RELEASE_CTL,
898 CS35L34_CAL_ERR_RLS, 0);
899 regmap_update_bits(cs35l34->regmap,
900 CS35L34_PROT_RELEASE_CTL,
901 CS35L34_CAL_ERR_RLS,
902 CS35L34_CAL_ERR_RLS);
903 regmap_update_bits(cs35l34->regmap,
904 CS35L34_PROT_RELEASE_CTL,
905 CS35L34_CAL_ERR_RLS, 0);
906
907 }
908 }
909
910 if (sticky1 & CS35L34_ALIVE_ERR)
911 dev_err(component->dev, "Alive error\n");
912
913 if (sticky1 & CS35L34_AMP_SHORT) {
914 dev_crit(component->dev, "Amp short error\n");
915
916
917 if (!(current1 & CS35L34_AMP_SHORT)) {
918 dev_dbg(component->dev,
919 "Amp short error release\n");
920 regmap_update_bits(cs35l34->regmap,
921 CS35L34_PROT_RELEASE_CTL,
922 CS35L34_SHORT_RLS, 0);
923 regmap_update_bits(cs35l34->regmap,
924 CS35L34_PROT_RELEASE_CTL,
925 CS35L34_SHORT_RLS,
926 CS35L34_SHORT_RLS);
927 regmap_update_bits(cs35l34->regmap,
928 CS35L34_PROT_RELEASE_CTL,
929 CS35L34_SHORT_RLS, 0);
930 }
931 }
932
933 if (sticky1 & CS35L34_OTW) {
934 dev_crit(component->dev, "Over temperature warning\n");
935
936
937 if (!(current1 & CS35L34_OTW)) {
938 dev_dbg(component->dev,
939 "Over temperature warning release\n");
940 regmap_update_bits(cs35l34->regmap,
941 CS35L34_PROT_RELEASE_CTL,
942 CS35L34_OTW_RLS, 0);
943 regmap_update_bits(cs35l34->regmap,
944 CS35L34_PROT_RELEASE_CTL,
945 CS35L34_OTW_RLS,
946 CS35L34_OTW_RLS);
947 regmap_update_bits(cs35l34->regmap,
948 CS35L34_PROT_RELEASE_CTL,
949 CS35L34_OTW_RLS, 0);
950 }
951 }
952
953 if (sticky1 & CS35L34_OTE) {
954 dev_crit(component->dev, "Over temperature error\n");
955
956
957 if (!(current1 & CS35L34_OTE)) {
958 dev_dbg(component->dev,
959 "Over temperature error release\n");
960 regmap_update_bits(cs35l34->regmap,
961 CS35L34_PROT_RELEASE_CTL,
962 CS35L34_OTE_RLS, 0);
963 regmap_update_bits(cs35l34->regmap,
964 CS35L34_PROT_RELEASE_CTL,
965 CS35L34_OTE_RLS,
966 CS35L34_OTE_RLS);
967 regmap_update_bits(cs35l34->regmap,
968 CS35L34_PROT_RELEASE_CTL,
969 CS35L34_OTE_RLS, 0);
970 }
971 }
972
973 if (sticky3 & CS35L34_BST_HIGH) {
974 dev_crit(component->dev, "VBST too high error; powering off!\n");
975 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
976 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
977 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
978 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
979 }
980
981 if (sticky3 & CS35L34_LBST_SHORT) {
982 dev_crit(component->dev, "LBST short error; powering off!\n");
983 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
984 CS35L34_PDN_AMP, CS35L34_PDN_AMP);
985 regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
986 CS35L34_PDN_ALL, CS35L34_PDN_ALL);
987 }
988
989 return IRQ_HANDLED;
990}
991
992static const char * const cs35l34_core_supplies[] = {
993 "VA",
994 "VP",
995};
996
997static int cs35l34_i2c_probe(struct i2c_client *i2c_client,
998 const struct i2c_device_id *id)
999{
1000 struct cs35l34_private *cs35l34;
1001 struct cs35l34_platform_data *pdata =
1002 dev_get_platdata(&i2c_client->dev);
1003 int i, devid;
1004 int ret;
1005 unsigned int reg;
1006
1007 cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
1008 if (!cs35l34)
1009 return -ENOMEM;
1010
1011 i2c_set_clientdata(i2c_client, cs35l34);
1012 cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
1013 if (IS_ERR(cs35l34->regmap)) {
1014 ret = PTR_ERR(cs35l34->regmap);
1015 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1016 return ret;
1017 }
1018
1019 cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies);
1020 for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++)
1021 cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i];
1022
1023 ret = devm_regulator_bulk_get(&i2c_client->dev,
1024 cs35l34->num_core_supplies,
1025 cs35l34->core_supplies);
1026 if (ret != 0) {
1027 dev_err(&i2c_client->dev,
1028 "Failed to request core supplies %d\n", ret);
1029 return ret;
1030 }
1031
1032 ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1033 cs35l34->core_supplies);
1034 if (ret != 0) {
1035 dev_err(&i2c_client->dev,
1036 "Failed to enable core supplies: %d\n", ret);
1037 return ret;
1038 }
1039
1040 if (pdata) {
1041 cs35l34->pdata = *pdata;
1042 } else {
1043 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1044 GFP_KERNEL);
1045 if (!pdata) {
1046 ret = -ENOMEM;
1047 goto err_regulator;
1048 }
1049
1050 if (i2c_client->dev.of_node) {
1051 ret = cs35l34_handle_of_data(i2c_client, pdata);
1052 if (ret != 0)
1053 goto err_regulator;
1054
1055 }
1056 cs35l34->pdata = *pdata;
1057 }
1058
1059 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1060 cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1061 "cs35l34", cs35l34);
1062 if (ret != 0)
1063 dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1064
1065 cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1066 "reset-gpios", GPIOD_OUT_LOW);
1067 if (IS_ERR(cs35l34->reset_gpio)) {
1068 ret = PTR_ERR(cs35l34->reset_gpio);
1069 goto err_regulator;
1070 }
1071
1072 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1073
1074 msleep(CS35L34_START_DELAY);
1075
1076 devid = cirrus_read_device_id(cs35l34->regmap, CS35L34_DEVID_AB);
1077 if (devid < 0) {
1078 ret = devid;
1079 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1080 goto err_reset;
1081 }
1082
1083 if (devid != CS35L34_CHIP_ID) {
1084 dev_err(&i2c_client->dev,
1085 "CS35l34 Device ID (%X). Expected ID %X\n",
1086 devid, CS35L34_CHIP_ID);
1087 ret = -ENODEV;
1088 goto err_reset;
1089 }
1090
1091 ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, ®);
1092 if (ret < 0) {
1093 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1094 goto err_reset;
1095 }
1096
1097 dev_info(&i2c_client->dev,
1098 "Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid,
1099 reg & 0xFF);
1100
1101
1102 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1,
1103 CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR |
1104 CS35L34_M_AMP_SHORT | CS35L34_M_OTW |
1105 CS35L34_M_OTE, 0);
1106 regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3,
1107 CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0);
1108
1109 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1110 pm_runtime_use_autosuspend(&i2c_client->dev);
1111 pm_runtime_set_active(&i2c_client->dev);
1112 pm_runtime_enable(&i2c_client->dev);
1113
1114 ret = devm_snd_soc_register_component(&i2c_client->dev,
1115 &soc_component_dev_cs35l34, &cs35l34_dai, 1);
1116 if (ret < 0) {
1117 dev_err(&i2c_client->dev,
1118 "%s: Register component failed\n", __func__);
1119 goto err_reset;
1120 }
1121
1122 return 0;
1123
1124err_reset:
1125 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1126err_regulator:
1127 regulator_bulk_disable(cs35l34->num_core_supplies,
1128 cs35l34->core_supplies);
1129
1130 return ret;
1131}
1132
1133static int cs35l34_i2c_remove(struct i2c_client *client)
1134{
1135 struct cs35l34_private *cs35l34 = i2c_get_clientdata(client);
1136
1137 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1138
1139 pm_runtime_disable(&client->dev);
1140 regulator_bulk_disable(cs35l34->num_core_supplies,
1141 cs35l34->core_supplies);
1142
1143 return 0;
1144}
1145
1146static int __maybe_unused cs35l34_runtime_resume(struct device *dev)
1147{
1148 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1149 int ret;
1150
1151 ret = regulator_bulk_enable(cs35l34->num_core_supplies,
1152 cs35l34->core_supplies);
1153
1154 if (ret != 0) {
1155 dev_err(dev, "Failed to enable core supplies: %d\n",
1156 ret);
1157 return ret;
1158 }
1159
1160 regcache_cache_only(cs35l34->regmap, false);
1161
1162 gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
1163 msleep(CS35L34_START_DELAY);
1164
1165 ret = regcache_sync(cs35l34->regmap);
1166 if (ret != 0) {
1167 dev_err(dev, "Failed to restore register cache\n");
1168 goto err;
1169 }
1170 return 0;
1171err:
1172 regcache_cache_only(cs35l34->regmap, true);
1173 regulator_bulk_disable(cs35l34->num_core_supplies,
1174 cs35l34->core_supplies);
1175
1176 return ret;
1177}
1178
1179static int __maybe_unused cs35l34_runtime_suspend(struct device *dev)
1180{
1181 struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
1182
1183 regcache_cache_only(cs35l34->regmap, true);
1184 regcache_mark_dirty(cs35l34->regmap);
1185
1186 gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
1187
1188 regulator_bulk_disable(cs35l34->num_core_supplies,
1189 cs35l34->core_supplies);
1190
1191 return 0;
1192}
1193
1194static const struct dev_pm_ops cs35l34_pm_ops = {
1195 SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend,
1196 cs35l34_runtime_resume,
1197 NULL)
1198};
1199
1200static const struct of_device_id cs35l34_of_match[] = {
1201 {.compatible = "cirrus,cs35l34"},
1202 {},
1203};
1204MODULE_DEVICE_TABLE(of, cs35l34_of_match);
1205
1206static const struct i2c_device_id cs35l34_id[] = {
1207 {"cs35l34", 0},
1208 {}
1209};
1210MODULE_DEVICE_TABLE(i2c, cs35l34_id);
1211
1212static struct i2c_driver cs35l34_i2c_driver = {
1213 .driver = {
1214 .name = "cs35l34",
1215 .pm = &cs35l34_pm_ops,
1216 .of_match_table = cs35l34_of_match,
1217
1218 },
1219 .id_table = cs35l34_id,
1220 .probe = cs35l34_i2c_probe,
1221 .remove = cs35l34_i2c_remove,
1222
1223};
1224
1225static int __init cs35l34_modinit(void)
1226{
1227 int ret;
1228
1229 ret = i2c_add_driver(&cs35l34_i2c_driver);
1230 if (ret != 0) {
1231 pr_err("Failed to register CS35l34 I2C driver: %d\n", ret);
1232 return ret;
1233 }
1234 return 0;
1235}
1236module_init(cs35l34_modinit);
1237
1238static void __exit cs35l34_exit(void)
1239{
1240 i2c_del_driver(&cs35l34_i2c_driver);
1241}
1242module_exit(cs35l34_exit);
1243
1244MODULE_DESCRIPTION("ASoC CS35l34 driver");
1245MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <Paul.Handrigan@cirrus.com>");
1246MODULE_LICENSE("GPL");
1247
