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12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/version.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/i2c.h>
19#include <linux/gpio.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22#include <linux/acpi.h>
23#include <linux/platform_device.h>
24#include <linux/property.h>
25#include <linux/regulator/consumer.h>
26#include <linux/gpio/consumer.h>
27#include <linux/of_device.h>
28#include <linux/pm_runtime.h>
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36#include <dt-bindings/sound/cs42l42.h>
37
38#include "cs42l42.h"
39#include "cirrus_legacy.h"
40
41static const struct reg_default cs42l42_reg_defaults[] = {
42 { CS42L42_FRZ_CTL, 0x00 },
43 { CS42L42_SRC_CTL, 0x10 },
44 { CS42L42_MCLK_STATUS, 0x02 },
45 { CS42L42_MCLK_CTL, 0x02 },
46 { CS42L42_SFTRAMP_RATE, 0xA4 },
47 { CS42L42_I2C_DEBOUNCE, 0x88 },
48 { CS42L42_I2C_STRETCH, 0x03 },
49 { CS42L42_I2C_TIMEOUT, 0xB7 },
50 { CS42L42_PWR_CTL1, 0xFF },
51 { CS42L42_PWR_CTL2, 0x84 },
52 { CS42L42_PWR_CTL3, 0x20 },
53 { CS42L42_RSENSE_CTL1, 0x40 },
54 { CS42L42_RSENSE_CTL2, 0x00 },
55 { CS42L42_OSC_SWITCH, 0x00 },
56 { CS42L42_OSC_SWITCH_STATUS, 0x05 },
57 { CS42L42_RSENSE_CTL3, 0x1B },
58 { CS42L42_TSENSE_CTL, 0x1B },
59 { CS42L42_TSRS_INT_DISABLE, 0x00 },
60 { CS42L42_TRSENSE_STATUS, 0x00 },
61 { CS42L42_HSDET_CTL1, 0x77 },
62 { CS42L42_HSDET_CTL2, 0x00 },
63 { CS42L42_HS_SWITCH_CTL, 0xF3 },
64 { CS42L42_HS_DET_STATUS, 0x00 },
65 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
66 { CS42L42_MCLK_SRC_SEL, 0x00 },
67 { CS42L42_SPDIF_CLK_CFG, 0x00 },
68 { CS42L42_FSYNC_PW_LOWER, 0x00 },
69 { CS42L42_FSYNC_PW_UPPER, 0x00 },
70 { CS42L42_FSYNC_P_LOWER, 0xF9 },
71 { CS42L42_FSYNC_P_UPPER, 0x00 },
72 { CS42L42_ASP_CLK_CFG, 0x00 },
73 { CS42L42_ASP_FRM_CFG, 0x10 },
74 { CS42L42_FS_RATE_EN, 0x00 },
75 { CS42L42_IN_ASRC_CLK, 0x00 },
76 { CS42L42_OUT_ASRC_CLK, 0x00 },
77 { CS42L42_PLL_DIV_CFG1, 0x00 },
78 { CS42L42_ADC_OVFL_STATUS, 0x00 },
79 { CS42L42_MIXER_STATUS, 0x00 },
80 { CS42L42_SRC_STATUS, 0x00 },
81 { CS42L42_ASP_RX_STATUS, 0x00 },
82 { CS42L42_ASP_TX_STATUS, 0x00 },
83 { CS42L42_CODEC_STATUS, 0x00 },
84 { CS42L42_DET_INT_STATUS1, 0x00 },
85 { CS42L42_DET_INT_STATUS2, 0x00 },
86 { CS42L42_SRCPL_INT_STATUS, 0x00 },
87 { CS42L42_VPMON_STATUS, 0x00 },
88 { CS42L42_PLL_LOCK_STATUS, 0x00 },
89 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
91 { CS42L42_MIXER_INT_MASK, 0x0F },
92 { CS42L42_SRC_INT_MASK, 0x0F },
93 { CS42L42_ASP_RX_INT_MASK, 0x1F },
94 { CS42L42_ASP_TX_INT_MASK, 0x0F },
95 { CS42L42_CODEC_INT_MASK, 0x03 },
96 { CS42L42_SRCPL_INT_MASK, 0xFF },
97 { CS42L42_VPMON_INT_MASK, 0x01 },
98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
100 { CS42L42_PLL_CTL1, 0x00 },
101 { CS42L42_PLL_DIV_FRAC0, 0x00 },
102 { CS42L42_PLL_DIV_FRAC1, 0x00 },
103 { CS42L42_PLL_DIV_FRAC2, 0x00 },
104 { CS42L42_PLL_DIV_INT, 0x40 },
105 { CS42L42_PLL_CTL3, 0x10 },
106 { CS42L42_PLL_CAL_RATIO, 0x80 },
107 { CS42L42_PLL_CTL4, 0x03 },
108 { CS42L42_LOAD_DET_RCSTAT, 0x00 },
109 { CS42L42_LOAD_DET_DONE, 0x00 },
110 { CS42L42_LOAD_DET_EN, 0x00 },
111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
112 { CS42L42_WAKE_CTL, 0xC0 },
113 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
114 { CS42L42_TIPSENSE_CTL, 0x02 },
115 { CS42L42_MISC_DET_CTL, 0x03 },
116 { CS42L42_MIC_DET_CTL1, 0x1F },
117 { CS42L42_MIC_DET_CTL2, 0x2F },
118 { CS42L42_DET_STATUS1, 0x00 },
119 { CS42L42_DET_STATUS2, 0x00 },
120 { CS42L42_DET_INT1_MASK, 0xE0 },
121 { CS42L42_DET_INT2_MASK, 0xFF },
122 { CS42L42_HS_BIAS_CTL, 0xC2 },
123 { CS42L42_ADC_CTL, 0x00 },
124 { CS42L42_ADC_VOLUME, 0x00 },
125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
126 { CS42L42_DAC_CTL1, 0x00 },
127 { CS42L42_DAC_CTL2, 0x02 },
128 { CS42L42_HP_CTL, 0x0D },
129 { CS42L42_CLASSH_CTL, 0x07 },
130 { CS42L42_MIXER_CHA_VOL, 0x3F },
131 { CS42L42_MIXER_ADC_VOL, 0x3F },
132 { CS42L42_MIXER_CHB_VOL, 0x3F },
133 { CS42L42_EQ_COEF_IN0, 0x22 },
134 { CS42L42_EQ_COEF_IN1, 0x00 },
135 { CS42L42_EQ_COEF_IN2, 0x00 },
136 { CS42L42_EQ_COEF_IN3, 0x00 },
137 { CS42L42_EQ_COEF_RW, 0x00 },
138 { CS42L42_EQ_COEF_OUT0, 0x00 },
139 { CS42L42_EQ_COEF_OUT1, 0x00 },
140 { CS42L42_EQ_COEF_OUT2, 0x00 },
141 { CS42L42_EQ_COEF_OUT3, 0x00 },
142 { CS42L42_EQ_INIT_STAT, 0x00 },
143 { CS42L42_EQ_START_FILT, 0x00 },
144 { CS42L42_EQ_MUTE_CTL, 0x00 },
145 { CS42L42_SP_RX_CH_SEL, 0x04 },
146 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
147 { CS42L42_SP_RX_FS, 0x8C },
148 { CS42l42_SPDIF_CH_SEL, 0x0E },
149 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
150 { CS42L42_SP_TX_FS, 0xCC },
151 { CS42L42_SPDIF_SW_CTL1, 0x3F },
152 { CS42L42_SRC_SDIN_FS, 0x40 },
153 { CS42L42_SRC_SDOUT_FS, 0x40 },
154 { CS42L42_SPDIF_CTL1, 0x01 },
155 { CS42L42_SPDIF_CTL2, 0x00 },
156 { CS42L42_SPDIF_CTL3, 0x00 },
157 { CS42L42_SPDIF_CTL4, 0x42 },
158 { CS42L42_ASP_TX_SZ_EN, 0x00 },
159 { CS42L42_ASP_TX_CH_EN, 0x00 },
160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
166 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
185 { CS42L42_SUB_REVID, 0x03 },
186};
187
188static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
189{
190 switch (reg) {
191 case CS42L42_PAGE_REGISTER:
192 case CS42L42_DEVID_AB:
193 case CS42L42_DEVID_CD:
194 case CS42L42_DEVID_E:
195 case CS42L42_FABID:
196 case CS42L42_REVID:
197 case CS42L42_FRZ_CTL:
198 case CS42L42_SRC_CTL:
199 case CS42L42_MCLK_STATUS:
200 case CS42L42_MCLK_CTL:
201 case CS42L42_SFTRAMP_RATE:
202 case CS42L42_I2C_DEBOUNCE:
203 case CS42L42_I2C_STRETCH:
204 case CS42L42_I2C_TIMEOUT:
205 case CS42L42_PWR_CTL1:
206 case CS42L42_PWR_CTL2:
207 case CS42L42_PWR_CTL3:
208 case CS42L42_RSENSE_CTL1:
209 case CS42L42_RSENSE_CTL2:
210 case CS42L42_OSC_SWITCH:
211 case CS42L42_OSC_SWITCH_STATUS:
212 case CS42L42_RSENSE_CTL3:
213 case CS42L42_TSENSE_CTL:
214 case CS42L42_TSRS_INT_DISABLE:
215 case CS42L42_TRSENSE_STATUS:
216 case CS42L42_HSDET_CTL1:
217 case CS42L42_HSDET_CTL2:
218 case CS42L42_HS_SWITCH_CTL:
219 case CS42L42_HS_DET_STATUS:
220 case CS42L42_HS_CLAMP_DISABLE:
221 case CS42L42_MCLK_SRC_SEL:
222 case CS42L42_SPDIF_CLK_CFG:
223 case CS42L42_FSYNC_PW_LOWER:
224 case CS42L42_FSYNC_PW_UPPER:
225 case CS42L42_FSYNC_P_LOWER:
226 case CS42L42_FSYNC_P_UPPER:
227 case CS42L42_ASP_CLK_CFG:
228 case CS42L42_ASP_FRM_CFG:
229 case CS42L42_FS_RATE_EN:
230 case CS42L42_IN_ASRC_CLK:
231 case CS42L42_OUT_ASRC_CLK:
232 case CS42L42_PLL_DIV_CFG1:
233 case CS42L42_ADC_OVFL_STATUS:
234 case CS42L42_MIXER_STATUS:
235 case CS42L42_SRC_STATUS:
236 case CS42L42_ASP_RX_STATUS:
237 case CS42L42_ASP_TX_STATUS:
238 case CS42L42_CODEC_STATUS:
239 case CS42L42_DET_INT_STATUS1:
240 case CS42L42_DET_INT_STATUS2:
241 case CS42L42_SRCPL_INT_STATUS:
242 case CS42L42_VPMON_STATUS:
243 case CS42L42_PLL_LOCK_STATUS:
244 case CS42L42_TSRS_PLUG_STATUS:
245 case CS42L42_ADC_OVFL_INT_MASK:
246 case CS42L42_MIXER_INT_MASK:
247 case CS42L42_SRC_INT_MASK:
248 case CS42L42_ASP_RX_INT_MASK:
249 case CS42L42_ASP_TX_INT_MASK:
250 case CS42L42_CODEC_INT_MASK:
251 case CS42L42_SRCPL_INT_MASK:
252 case CS42L42_VPMON_INT_MASK:
253 case CS42L42_PLL_LOCK_INT_MASK:
254 case CS42L42_TSRS_PLUG_INT_MASK:
255 case CS42L42_PLL_CTL1:
256 case CS42L42_PLL_DIV_FRAC0:
257 case CS42L42_PLL_DIV_FRAC1:
258 case CS42L42_PLL_DIV_FRAC2:
259 case CS42L42_PLL_DIV_INT:
260 case CS42L42_PLL_CTL3:
261 case CS42L42_PLL_CAL_RATIO:
262 case CS42L42_PLL_CTL4:
263 case CS42L42_LOAD_DET_RCSTAT:
264 case CS42L42_LOAD_DET_DONE:
265 case CS42L42_LOAD_DET_EN:
266 case CS42L42_HSBIAS_SC_AUTOCTL:
267 case CS42L42_WAKE_CTL:
268 case CS42L42_ADC_DISABLE_MUTE:
269 case CS42L42_TIPSENSE_CTL:
270 case CS42L42_MISC_DET_CTL:
271 case CS42L42_MIC_DET_CTL1:
272 case CS42L42_MIC_DET_CTL2:
273 case CS42L42_DET_STATUS1:
274 case CS42L42_DET_STATUS2:
275 case CS42L42_DET_INT1_MASK:
276 case CS42L42_DET_INT2_MASK:
277 case CS42L42_HS_BIAS_CTL:
278 case CS42L42_ADC_CTL:
279 case CS42L42_ADC_VOLUME:
280 case CS42L42_ADC_WNF_HPF_CTL:
281 case CS42L42_DAC_CTL1:
282 case CS42L42_DAC_CTL2:
283 case CS42L42_HP_CTL:
284 case CS42L42_CLASSH_CTL:
285 case CS42L42_MIXER_CHA_VOL:
286 case CS42L42_MIXER_ADC_VOL:
287 case CS42L42_MIXER_CHB_VOL:
288 case CS42L42_EQ_COEF_IN0:
289 case CS42L42_EQ_COEF_IN1:
290 case CS42L42_EQ_COEF_IN2:
291 case CS42L42_EQ_COEF_IN3:
292 case CS42L42_EQ_COEF_RW:
293 case CS42L42_EQ_COEF_OUT0:
294 case CS42L42_EQ_COEF_OUT1:
295 case CS42L42_EQ_COEF_OUT2:
296 case CS42L42_EQ_COEF_OUT3:
297 case CS42L42_EQ_INIT_STAT:
298 case CS42L42_EQ_START_FILT:
299 case CS42L42_EQ_MUTE_CTL:
300 case CS42L42_SP_RX_CH_SEL:
301 case CS42L42_SP_RX_ISOC_CTL:
302 case CS42L42_SP_RX_FS:
303 case CS42l42_SPDIF_CH_SEL:
304 case CS42L42_SP_TX_ISOC_CTL:
305 case CS42L42_SP_TX_FS:
306 case CS42L42_SPDIF_SW_CTL1:
307 case CS42L42_SRC_SDIN_FS:
308 case CS42L42_SRC_SDOUT_FS:
309 case CS42L42_SPDIF_CTL1:
310 case CS42L42_SPDIF_CTL2:
311 case CS42L42_SPDIF_CTL3:
312 case CS42L42_SPDIF_CTL4:
313 case CS42L42_ASP_TX_SZ_EN:
314 case CS42L42_ASP_TX_CH_EN:
315 case CS42L42_ASP_TX_CH_AP_RES:
316 case CS42L42_ASP_TX_CH1_BIT_MSB:
317 case CS42L42_ASP_TX_CH1_BIT_LSB:
318 case CS42L42_ASP_TX_HIZ_DLY_CFG:
319 case CS42L42_ASP_TX_CH2_BIT_MSB:
320 case CS42L42_ASP_TX_CH2_BIT_LSB:
321 case CS42L42_ASP_RX_DAI0_EN:
322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
340 case CS42L42_SUB_REVID:
341 return true;
342 default:
343 return false;
344 }
345}
346
347static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
348{
349 switch (reg) {
350 case CS42L42_DEVID_AB:
351 case CS42L42_DEVID_CD:
352 case CS42L42_DEVID_E:
353 case CS42L42_MCLK_STATUS:
354 case CS42L42_TRSENSE_STATUS:
355 case CS42L42_HS_DET_STATUS:
356 case CS42L42_ADC_OVFL_STATUS:
357 case CS42L42_MIXER_STATUS:
358 case CS42L42_SRC_STATUS:
359 case CS42L42_ASP_RX_STATUS:
360 case CS42L42_ASP_TX_STATUS:
361 case CS42L42_CODEC_STATUS:
362 case CS42L42_DET_INT_STATUS1:
363 case CS42L42_DET_INT_STATUS2:
364 case CS42L42_SRCPL_INT_STATUS:
365 case CS42L42_VPMON_STATUS:
366 case CS42L42_PLL_LOCK_STATUS:
367 case CS42L42_TSRS_PLUG_STATUS:
368 case CS42L42_LOAD_DET_RCSTAT:
369 case CS42L42_LOAD_DET_DONE:
370 case CS42L42_DET_STATUS1:
371 case CS42L42_DET_STATUS2:
372 return true;
373 default:
374 return false;
375 }
376}
377
378static const struct regmap_range_cfg cs42l42_page_range = {
379 .name = "Pages",
380 .range_min = 0,
381 .range_max = CS42L42_MAX_REGISTER,
382 .selector_reg = CS42L42_PAGE_REGISTER,
383 .selector_mask = 0xff,
384 .selector_shift = 0,
385 .window_start = 0,
386 .window_len = 256,
387};
388
389static const struct regmap_config cs42l42_regmap = {
390 .reg_bits = 8,
391 .val_bits = 8,
392
393 .readable_reg = cs42l42_readable_register,
394 .volatile_reg = cs42l42_volatile_register,
395
396 .ranges = &cs42l42_page_range,
397 .num_ranges = 1,
398
399 .max_register = CS42L42_MAX_REGISTER,
400 .reg_defaults = cs42l42_reg_defaults,
401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
402 .cache_type = REGCACHE_RBTREE,
403
404 .use_single_read = true,
405 .use_single_write = true,
406};
407
408static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
409static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
410
411static const char * const cs42l42_hpf_freq_text[] = {
412 "1.86Hz", "120Hz", "235Hz", "466Hz"
413};
414
415static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
416 CS42L42_ADC_HPF_CF_SHIFT,
417 cs42l42_hpf_freq_text);
418
419static const char * const cs42l42_wnf3_freq_text[] = {
420 "160Hz", "180Hz", "200Hz", "220Hz",
421 "240Hz", "260Hz", "280Hz", "300Hz"
422};
423
424static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
425 CS42L42_ADC_WNF_CF_SHIFT,
426 cs42l42_wnf3_freq_text);
427
428static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
429
430 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
431 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
432 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
433 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
434 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
435 CS42L42_ADC_INV_SHIFT, true, false),
436 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
437 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
438 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
439 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
440 CS42L42_ADC_WNF_EN_SHIFT, true, false),
441 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
442 CS42L42_ADC_HPF_EN_SHIFT, true, false),
443 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
444 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
445
446
447 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
448 CS42L42_DACA_INV_SHIFT, true, false),
449 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
450 CS42L42_DACB_INV_SHIFT, true, false),
451 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
452 CS42L42_DAC_HPF_EN_SHIFT, true, false),
453 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
454 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
455 0x3f, 1, mixer_tlv)
456};
457
458static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
459
460 SND_SOC_DAPM_OUTPUT("HP"),
461 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1),
462 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
463 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
464 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
465
466
467 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
468
469
470 SND_SOC_DAPM_INPUT("HS"),
471 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1),
472 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
473 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
474
475
476 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
478
479
480 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
481};
482
483static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
484
485 {"HP", NULL, "DAC"},
486 {"DAC", NULL, "MIXER"},
487 {"MIXER", NULL, "SDIN1"},
488 {"MIXER", NULL, "SDIN2"},
489 {"SDIN1", NULL, "Playback"},
490 {"SDIN2", NULL, "Playback"},
491
492
493 {"SDIN1", NULL, "ASP DAI0"},
494 {"SDIN2", NULL, "ASP DAI0"},
495 {"SDIN1", NULL, "SCLK"},
496 {"SDIN2", NULL, "SCLK"},
497
498
499 {"ADC", NULL, "HS"},
500 { "SDOUT1", NULL, "ADC" },
501 { "SDOUT2", NULL, "ADC" },
502 { "Capture", NULL, "SDOUT1" },
503 { "Capture", NULL, "SDOUT2" },
504
505
506 { "SDOUT1", NULL, "ASP DAO0" },
507 { "SDOUT2", NULL, "ASP DAO0" },
508 { "SDOUT1", NULL, "SCLK" },
509 { "SDOUT2", NULL, "SCLK" },
510 { "SDOUT1", NULL, "ASP TX EN" },
511 { "SDOUT2", NULL, "ASP TX EN" },
512};
513
514static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
515{
516 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
517
518 cs42l42->jack = jk;
519
520 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
521 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK |
522 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK,
523 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) |
524 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT));
525
526 return 0;
527}
528
529static int cs42l42_component_probe(struct snd_soc_component *component)
530{
531 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
532
533 cs42l42->component = component;
534
535 return 0;
536}
537
538static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
539 .probe = cs42l42_component_probe,
540 .set_jack = cs42l42_set_jack,
541 .dapm_widgets = cs42l42_dapm_widgets,
542 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
543 .dapm_routes = cs42l42_audio_map,
544 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
545 .controls = cs42l42_snd_controls,
546 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
547 .idle_bias_on = 1,
548 .endianness = 1,
549 .non_legacy_dai_naming = 1,
550};
551
552
553static const struct reg_sequence cs42l42_to_sclk_seq[] = {
554 {
555 .reg = CS42L42_OSC_SWITCH,
556 .def = CS42L42_SCLK_PRESENT_MASK,
557 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
558 },
559};
560
561
562static const struct reg_sequence cs42l42_to_osc_seq[] = {
563 {
564 .reg = CS42L42_OSC_SWITCH,
565 .def = 0,
566 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
567 },
568};
569
570struct cs42l42_pll_params {
571 u32 sclk;
572 u8 mclk_div;
573 u8 mclk_src_sel;
574 u8 sclk_prediv;
575 u8 pll_div_int;
576 u32 pll_div_frac;
577 u8 pll_mode;
578 u8 pll_divout;
579 u32 mclk_int;
580 u8 pll_cal_ratio;
581 u8 n;
582};
583
584
585
586
587
588static const struct cs42l42_pll_params pll_ratio_table[] = {
589 { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
590 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
591 { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
592 { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
593 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
594 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
595 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
596 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1},
597 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1},
598 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
599 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
600 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
601 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
602 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
603 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
604 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1},
605 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1},
606 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1}
607};
608
609static int cs42l42_pll_config(struct snd_soc_component *component)
610{
611 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
612 int i;
613 u32 clk;
614 u32 fsync;
615
616 if (!cs42l42->sclk)
617 clk = cs42l42->bclk;
618 else
619 clk = cs42l42->sclk;
620
621 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
622 if (pll_ratio_table[i].sclk == clk) {
623 cs42l42->pll_config = i;
624
625
626 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
627 CS42L42_INTERNAL_FS_MASK,
628 ((pll_ratio_table[i].mclk_int !=
629 12000000) &&
630 (pll_ratio_table[i].mclk_int !=
631 24000000)) <<
632 CS42L42_INTERNAL_FS_SHIFT);
633
634 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
635 CS42L42_MCLKDIV_MASK,
636 (pll_ratio_table[i].mclk_div <<
637 CS42L42_MCLKDIV_SHIFT));
638
639 fsync = clk / cs42l42->srate;
640 if (((fsync * cs42l42->srate) != clk)
641 || ((fsync % 2) != 0)) {
642 dev_err(component->dev,
643 "Unsupported sclk %d/sample rate %d\n",
644 clk,
645 cs42l42->srate);
646 return -EINVAL;
647 }
648
649 snd_soc_component_update_bits(component,
650 CS42L42_FSYNC_P_LOWER,
651 CS42L42_FSYNC_PERIOD_MASK,
652 CS42L42_FRAC0_VAL(fsync - 1) <<
653 CS42L42_FSYNC_PERIOD_SHIFT);
654 snd_soc_component_update_bits(component,
655 CS42L42_FSYNC_P_UPPER,
656 CS42L42_FSYNC_PERIOD_MASK,
657 CS42L42_FRAC1_VAL(fsync - 1) <<
658 CS42L42_FSYNC_PERIOD_SHIFT);
659
660 fsync = fsync / 2;
661 snd_soc_component_update_bits(component,
662 CS42L42_FSYNC_PW_LOWER,
663 CS42L42_FSYNC_PULSE_WIDTH_MASK,
664 CS42L42_FRAC0_VAL(fsync - 1) <<
665 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
666 snd_soc_component_update_bits(component,
667 CS42L42_FSYNC_PW_UPPER,
668 CS42L42_FSYNC_PULSE_WIDTH_MASK,
669 CS42L42_FRAC1_VAL(fsync - 1) <<
670 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
671
672 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
673 CS42L42_FS_EN_MASK,
674 (CS42L42_FS_EN_IASRC_96K |
675 CS42L42_FS_EN_OASRC_96K) <<
676 CS42L42_FS_EN_SHIFT);
677
678 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
679 CS42L42_CLK_IASRC_SEL_MASK,
680 CS42L42_CLK_IASRC_SEL_12 <<
681 CS42L42_CLK_IASRC_SEL_SHIFT);
682 snd_soc_component_update_bits(component,
683 CS42L42_OUT_ASRC_CLK,
684 CS42L42_CLK_OASRC_SEL_MASK,
685 CS42L42_CLK_OASRC_SEL_12 <<
686 CS42L42_CLK_OASRC_SEL_SHIFT);
687 if (pll_ratio_table[i].mclk_src_sel == 0) {
688
689 snd_soc_component_update_bits(component,
690 CS42L42_PLL_CTL1,
691 CS42L42_PLL_START_MASK, 0);
692 } else {
693
694 snd_soc_component_update_bits(component,
695 CS42L42_PLL_DIV_CFG1,
696 CS42L42_SCLK_PREDIV_MASK,
697 pll_ratio_table[i].sclk_prediv
698 << CS42L42_SCLK_PREDIV_SHIFT);
699 snd_soc_component_update_bits(component,
700 CS42L42_PLL_DIV_INT,
701 CS42L42_PLL_DIV_INT_MASK,
702 pll_ratio_table[i].pll_div_int
703 << CS42L42_PLL_DIV_INT_SHIFT);
704 snd_soc_component_update_bits(component,
705 CS42L42_PLL_DIV_FRAC0,
706 CS42L42_PLL_DIV_FRAC_MASK,
707 CS42L42_FRAC0_VAL(
708 pll_ratio_table[i].pll_div_frac)
709 << CS42L42_PLL_DIV_FRAC_SHIFT);
710 snd_soc_component_update_bits(component,
711 CS42L42_PLL_DIV_FRAC1,
712 CS42L42_PLL_DIV_FRAC_MASK,
713 CS42L42_FRAC1_VAL(
714 pll_ratio_table[i].pll_div_frac)
715 << CS42L42_PLL_DIV_FRAC_SHIFT);
716 snd_soc_component_update_bits(component,
717 CS42L42_PLL_DIV_FRAC2,
718 CS42L42_PLL_DIV_FRAC_MASK,
719 CS42L42_FRAC2_VAL(
720 pll_ratio_table[i].pll_div_frac)
721 << CS42L42_PLL_DIV_FRAC_SHIFT);
722 snd_soc_component_update_bits(component,
723 CS42L42_PLL_CTL4,
724 CS42L42_PLL_MODE_MASK,
725 pll_ratio_table[i].pll_mode
726 << CS42L42_PLL_MODE_SHIFT);
727 snd_soc_component_update_bits(component,
728 CS42L42_PLL_CTL3,
729 CS42L42_PLL_DIVOUT_MASK,
730 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
731 << CS42L42_PLL_DIVOUT_SHIFT);
732 if (pll_ratio_table[i].n != 1)
733 cs42l42->pll_divout = pll_ratio_table[i].pll_divout;
734 else
735 cs42l42->pll_divout = 0;
736 snd_soc_component_update_bits(component,
737 CS42L42_PLL_CAL_RATIO,
738 CS42L42_PLL_CAL_RATIO_MASK,
739 pll_ratio_table[i].pll_cal_ratio
740 << CS42L42_PLL_CAL_RATIO_SHIFT);
741 }
742 return 0;
743 }
744 }
745
746 return -EINVAL;
747}
748
749static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
750{
751 struct snd_soc_component *component = codec_dai->component;
752 u32 asp_cfg_val = 0;
753
754 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
755 case SND_SOC_DAIFMT_CBS_CFM:
756 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
757 CS42L42_ASP_MODE_SHIFT;
758 break;
759 case SND_SOC_DAIFMT_CBS_CFS:
760 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
761 CS42L42_ASP_MODE_SHIFT;
762 break;
763 default:
764 return -EINVAL;
765 }
766
767
768 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
769 case SND_SOC_DAIFMT_I2S:
770
771
772
773
774 snd_soc_component_update_bits(component,
775 CS42L42_ASP_FRM_CFG,
776 CS42L42_ASP_STP_MASK |
777 CS42L42_ASP_5050_MASK |
778 CS42L42_ASP_FSD_MASK,
779 CS42L42_ASP_5050_MASK |
780 (CS42L42_ASP_FSD_1_0 <<
781 CS42L42_ASP_FSD_SHIFT));
782 break;
783 default:
784 return -EINVAL;
785 }
786
787
788 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
789 case SND_SOC_DAIFMT_NB_NF:
790 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
791 break;
792 case SND_SOC_DAIFMT_NB_IF:
793 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
794 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
795 break;
796 case SND_SOC_DAIFMT_IB_NF:
797 break;
798 case SND_SOC_DAIFMT_IB_IF:
799 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
800 break;
801 }
802
803 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
804 CS42L42_ASP_SCPOL_MASK |
805 CS42L42_ASP_LCPOL_MASK,
806 asp_cfg_val);
807
808 return 0;
809}
810
811static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
812{
813 struct snd_soc_component *component = dai->component;
814 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
815
816
817
818
819
820
821 if (cs42l42->sclk)
822 return 0;
823
824
825 return snd_pcm_hw_constraint_minmax(substream->runtime,
826 SNDRV_PCM_HW_PARAM_RATE,
827 44100, 192000);
828}
829
830static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
831 struct snd_pcm_hw_params *params,
832 struct snd_soc_dai *dai)
833{
834 struct snd_soc_component *component = dai->component;
835 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
836 unsigned int channels = params_channels(params);
837 unsigned int width = (params_width(params) / 8) - 1;
838 unsigned int val = 0;
839
840 cs42l42->srate = params_rate(params);
841 cs42l42->bclk = snd_soc_params_to_bclk(params);
842
843
844 if (channels == 1)
845 cs42l42->bclk *= 2;
846
847
848
849
850
851 if (params_width(params) == 24)
852 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
853
854 switch(substream->stream) {
855 case SNDRV_PCM_STREAM_CAPTURE:
856 if (channels == 2) {
857 val |= CS42L42_ASP_TX_CH2_AP_MASK;
858 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT;
859 }
860 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT;
861
862 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
863 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
864 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
865 break;
866 case SNDRV_PCM_STREAM_PLAYBACK:
867 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
868
869 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
870 CS42L42_ASP_RX_CH_AP_MASK |
871 CS42L42_ASP_RX_CH_RES_MASK, val);
872
873 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
874 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
875 CS42L42_ASP_RX_CH_AP_MASK |
876 CS42L42_ASP_RX_CH_RES_MASK, val);
877
878
879 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
880 CS42L42_SP_RX_CHB_SEL_MASK,
881 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
882
883
884 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
885 CS42L42_ASP_RX0_CH_EN_MASK,
886 BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
887 BIT(CS42L42_ASP_RX0_CH2_SHIFT));
888 break;
889 default:
890 break;
891 }
892
893 return cs42l42_pll_config(component);
894}
895
896static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
897 int clk_id, unsigned int freq, int dir)
898{
899 struct snd_soc_component *component = dai->component;
900 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
901 int i;
902
903 if (freq == 0) {
904 cs42l42->sclk = 0;
905 return 0;
906 }
907
908 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
909 if (pll_ratio_table[i].sclk == freq) {
910 cs42l42->sclk = freq;
911 return 0;
912 }
913 }
914
915 dev_err(component->dev, "SCLK %u not supported\n", freq);
916
917 return -EINVAL;
918}
919
920static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
921{
922 struct snd_soc_component *component = dai->component;
923 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
924 unsigned int regval;
925 int ret;
926
927 if (mute) {
928
929 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
930 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
931 CS42L42_HP_ANA_AMUTE_MASK |
932 CS42L42_HP_ANA_BMUTE_MASK,
933 CS42L42_HP_ANA_AMUTE_MASK |
934 CS42L42_HP_ANA_BMUTE_MASK);
935
936 cs42l42->stream_use &= ~(1 << stream);
937 if(!cs42l42->stream_use) {
938
939
940
941
942
943 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
944 ARRAY_SIZE(cs42l42_to_osc_seq));
945
946
947 snd_soc_component_update_bits(component,
948 CS42L42_MCLK_SRC_SEL,
949 CS42L42_MCLK_SRC_SEL_MASK,
950 0);
951 usleep_range(100, 200);
952
953 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
954 CS42L42_PLL_START_MASK, 0);
955 }
956 } else {
957 if (!cs42l42->stream_use) {
958
959 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
960 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
961 CS42L42_PLL_START_MASK, 1);
962
963 if (cs42l42->pll_divout) {
964 usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
965 CS42L42_PLL_DIVOUT_TIME_US * 2);
966 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
967 CS42L42_PLL_DIVOUT_MASK,
968 cs42l42->pll_divout <<
969 CS42L42_PLL_DIVOUT_SHIFT);
970 }
971
972 ret = regmap_read_poll_timeout(cs42l42->regmap,
973 CS42L42_PLL_LOCK_STATUS,
974 regval,
975 (regval & 1),
976 CS42L42_PLL_LOCK_POLL_US,
977 CS42L42_PLL_LOCK_TIMEOUT_US);
978 if (ret < 0)
979 dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
980
981
982 snd_soc_component_update_bits(component,
983 CS42L42_MCLK_SRC_SEL,
984 CS42L42_MCLK_SRC_SEL_MASK,
985 CS42L42_MCLK_SRC_SEL_MASK);
986 }
987
988
989 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
990 ARRAY_SIZE(cs42l42_to_sclk_seq));
991 }
992 cs42l42->stream_use |= 1 << stream;
993
994 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
995
996 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
997 CS42L42_HP_ANA_AMUTE_MASK |
998 CS42L42_HP_ANA_BMUTE_MASK,
999 0);
1000 }
1001 }
1002
1003 return 0;
1004}
1005
1006#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1007 SNDRV_PCM_FMTBIT_S24_LE |\
1008 SNDRV_PCM_FMTBIT_S32_LE )
1009
1010static const struct snd_soc_dai_ops cs42l42_ops = {
1011 .startup = cs42l42_dai_startup,
1012 .hw_params = cs42l42_pcm_hw_params,
1013 .set_fmt = cs42l42_set_dai_fmt,
1014 .set_sysclk = cs42l42_set_sysclk,
1015 .mute_stream = cs42l42_mute_stream,
1016};
1017
1018static struct snd_soc_dai_driver cs42l42_dai = {
1019 .name = "cs42l42",
1020 .playback = {
1021 .stream_name = "Playback",
1022 .channels_min = 1,
1023 .channels_max = 2,
1024 .rates = SNDRV_PCM_RATE_8000_192000,
1025 .formats = CS42L42_FORMATS,
1026 },
1027 .capture = {
1028 .stream_name = "Capture",
1029 .channels_min = 1,
1030 .channels_max = 2,
1031 .rates = SNDRV_PCM_RATE_8000_192000,
1032 .formats = CS42L42_FORMATS,
1033 },
1034 .symmetric_rate = 1,
1035 .symmetric_sample_bits = 1,
1036 .ops = &cs42l42_ops,
1037};
1038
1039static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1040{
1041 unsigned int hs_det_status;
1042 unsigned int int_status;
1043
1044
1045 regmap_update_bits(cs42l42->regmap,
1046 CS42L42_CODEC_INT_MASK,
1047 CS42L42_PDN_DONE_MASK |
1048 CS42L42_HSDET_AUTO_DONE_MASK,
1049 (1 << CS42L42_PDN_DONE_SHIFT) |
1050 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1051
1052
1053 regmap_update_bits(cs42l42->regmap,
1054 CS42L42_HSDET_CTL2,
1055 CS42L42_HSDET_CTRL_MASK |
1056 CS42L42_HSDET_SET_MASK |
1057 CS42L42_HSBIAS_REF_MASK |
1058 CS42L42_HSDET_AUTO_TIME_MASK,
1059 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1060 (2 << CS42L42_HSDET_SET_SHIFT) |
1061 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1062 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1063
1064
1065 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1066
1067 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1068 CS42L42_HSDET_TYPE_SHIFT;
1069
1070
1071 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1072 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1073
1074 regmap_update_bits(cs42l42->regmap,
1075 CS42L42_HSBIAS_SC_AUTOCTL,
1076 CS42L42_HSBIAS_SENSE_EN_MASK |
1077 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1078 CS42L42_TIP_SENSE_EN_MASK |
1079 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1080 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1081 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1082 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1083 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1084
1085
1086 regmap_update_bits(cs42l42->regmap,
1087 CS42L42_MIC_DET_CTL1,
1088 CS42L42_LATCH_TO_VP_MASK |
1089 CS42L42_EVENT_STAT_SEL_MASK |
1090 CS42L42_HS_DET_LEVEL_MASK,
1091 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1092 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1093 (cs42l42->bias_thresholds[0] <<
1094 CS42L42_HS_DET_LEVEL_SHIFT));
1095
1096
1097 regmap_update_bits(cs42l42->regmap,
1098 CS42L42_HSBIAS_SC_AUTOCTL,
1099 CS42L42_HSBIAS_SENSE_EN_MASK |
1100 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1101 CS42L42_TIP_SENSE_EN_MASK |
1102 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1103 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1104 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1105 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1106 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1107
1108
1109 regmap_update_bits(cs42l42->regmap,
1110 CS42L42_MISC_DET_CTL,
1111 CS42L42_DETECT_MODE_MASK |
1112 CS42L42_HSBIAS_CTL_MASK |
1113 CS42L42_PDN_MIC_LVL_DET_MASK,
1114 (0 << CS42L42_DETECT_MODE_SHIFT) |
1115 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1116 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1117
1118 msleep(cs42l42->btn_det_init_dbnce);
1119
1120
1121 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1122 &int_status);
1123
1124
1125 regmap_update_bits(cs42l42->regmap,
1126 CS42L42_DET_INT2_MASK,
1127 CS42L42_M_DETECT_TF_MASK |
1128 CS42L42_M_DETECT_FT_MASK |
1129 CS42L42_M_HSBIAS_HIZ_MASK |
1130 CS42L42_M_SHORT_RLS_MASK |
1131 CS42L42_M_SHORT_DET_MASK,
1132 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1133 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1134 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1135 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1136 (1 << CS42L42_M_SHORT_DET_SHIFT));
1137 } else {
1138
1139 regmap_update_bits(cs42l42->regmap,
1140 CS42L42_MISC_DET_CTL,
1141 CS42L42_DETECT_MODE_MASK |
1142 CS42L42_HSBIAS_CTL_MASK |
1143 CS42L42_PDN_MIC_LVL_DET_MASK,
1144 (0 << CS42L42_DETECT_MODE_SHIFT) |
1145 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1146 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1147 }
1148
1149 regmap_update_bits(cs42l42->regmap,
1150 CS42L42_DAC_CTL2,
1151 CS42L42_HPOUT_PULLDOWN_MASK |
1152 CS42L42_HPOUT_LOAD_MASK |
1153 CS42L42_HPOUT_CLAMP_MASK |
1154 CS42L42_DAC_HPF_EN_MASK |
1155 CS42L42_DAC_MON_EN_MASK,
1156 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1157 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1158 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1159 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1160 (0 << CS42L42_DAC_MON_EN_SHIFT));
1161
1162
1163 regmap_update_bits(cs42l42->regmap,
1164 CS42L42_TSRS_PLUG_INT_MASK,
1165 CS42L42_RS_PLUG_MASK |
1166 CS42L42_RS_UNPLUG_MASK |
1167 CS42L42_TS_PLUG_MASK |
1168 CS42L42_TS_UNPLUG_MASK,
1169 (1 << CS42L42_RS_PLUG_SHIFT) |
1170 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1171 (0 << CS42L42_TS_PLUG_SHIFT) |
1172 (0 << CS42L42_TS_UNPLUG_SHIFT));
1173}
1174
1175static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1176{
1177
1178 regmap_update_bits(cs42l42->regmap,
1179 CS42L42_TSRS_PLUG_INT_MASK,
1180 CS42L42_RS_PLUG_MASK |
1181 CS42L42_RS_UNPLUG_MASK |
1182 CS42L42_TS_PLUG_MASK |
1183 CS42L42_TS_UNPLUG_MASK,
1184 (1 << CS42L42_RS_PLUG_SHIFT) |
1185 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1186 (1 << CS42L42_TS_PLUG_SHIFT) |
1187 (1 << CS42L42_TS_UNPLUG_SHIFT));
1188
1189
1190 regmap_update_bits(cs42l42->regmap,
1191 CS42L42_MISC_DET_CTL,
1192 CS42L42_DETECT_MODE_MASK |
1193 CS42L42_HSBIAS_CTL_MASK |
1194 CS42L42_PDN_MIC_LVL_DET_MASK,
1195 (0 << CS42L42_DETECT_MODE_SHIFT) |
1196 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1197 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1198
1199
1200 regmap_update_bits(cs42l42->regmap,
1201 CS42L42_HSBIAS_SC_AUTOCTL,
1202 CS42L42_HSBIAS_SENSE_EN_MASK |
1203 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1204 CS42L42_TIP_SENSE_EN_MASK |
1205 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1206 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1207 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1208 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1209 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1210
1211
1212 regmap_update_bits(cs42l42->regmap,
1213 CS42L42_HSDET_CTL2,
1214 CS42L42_HSDET_CTRL_MASK |
1215 CS42L42_HSDET_SET_MASK |
1216 CS42L42_HSBIAS_REF_MASK |
1217 CS42L42_HSDET_AUTO_TIME_MASK,
1218 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1219 (2 << CS42L42_HSDET_SET_SHIFT) |
1220 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1221 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1222
1223 regmap_update_bits(cs42l42->regmap,
1224 CS42L42_DAC_CTL2,
1225 CS42L42_HPOUT_PULLDOWN_MASK |
1226 CS42L42_HPOUT_LOAD_MASK |
1227 CS42L42_HPOUT_CLAMP_MASK |
1228 CS42L42_DAC_HPF_EN_MASK |
1229 CS42L42_DAC_MON_EN_MASK,
1230 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1231 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1232 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1233 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1234 (1 << CS42L42_DAC_MON_EN_SHIFT));
1235
1236
1237 regmap_update_bits(cs42l42->regmap,
1238 CS42L42_MISC_DET_CTL,
1239 CS42L42_DETECT_MODE_MASK |
1240 CS42L42_HSBIAS_CTL_MASK |
1241 CS42L42_PDN_MIC_LVL_DET_MASK,
1242 (0 << CS42L42_DETECT_MODE_SHIFT) |
1243 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1244 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1245
1246
1247 msleep(cs42l42->hs_bias_ramp_time);
1248
1249
1250 regmap_update_bits(cs42l42->regmap,
1251 CS42L42_CODEC_INT_MASK,
1252 CS42L42_PDN_DONE_MASK |
1253 CS42L42_HSDET_AUTO_DONE_MASK,
1254 (1 << CS42L42_PDN_DONE_SHIFT) |
1255 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1256
1257
1258 regmap_update_bits(cs42l42->regmap,
1259 CS42L42_HSDET_CTL2,
1260 CS42L42_HSDET_CTRL_MASK |
1261 CS42L42_HSDET_SET_MASK |
1262 CS42L42_HSBIAS_REF_MASK |
1263 CS42L42_HSDET_AUTO_TIME_MASK,
1264 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1265 (2 << CS42L42_HSDET_SET_SHIFT) |
1266 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1267 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1268}
1269
1270static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1271{
1272
1273 regmap_update_bits(cs42l42->regmap,
1274 CS42L42_DET_INT2_MASK,
1275 CS42L42_M_DETECT_TF_MASK |
1276 CS42L42_M_DETECT_FT_MASK |
1277 CS42L42_M_HSBIAS_HIZ_MASK |
1278 CS42L42_M_SHORT_RLS_MASK |
1279 CS42L42_M_SHORT_DET_MASK,
1280 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1281 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1282 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1283 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1284 (1 << CS42L42_M_SHORT_DET_SHIFT));
1285
1286
1287 regmap_update_bits(cs42l42->regmap,
1288 CS42L42_MISC_DET_CTL,
1289 CS42L42_DETECT_MODE_MASK |
1290 CS42L42_HSBIAS_CTL_MASK |
1291 CS42L42_PDN_MIC_LVL_DET_MASK,
1292 (0 << CS42L42_DETECT_MODE_SHIFT) |
1293 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1294 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1295
1296
1297 regmap_update_bits(cs42l42->regmap,
1298 CS42L42_HSBIAS_SC_AUTOCTL,
1299 CS42L42_HSBIAS_SENSE_EN_MASK |
1300 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1301 CS42L42_TIP_SENSE_EN_MASK |
1302 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1303 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1304 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1305 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1306 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1307
1308
1309 regmap_update_bits(cs42l42->regmap,
1310 CS42L42_HSDET_CTL2,
1311 CS42L42_HSDET_CTRL_MASK |
1312 CS42L42_HSDET_SET_MASK |
1313 CS42L42_HSBIAS_REF_MASK |
1314 CS42L42_HSDET_AUTO_TIME_MASK,
1315 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1316 (2 << CS42L42_HSDET_SET_SHIFT) |
1317 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1318 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1319}
1320
1321static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1322{
1323 int bias_level;
1324 unsigned int detect_status;
1325
1326
1327 regmap_update_bits(cs42l42->regmap,
1328 CS42L42_DET_INT2_MASK,
1329 CS42L42_M_DETECT_TF_MASK |
1330 CS42L42_M_DETECT_FT_MASK |
1331 CS42L42_M_HSBIAS_HIZ_MASK |
1332 CS42L42_M_SHORT_RLS_MASK |
1333 CS42L42_M_SHORT_DET_MASK,
1334 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1335 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1336 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1337 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1338 (1 << CS42L42_M_SHORT_DET_SHIFT));
1339
1340 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1341 cs42l42->btn_det_event_dbnce * 2000);
1342
1343
1344 bias_level = 1;
1345 do {
1346
1347 regmap_update_bits(cs42l42->regmap,
1348 CS42L42_MIC_DET_CTL1,
1349 CS42L42_LATCH_TO_VP_MASK |
1350 CS42L42_EVENT_STAT_SEL_MASK |
1351 CS42L42_HS_DET_LEVEL_MASK,
1352 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1353 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1354 (cs42l42->bias_thresholds[bias_level] <<
1355 CS42L42_HS_DET_LEVEL_SHIFT));
1356
1357 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1358 &detect_status);
1359 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1360 (++bias_level < CS42L42_NUM_BIASES));
1361
1362 switch (bias_level) {
1363 case 1:
1364 bias_level = SND_JACK_BTN_2;
1365 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1366 break;
1367 case 2:
1368 bias_level = SND_JACK_BTN_1;
1369 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1370 break;
1371 case 3:
1372 bias_level = SND_JACK_BTN_3;
1373 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1374 break;
1375 case 4:
1376 bias_level = SND_JACK_BTN_0;
1377 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1378 break;
1379 default:
1380 bias_level = 0;
1381 break;
1382 }
1383
1384
1385 regmap_update_bits(cs42l42->regmap,
1386 CS42L42_MIC_DET_CTL1,
1387 CS42L42_LATCH_TO_VP_MASK |
1388 CS42L42_EVENT_STAT_SEL_MASK |
1389 CS42L42_HS_DET_LEVEL_MASK,
1390 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1391 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1392 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1393
1394
1395 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1396 &detect_status);
1397
1398
1399 regmap_update_bits(cs42l42->regmap,
1400 CS42L42_DET_INT2_MASK,
1401 CS42L42_M_DETECT_TF_MASK |
1402 CS42L42_M_DETECT_FT_MASK |
1403 CS42L42_M_HSBIAS_HIZ_MASK |
1404 CS42L42_M_SHORT_RLS_MASK |
1405 CS42L42_M_SHORT_DET_MASK,
1406 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1407 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1408 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1409 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1410 (1 << CS42L42_M_SHORT_DET_SHIFT));
1411
1412 return bias_level;
1413}
1414
1415struct cs42l42_irq_params {
1416 u16 status_addr;
1417 u16 mask_addr;
1418 u8 mask;
1419};
1420
1421static const struct cs42l42_irq_params irq_params_table[] = {
1422 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1423 CS42L42_ADC_OVFL_VAL_MASK},
1424 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1425 CS42L42_MIXER_VAL_MASK},
1426 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1427 CS42L42_SRC_VAL_MASK},
1428 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1429 CS42L42_ASP_RX_VAL_MASK},
1430 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1431 CS42L42_ASP_TX_VAL_MASK},
1432 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1433 CS42L42_CODEC_VAL_MASK},
1434 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1435 CS42L42_DET_INT_VAL1_MASK},
1436 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1437 CS42L42_DET_INT_VAL2_MASK},
1438 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1439 CS42L42_SRCPL_VAL_MASK},
1440 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1441 CS42L42_VPMON_VAL_MASK},
1442 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1443 CS42L42_PLL_LOCK_VAL_MASK},
1444 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1445 CS42L42_TSRS_PLUG_VAL_MASK}
1446};
1447
1448static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1449{
1450 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1451 struct snd_soc_component *component = cs42l42->component;
1452 unsigned int stickies[12];
1453 unsigned int masks[12];
1454 unsigned int current_plug_status;
1455 unsigned int current_button_status;
1456 unsigned int i;
1457 int report = 0;
1458
1459
1460
1461 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1462 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1463 &(stickies[i]));
1464 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1465 &(masks[i]));
1466 stickies[i] = stickies[i] & (~masks[i]) &
1467 irq_params_table[i].mask;
1468 }
1469
1470
1471 current_plug_status = (stickies[11] &
1472 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1473 CS42L42_TS_PLUG_SHIFT;
1474
1475
1476 current_button_status = stickies[7] &
1477 (CS42L42_M_DETECT_TF_MASK |
1478 CS42L42_M_DETECT_FT_MASK |
1479 CS42L42_M_HSBIAS_HIZ_MASK);
1480
1481
1482 if ((~masks[5]) & irq_params_table[5].mask) {
1483 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1484 cs42l42_process_hs_type_detect(cs42l42);
1485 switch(cs42l42->hs_type){
1486 case CS42L42_PLUG_CTIA:
1487 case CS42L42_PLUG_OMTP:
1488 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1489 SND_JACK_HEADSET);
1490 break;
1491 case CS42L42_PLUG_HEADPHONE:
1492 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1493 SND_JACK_HEADPHONE);
1494 break;
1495 default:
1496 break;
1497 }
1498 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1499 }
1500 }
1501
1502
1503 if ((~masks[11]) & irq_params_table[11].mask) {
1504 switch (current_plug_status) {
1505 case CS42L42_TS_PLUG:
1506 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1507 cs42l42->plug_state = CS42L42_TS_PLUG;
1508 cs42l42_init_hs_type_detect(cs42l42);
1509 }
1510 break;
1511
1512 case CS42L42_TS_UNPLUG:
1513 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1514 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1515 cs42l42_cancel_hs_type_detect(cs42l42);
1516
1517 switch(cs42l42->hs_type){
1518 case CS42L42_PLUG_CTIA:
1519 case CS42L42_PLUG_OMTP:
1520 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1521 break;
1522 case CS42L42_PLUG_HEADPHONE:
1523 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1524 break;
1525 default:
1526 break;
1527 }
1528 snd_soc_jack_report(cs42l42->jack, 0,
1529 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1530 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1531
1532 dev_dbg(component->dev, "Unplug event\n");
1533 }
1534 break;
1535
1536 default:
1537 if (cs42l42->plug_state != CS42L42_TS_TRANS)
1538 cs42l42->plug_state = CS42L42_TS_TRANS;
1539 }
1540 }
1541
1542
1543 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1544 if (!(current_button_status &
1545 CS42L42_M_HSBIAS_HIZ_MASK)) {
1546
1547 if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1548 dev_dbg(component->dev, "Button released\n");
1549 report = 0;
1550 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1551 report = cs42l42_handle_button_press(cs42l42);
1552
1553 }
1554 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1555 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1556 }
1557 }
1558
1559 return IRQ_HANDLED;
1560}
1561
1562static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1563{
1564 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1565 CS42L42_ADC_OVFL_MASK,
1566 (1 << CS42L42_ADC_OVFL_SHIFT));
1567
1568 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1569 CS42L42_MIX_CHB_OVFL_MASK |
1570 CS42L42_MIX_CHA_OVFL_MASK |
1571 CS42L42_EQ_OVFL_MASK |
1572 CS42L42_EQ_BIQUAD_OVFL_MASK,
1573 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1574 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1575 (1 << CS42L42_EQ_OVFL_SHIFT) |
1576 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1577
1578 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1579 CS42L42_SRC_ILK_MASK |
1580 CS42L42_SRC_OLK_MASK |
1581 CS42L42_SRC_IUNLK_MASK |
1582 CS42L42_SRC_OUNLK_MASK,
1583 (1 << CS42L42_SRC_ILK_SHIFT) |
1584 (1 << CS42L42_SRC_OLK_SHIFT) |
1585 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1586 (1 << CS42L42_SRC_OUNLK_SHIFT));
1587
1588 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1589 CS42L42_ASPRX_NOLRCK_MASK |
1590 CS42L42_ASPRX_EARLY_MASK |
1591 CS42L42_ASPRX_LATE_MASK |
1592 CS42L42_ASPRX_ERROR_MASK |
1593 CS42L42_ASPRX_OVLD_MASK,
1594 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1595 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1596 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1597 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1598 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1599
1600 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1601 CS42L42_ASPTX_NOLRCK_MASK |
1602 CS42L42_ASPTX_EARLY_MASK |
1603 CS42L42_ASPTX_LATE_MASK |
1604 CS42L42_ASPTX_SMERROR_MASK,
1605 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1606 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1607 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1608 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1609
1610 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1611 CS42L42_PDN_DONE_MASK |
1612 CS42L42_HSDET_AUTO_DONE_MASK,
1613 (1 << CS42L42_PDN_DONE_SHIFT) |
1614 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1615
1616 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1617 CS42L42_SRCPL_ADC_LK_MASK |
1618 CS42L42_SRCPL_DAC_LK_MASK |
1619 CS42L42_SRCPL_ADC_UNLK_MASK |
1620 CS42L42_SRCPL_DAC_UNLK_MASK,
1621 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1622 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1623 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1624 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1625
1626 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1627 CS42L42_TIP_SENSE_UNPLUG_MASK |
1628 CS42L42_TIP_SENSE_PLUG_MASK |
1629 CS42L42_HSBIAS_SENSE_MASK,
1630 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1631 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1632 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1633
1634 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1635 CS42L42_M_DETECT_TF_MASK |
1636 CS42L42_M_DETECT_FT_MASK |
1637 CS42L42_M_HSBIAS_HIZ_MASK |
1638 CS42L42_M_SHORT_RLS_MASK |
1639 CS42L42_M_SHORT_DET_MASK,
1640 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1641 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1642 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1643 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1644 (1 << CS42L42_M_SHORT_DET_SHIFT));
1645
1646 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1647 CS42L42_VPMON_MASK,
1648 (1 << CS42L42_VPMON_SHIFT));
1649
1650 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1651 CS42L42_PLL_LOCK_MASK,
1652 (1 << CS42L42_PLL_LOCK_SHIFT));
1653
1654 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1655 CS42L42_RS_PLUG_MASK |
1656 CS42L42_RS_UNPLUG_MASK |
1657 CS42L42_TS_PLUG_MASK |
1658 CS42L42_TS_UNPLUG_MASK,
1659 (1 << CS42L42_RS_PLUG_SHIFT) |
1660 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1661 (1 << CS42L42_TS_PLUG_SHIFT) |
1662 (1 << CS42L42_TS_UNPLUG_SHIFT));
1663}
1664
1665static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1666{
1667 unsigned int reg;
1668
1669 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1670
1671
1672 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1673 CS42L42_LATCH_TO_VP_MASK |
1674 CS42L42_EVENT_STAT_SEL_MASK |
1675 CS42L42_HS_DET_LEVEL_MASK,
1676 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1677 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1678 (cs42l42->bias_thresholds[0] <<
1679 CS42L42_HS_DET_LEVEL_SHIFT));
1680
1681
1682 regmap_update_bits(cs42l42->regmap,
1683 CS42L42_HS_CLAMP_DISABLE,
1684 CS42L42_HS_CLAMP_DISABLE_MASK,
1685 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1686
1687
1688 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1689 CS42L42_TIP_SENSE_CTRL_MASK |
1690 CS42L42_TIP_SENSE_INV_MASK |
1691 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1692 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1693 (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1694 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1695
1696
1697 regmap_read(cs42l42->regmap,
1698 CS42L42_TSRS_PLUG_STATUS,
1699 ®);
1700 cs42l42->plug_state = (((char) reg) &
1701 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1702 CS42L42_TS_PLUG_SHIFT;
1703}
1704
1705static const unsigned int threshold_defaults[] = {
1706 CS42L42_HS_DET_LEVEL_15,
1707 CS42L42_HS_DET_LEVEL_8,
1708 CS42L42_HS_DET_LEVEL_4,
1709 CS42L42_HS_DET_LEVEL_1
1710};
1711
1712static int cs42l42_handle_device_data(struct device *dev,
1713 struct cs42l42_private *cs42l42)
1714{
1715 unsigned int val;
1716 u32 thresholds[CS42L42_NUM_BIASES];
1717 int ret;
1718 int i;
1719
1720 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1721 if (!ret) {
1722 switch (val) {
1723 case CS42L42_TS_INV_EN:
1724 case CS42L42_TS_INV_DIS:
1725 cs42l42->ts_inv = val;
1726 break;
1727 default:
1728 dev_err(dev,
1729 "Wrong cirrus,ts-inv DT value %d\n",
1730 val);
1731 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1732 }
1733 } else {
1734 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1735 }
1736
1737 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1738 CS42L42_TS_INV_MASK,
1739 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1740
1741 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1742 if (!ret) {
1743 switch (val) {
1744 case CS42L42_TS_DBNCE_0:
1745 case CS42L42_TS_DBNCE_125:
1746 case CS42L42_TS_DBNCE_250:
1747 case CS42L42_TS_DBNCE_500:
1748 case CS42L42_TS_DBNCE_750:
1749 case CS42L42_TS_DBNCE_1000:
1750 case CS42L42_TS_DBNCE_1250:
1751 case CS42L42_TS_DBNCE_1500:
1752 cs42l42->ts_dbnc_rise = val;
1753 break;
1754 default:
1755 dev_err(dev,
1756 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1757 val);
1758 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1759 }
1760 } else {
1761 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1762 }
1763
1764 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1765 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1766 (cs42l42->ts_dbnc_rise <<
1767 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1768
1769 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1770 if (!ret) {
1771 switch (val) {
1772 case CS42L42_TS_DBNCE_0:
1773 case CS42L42_TS_DBNCE_125:
1774 case CS42L42_TS_DBNCE_250:
1775 case CS42L42_TS_DBNCE_500:
1776 case CS42L42_TS_DBNCE_750:
1777 case CS42L42_TS_DBNCE_1000:
1778 case CS42L42_TS_DBNCE_1250:
1779 case CS42L42_TS_DBNCE_1500:
1780 cs42l42->ts_dbnc_fall = val;
1781 break;
1782 default:
1783 dev_err(dev,
1784 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1785 val);
1786 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1787 }
1788 } else {
1789 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1790 }
1791
1792 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1793 CS42L42_TS_FALL_DBNCE_TIME_MASK,
1794 (cs42l42->ts_dbnc_fall <<
1795 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1796
1797 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1798 if (!ret) {
1799 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1800 cs42l42->btn_det_init_dbnce = val;
1801 else {
1802 dev_err(dev,
1803 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1804 val);
1805 cs42l42->btn_det_init_dbnce =
1806 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1807 }
1808 } else {
1809 cs42l42->btn_det_init_dbnce =
1810 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1811 }
1812
1813 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1814 if (!ret) {
1815 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1816 cs42l42->btn_det_event_dbnce = val;
1817 else {
1818 dev_err(dev,
1819 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1820 cs42l42->btn_det_event_dbnce =
1821 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1822 }
1823 } else {
1824 cs42l42->btn_det_event_dbnce =
1825 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1826 }
1827
1828 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1829 thresholds, ARRAY_SIZE(thresholds));
1830 if (!ret) {
1831 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1832 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1833 cs42l42->bias_thresholds[i] = thresholds[i];
1834 else {
1835 dev_err(dev,
1836 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1837 thresholds[i]);
1838 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1839 }
1840 }
1841 } else {
1842 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1843 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1844 }
1845
1846 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
1847 if (!ret) {
1848 switch (val) {
1849 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1850 cs42l42->hs_bias_ramp_rate = val;
1851 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1852 break;
1853 case CS42L42_HSBIAS_RAMP_FAST:
1854 cs42l42->hs_bias_ramp_rate = val;
1855 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1856 break;
1857 case CS42L42_HSBIAS_RAMP_SLOW:
1858 cs42l42->hs_bias_ramp_rate = val;
1859 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1860 break;
1861 case CS42L42_HSBIAS_RAMP_SLOWEST:
1862 cs42l42->hs_bias_ramp_rate = val;
1863 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1864 break;
1865 default:
1866 dev_err(dev,
1867 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1868 val);
1869 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1870 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1871 }
1872 } else {
1873 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1874 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1875 }
1876
1877 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1878 CS42L42_HSBIAS_RAMP_MASK,
1879 (cs42l42->hs_bias_ramp_rate <<
1880 CS42L42_HSBIAS_RAMP_SHIFT));
1881
1882 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
1883 cs42l42->hs_bias_sense_en = 0;
1884 else
1885 cs42l42->hs_bias_sense_en = 1;
1886
1887 return 0;
1888}
1889
1890static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1891 const struct i2c_device_id *id)
1892{
1893 struct cs42l42_private *cs42l42;
1894 int ret, i, devid;
1895 unsigned int reg;
1896
1897 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1898 GFP_KERNEL);
1899 if (!cs42l42)
1900 return -ENOMEM;
1901
1902 i2c_set_clientdata(i2c_client, cs42l42);
1903
1904 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1905 if (IS_ERR(cs42l42->regmap)) {
1906 ret = PTR_ERR(cs42l42->regmap);
1907 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1908 return ret;
1909 }
1910
1911 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1912 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1913
1914 ret = devm_regulator_bulk_get(&i2c_client->dev,
1915 ARRAY_SIZE(cs42l42->supplies),
1916 cs42l42->supplies);
1917 if (ret != 0) {
1918 dev_err(&i2c_client->dev,
1919 "Failed to request supplies: %d\n", ret);
1920 return ret;
1921 }
1922
1923 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1924 cs42l42->supplies);
1925 if (ret != 0) {
1926 dev_err(&i2c_client->dev,
1927 "Failed to enable supplies: %d\n", ret);
1928 return ret;
1929 }
1930
1931
1932 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1933 "reset", GPIOD_OUT_LOW);
1934 if (IS_ERR(cs42l42->reset_gpio)) {
1935 ret = PTR_ERR(cs42l42->reset_gpio);
1936 goto err_disable;
1937 }
1938
1939 if (cs42l42->reset_gpio) {
1940 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1941 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1942 }
1943 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1944
1945
1946 ret = devm_request_threaded_irq(&i2c_client->dev,
1947 i2c_client->irq,
1948 NULL, cs42l42_irq_thread,
1949 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1950 "cs42l42", cs42l42);
1951
1952 if (ret != 0)
1953 dev_err(&i2c_client->dev,
1954 "Failed to request IRQ: %d\n", ret);
1955
1956
1957 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
1958 if (devid < 0) {
1959 ret = devid;
1960 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1961 goto err_disable;
1962 }
1963
1964 if (devid != CS42L42_CHIP_ID) {
1965 ret = -ENODEV;
1966 dev_err(&i2c_client->dev,
1967 "CS42L42 Device ID (%X). Expected %X\n",
1968 devid, CS42L42_CHIP_ID);
1969 goto err_disable;
1970 }
1971
1972 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
1973 if (ret < 0) {
1974 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1975 goto err_disable;
1976 }
1977
1978 dev_info(&i2c_client->dev,
1979 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1980
1981
1982 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1983 CS42L42_ASP_DAO_PDN_MASK |
1984 CS42L42_ASP_DAI_PDN_MASK |
1985 CS42L42_MIXER_PDN_MASK |
1986 CS42L42_EQ_PDN_MASK |
1987 CS42L42_HP_PDN_MASK |
1988 CS42L42_ADC_PDN_MASK |
1989 CS42L42_PDN_ALL_MASK,
1990 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1991 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1992 (1 << CS42L42_MIXER_PDN_SHIFT) |
1993 (1 << CS42L42_EQ_PDN_SHIFT) |
1994 (1 << CS42L42_HP_PDN_SHIFT) |
1995 (1 << CS42L42_ADC_PDN_SHIFT) |
1996 (0 << CS42L42_PDN_ALL_SHIFT));
1997
1998 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
1999 if (ret != 0)
2000 goto err_disable;
2001
2002
2003 cs42l42_setup_hs_type_detect(cs42l42);
2004
2005
2006 cs42l42_set_interrupt_masks(cs42l42);
2007
2008
2009 ret = devm_snd_soc_register_component(&i2c_client->dev,
2010 &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2011 if (ret < 0)
2012 goto err_disable;
2013 return 0;
2014
2015err_disable:
2016 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2017 cs42l42->supplies);
2018 return ret;
2019}
2020
2021static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2022{
2023 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2024
2025 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
2026 pm_runtime_suspend(&i2c_client->dev);
2027 pm_runtime_disable(&i2c_client->dev);
2028
2029 return 0;
2030}
2031
2032#ifdef CONFIG_PM
2033static int cs42l42_runtime_suspend(struct device *dev)
2034{
2035 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2036
2037 regcache_cache_only(cs42l42->regmap, true);
2038 regcache_mark_dirty(cs42l42->regmap);
2039
2040
2041 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2042
2043
2044 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2045 cs42l42->supplies);
2046
2047 return 0;
2048}
2049
2050static int cs42l42_runtime_resume(struct device *dev)
2051{
2052 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2053 int ret;
2054
2055
2056 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2057 cs42l42->supplies);
2058 if (ret != 0) {
2059 dev_err(dev, "Failed to enable supplies: %d\n",
2060 ret);
2061 return ret;
2062 }
2063
2064 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2065 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2066
2067 regcache_cache_only(cs42l42->regmap, false);
2068 regcache_sync(cs42l42->regmap);
2069
2070 return 0;
2071}
2072#endif
2073
2074static const struct dev_pm_ops cs42l42_runtime_pm = {
2075 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
2076 NULL)
2077};
2078
2079#ifdef CONFIG_OF
2080static const struct of_device_id cs42l42_of_match[] = {
2081 { .compatible = "cirrus,cs42l42", },
2082 {}
2083};
2084MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2085#endif
2086
2087#ifdef CONFIG_ACPI
2088static const struct acpi_device_id cs42l42_acpi_match[] = {
2089 {"10134242", 0,},
2090 {}
2091};
2092MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2093#endif
2094
2095static const struct i2c_device_id cs42l42_id[] = {
2096 {"cs42l42", 0},
2097 {}
2098};
2099
2100MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2101
2102static struct i2c_driver cs42l42_i2c_driver = {
2103 .driver = {
2104 .name = "cs42l42",
2105 .pm = &cs42l42_runtime_pm,
2106 .of_match_table = of_match_ptr(cs42l42_of_match),
2107 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2108 },
2109 .id_table = cs42l42_id,
2110 .probe = cs42l42_i2c_probe,
2111 .remove = cs42l42_i2c_remove,
2112};
2113
2114module_i2c_driver(cs42l42_i2c_driver);
2115
2116MODULE_DESCRIPTION("ASoC CS42L42 driver");
2117MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2118MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2119MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2120MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2121MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2122MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2123MODULE_LICENSE("GPL");
2124
