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11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/of_gpio.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/input.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22#include <linux/workqueue.h>
23#include <linux/platform_device.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/cs42l52.h>
32#include "cs42l52.h"
33
34struct sp_config {
35 u8 spc, format, spfs;
36 u32 srate;
37};
38
39struct cs42l52_private {
40 struct regmap *regmap;
41 struct snd_soc_component *component;
42 struct device *dev;
43 struct sp_config config;
44 struct cs42l52_platform_data pdata;
45 u32 sysclk;
46 u8 mclksel;
47 u32 mclk;
48 u8 flags;
49 struct input_dev *beep;
50 struct work_struct beep_work;
51 int beep_rate;
52};
53
54static const struct reg_default cs42l52_reg_defaults[] = {
55 { CS42L52_PWRCTL1, 0x9F },
56 { CS42L52_PWRCTL2, 0x07 },
57 { CS42L52_PWRCTL3, 0xFF },
58 { CS42L52_CLK_CTL, 0xA0 },
59 { CS42L52_IFACE_CTL1, 0x00 },
60 { CS42L52_ADC_PGA_A, 0x80 },
61 { CS42L52_ADC_PGA_B, 0x80 },
62 { CS42L52_ANALOG_HPF_CTL, 0xA5 },
63 { CS42L52_ADC_HPF_FREQ, 0x00 },
64 { CS42L52_ADC_MISC_CTL, 0x00 },
65 { CS42L52_PB_CTL1, 0x60 },
66 { CS42L52_MISC_CTL, 0x02 },
67 { CS42L52_PB_CTL2, 0x00 },
68 { CS42L52_MICA_CTL, 0x00 },
69 { CS42L52_MICB_CTL, 0x00 },
70 { CS42L52_PGAA_CTL, 0x00 },
71 { CS42L52_PGAB_CTL, 0x00 },
72 { CS42L52_PASSTHRUA_VOL, 0x00 },
73 { CS42L52_PASSTHRUB_VOL, 0x00 },
74 { CS42L52_ADCA_VOL, 0x00 },
75 { CS42L52_ADCB_VOL, 0x00 },
76 { CS42L52_ADCA_MIXER_VOL, 0x80 },
77 { CS42L52_ADCB_MIXER_VOL, 0x80 },
78 { CS42L52_PCMA_MIXER_VOL, 0x00 },
79 { CS42L52_PCMB_MIXER_VOL, 0x00 },
80 { CS42L52_BEEP_FREQ, 0x00 },
81 { CS42L52_BEEP_VOL, 0x00 },
82 { CS42L52_BEEP_TONE_CTL, 0x00 },
83 { CS42L52_TONE_CTL, 0x00 },
84 { CS42L52_MASTERA_VOL, 0x00 },
85 { CS42L52_MASTERB_VOL, 0x00 },
86 { CS42L52_HPA_VOL, 0x00 },
87 { CS42L52_HPB_VOL, 0x00 },
88 { CS42L52_SPKA_VOL, 0x00 },
89 { CS42L52_SPKB_VOL, 0x00 },
90 { CS42L52_ADC_PCM_MIXER, 0x00 },
91 { CS42L52_LIMITER_CTL1, 0x00 },
92 { CS42L52_LIMITER_CTL2, 0x7F },
93 { CS42L52_LIMITER_AT_RATE, 0xC0 },
94 { CS42L52_ALC_CTL, 0x00 },
95 { CS42L52_ALC_RATE, 0x3F },
96 { CS42L52_ALC_THRESHOLD, 0x3f },
97 { CS42L52_NOISE_GATE_CTL, 0x00 },
98 { CS42L52_CLK_STATUS, 0x00 },
99 { CS42L52_BATT_COMPEN, 0x00 },
100 { CS42L52_BATT_LEVEL, 0x00 },
101 { CS42L52_SPK_STATUS, 0x00 },
102 { CS42L52_TEM_CTL, 0x3B },
103 { CS42L52_THE_FOLDBACK, 0x00 },
104};
105
106static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
107{
108 switch (reg) {
109 case CS42L52_CHIP ... CS42L52_CHARGE_PUMP:
110 return true;
111 default:
112 return false;
113 }
114}
115
116static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
117{
118 switch (reg) {
119 case CS42L52_IFACE_CTL2:
120 case CS42L52_CLK_STATUS:
121 case CS42L52_BATT_LEVEL:
122 case CS42L52_SPK_STATUS:
123 case CS42L52_CHARGE_PUMP:
124 return true;
125 default:
126 return false;
127 }
128}
129
130static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
131
132static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
133
134static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
135
136static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
137
138static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
139
140static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
141
142static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
143
144static const DECLARE_TLV_DB_RANGE(limiter_tlv,
145 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
146 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
147);
148
149static const char * const cs42l52_adca_text[] = {
150 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
151
152static const char * const cs42l52_adcb_text[] = {
153 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
154
155static SOC_ENUM_SINGLE_DECL(adca_enum,
156 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
157
158static SOC_ENUM_SINGLE_DECL(adcb_enum,
159 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
160
161static const struct snd_kcontrol_new adca_mux =
162 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
163
164static const struct snd_kcontrol_new adcb_mux =
165 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
166
167static const char * const mic_bias_level_text[] = {
168 "0.5 +VA", "0.6 +VA", "0.7 +VA",
169 "0.8 +VA", "0.83 +VA", "0.91 +VA"
170};
171
172static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
173 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
174
175static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
176
177static SOC_ENUM_SINGLE_DECL(mica_enum,
178 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
179
180static SOC_ENUM_SINGLE_DECL(micb_enum,
181 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
182
183static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
184
185static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
186 CS42L52_ADC_MISC_CTL, 6,
187 digital_output_mux_text);
188
189static const struct snd_kcontrol_new digital_output_mux =
190 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
191
192static const char * const hp_gain_num_text[] = {
193 "0.3959", "0.4571", "0.5111", "0.6047",
194 "0.7099", "0.8399", "1.000", "1.1430"
195};
196
197static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
198 CS42L52_PB_CTL1, 5,
199 hp_gain_num_text);
200
201static const char * const beep_pitch_text[] = {
202 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
203 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
204};
205
206static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
207 CS42L52_BEEP_FREQ, 4,
208 beep_pitch_text);
209
210static const char * const beep_ontime_text[] = {
211 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
212 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
213 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
214};
215
216static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
217 CS42L52_BEEP_FREQ, 0,
218 beep_ontime_text);
219
220static const char * const beep_offtime_text[] = {
221 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
222 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
223};
224
225static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
226 CS42L52_BEEP_VOL, 5,
227 beep_offtime_text);
228
229static const char * const beep_config_text[] = {
230 "Off", "Single", "Multiple", "Continuous"
231};
232
233static SOC_ENUM_SINGLE_DECL(beep_config_enum,
234 CS42L52_BEEP_TONE_CTL, 6,
235 beep_config_text);
236
237static const char * const beep_bass_text[] = {
238 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
239};
240
241static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
242 CS42L52_BEEP_TONE_CTL, 1,
243 beep_bass_text);
244
245static const char * const beep_treble_text[] = {
246 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
247};
248
249static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
250 CS42L52_BEEP_TONE_CTL, 3,
251 beep_treble_text);
252
253static const char * const ng_threshold_text[] = {
254 "-34dB", "-37dB", "-40dB", "-43dB",
255 "-46dB", "-52dB", "-58dB", "-64dB"
256};
257
258static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
259 CS42L52_NOISE_GATE_CTL, 2,
260 ng_threshold_text);
261
262static const char * const cs42l52_ng_delay_text[] = {
263 "50ms", "100ms", "150ms", "200ms"};
264
265static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
266 CS42L52_NOISE_GATE_CTL, 0,
267 cs42l52_ng_delay_text);
268
269static const char * const cs42l52_ng_type_text[] = {
270 "Apply Specific", "Apply All"
271};
272
273static SOC_ENUM_SINGLE_DECL(ng_type_enum,
274 CS42L52_NOISE_GATE_CTL, 6,
275 cs42l52_ng_type_text);
276
277static const char * const left_swap_text[] = {
278 "Left", "LR 2", "Right"};
279
280static const char * const right_swap_text[] = {
281 "Right", "LR 2", "Left"};
282
283static const unsigned int swap_values[] = { 0, 1, 3 };
284
285static const struct soc_enum adca_swap_enum =
286 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
287 ARRAY_SIZE(left_swap_text),
288 left_swap_text,
289 swap_values);
290
291static const struct snd_kcontrol_new adca_mixer =
292 SOC_DAPM_ENUM("Route", adca_swap_enum);
293
294static const struct soc_enum pcma_swap_enum =
295 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
296 ARRAY_SIZE(left_swap_text),
297 left_swap_text,
298 swap_values);
299
300static const struct snd_kcontrol_new pcma_mixer =
301 SOC_DAPM_ENUM("Route", pcma_swap_enum);
302
303static const struct soc_enum adcb_swap_enum =
304 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
305 ARRAY_SIZE(right_swap_text),
306 right_swap_text,
307 swap_values);
308
309static const struct snd_kcontrol_new adcb_mixer =
310 SOC_DAPM_ENUM("Route", adcb_swap_enum);
311
312static const struct soc_enum pcmb_swap_enum =
313 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
314 ARRAY_SIZE(right_swap_text),
315 right_swap_text,
316 swap_values);
317
318static const struct snd_kcontrol_new pcmb_mixer =
319 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
320
321
322static const struct snd_kcontrol_new passthrul_ctl =
323 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
324
325static const struct snd_kcontrol_new passthrur_ctl =
326 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
327
328static const struct snd_kcontrol_new spkl_ctl =
329 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
330
331static const struct snd_kcontrol_new spkr_ctl =
332 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
333
334static const struct snd_kcontrol_new hpl_ctl =
335 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
336
337static const struct snd_kcontrol_new hpr_ctl =
338 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
339
340static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
341
342 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
343 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
344
345 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
346 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
347
348 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
349
350 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
351 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
352
353 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
354 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pga_tlv),
355
356 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
357
358 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
359 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
360
361 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
362
363 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
364 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
365 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
366 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
367 0, 0x19, 0x7F, ipd_tlv),
368
369 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
370
371 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
372 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
373
374 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
375 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
376
377 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
378 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
379 0, 0x19, 0x7f, mix_tlv),
380 SOC_DOUBLE_R("PCM Mixer Switch",
381 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
382
383 SOC_ENUM("Beep Config", beep_config_enum),
384 SOC_ENUM("Beep Pitch", beep_pitch_enum),
385 SOC_ENUM("Beep on Time", beep_ontime_enum),
386 SOC_ENUM("Beep off Time", beep_offtime_enum),
387 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
388 0, 0x07, 0x1f, beep_tlv),
389 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
390 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
391 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
392
393 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
394 SOC_SINGLE_TLV("Treble Gain Volume",
395 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
396 SOC_SINGLE_TLV("Bass Gain Volume",
397 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
398
399
400 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
401 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
402 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
403 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
404 SOC_SINGLE_TLV("Limiter Release Rate Volume",
405 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
406 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
407 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
408
409 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
410 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
411 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
412
413
414 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
415 0, 63, 0, limiter_tlv),
416 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
417 0, 63, 0, limiter_tlv),
418 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
419 5, 7, 0, limiter_tlv),
420 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
421 2, 7, 0, limiter_tlv),
422
423 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
424 CS42L52_PGAB_CTL, 7, 1, 1),
425 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
426 CS42L52_PGAB_CTL, 6, 1, 1),
427 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
428
429
430 SOC_ENUM("NG Type Switch", ng_type_enum),
431 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
432 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
433 SOC_ENUM("NG Threshold", ng_threshold_enum),
434 SOC_ENUM("NG Delay", ng_delay_enum),
435
436 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
437
438 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
439 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
440 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
441 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
442 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
443
444 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
445 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
446 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
447
448 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
449 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
450 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
451 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
452
453 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
454 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
455
456 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
457 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
458
459 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
460 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
461
462};
463
464static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
465 SOC_ENUM("MICA Select", mica_enum),
466};
467
468static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
469 SOC_ENUM("MICB Select", micb_enum),
470};
471
472static int cs42l52_add_mic_controls(struct snd_soc_component *component)
473{
474 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
475 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
476
477 if (!pdata->mica_diff_cfg)
478 snd_soc_add_component_controls(component, cs42l52_mica_controls,
479 ARRAY_SIZE(cs42l52_mica_controls));
480
481 if (!pdata->micb_diff_cfg)
482 snd_soc_add_component_controls(component, cs42l52_micb_controls,
483 ARRAY_SIZE(cs42l52_micb_controls));
484
485 return 0;
486}
487
488static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
489
490 SND_SOC_DAPM_INPUT("AIN1L"),
491 SND_SOC_DAPM_INPUT("AIN1R"),
492 SND_SOC_DAPM_INPUT("AIN2L"),
493 SND_SOC_DAPM_INPUT("AIN2R"),
494 SND_SOC_DAPM_INPUT("AIN3L"),
495 SND_SOC_DAPM_INPUT("AIN3R"),
496 SND_SOC_DAPM_INPUT("AIN4L"),
497 SND_SOC_DAPM_INPUT("AIN4R"),
498 SND_SOC_DAPM_INPUT("MICA"),
499 SND_SOC_DAPM_INPUT("MICB"),
500 SND_SOC_DAPM_SIGGEN("Beep"),
501
502 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
503 SND_SOC_NOPM, 0, 0),
504 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
505 SND_SOC_NOPM, 0, 0),
506
507 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
508 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
509 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
510 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
511
512 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
513 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
514
515 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
516 0, 0, &adca_mixer),
517 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
518 0, 0, &adcb_mixer),
519
520 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
521 0, 0, &digital_output_mux),
522
523 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
524 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
525
526 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
527 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
528
529 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
530 SND_SOC_NOPM, 0, 0),
531 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
532 SND_SOC_NOPM, 0, 0),
533
534 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
535 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
536
537 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
538 6, 0, &passthrul_ctl),
539 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
540 7, 0, &passthrur_ctl),
541
542 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
543 0, 0, &pcma_mixer),
544 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
545 0, 0, &pcmb_mixer),
546
547 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
548 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
549
550 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
551 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
552
553 SND_SOC_DAPM_OUTPUT("HPOUTA"),
554 SND_SOC_DAPM_OUTPUT("HPOUTB"),
555 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
556 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
557
558};
559
560static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
561
562 {"Capture", NULL, "AIFOUTL"},
563 {"Capture", NULL, "AIFOUTL"},
564
565 {"AIFOUTL", NULL, "Output Mux"},
566 {"AIFOUTR", NULL, "Output Mux"},
567
568 {"Output Mux", "ADC", "ADC Left"},
569 {"Output Mux", "ADC", "ADC Right"},
570
571 {"ADC Left", NULL, "Charge Pump"},
572 {"ADC Right", NULL, "Charge Pump"},
573
574 {"Charge Pump", NULL, "ADC Left Mux"},
575 {"Charge Pump", NULL, "ADC Right Mux"},
576
577 {"ADC Left Mux", "Input1A", "AIN1L"},
578 {"ADC Right Mux", "Input1B", "AIN1R"},
579 {"ADC Left Mux", "Input2A", "AIN2L"},
580 {"ADC Right Mux", "Input2B", "AIN2R"},
581 {"ADC Left Mux", "Input3A", "AIN3L"},
582 {"ADC Right Mux", "Input3B", "AIN3R"},
583 {"ADC Left Mux", "Input4A", "AIN4L"},
584 {"ADC Right Mux", "Input4B", "AIN4R"},
585 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
586 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
587
588 {"PGA Left", "Switch", "AIN1L"},
589 {"PGA Right", "Switch", "AIN1R"},
590 {"PGA Left", "Switch", "AIN2L"},
591 {"PGA Right", "Switch", "AIN2R"},
592 {"PGA Left", "Switch", "AIN3L"},
593 {"PGA Right", "Switch", "AIN3R"},
594 {"PGA Left", "Switch", "AIN4L"},
595 {"PGA Right", "Switch", "AIN4R"},
596
597 {"PGA Left", "Switch", "PGA MICA"},
598 {"PGA MICA", NULL, "MICA"},
599
600 {"PGA Right", "Switch", "PGA MICB"},
601 {"PGA MICB", NULL, "MICB"},
602
603 {"HPOUTA", NULL, "HP Left Amp"},
604 {"HPOUTB", NULL, "HP Right Amp"},
605 {"HP Left Amp", NULL, "Bypass Left"},
606 {"HP Right Amp", NULL, "Bypass Right"},
607 {"Bypass Left", "Switch", "PGA Left"},
608 {"Bypass Right", "Switch", "PGA Right"},
609 {"HP Left Amp", "Switch", "DAC Left"},
610 {"HP Right Amp", "Switch", "DAC Right"},
611
612 {"SPKOUTA", NULL, "SPK Left Amp"},
613 {"SPKOUTB", NULL, "SPK Right Amp"},
614
615 {"SPK Left Amp", NULL, "Beep"},
616 {"SPK Right Amp", NULL, "Beep"},
617 {"SPK Left Amp", "Switch", "Playback"},
618 {"SPK Right Amp", "Switch", "Playback"},
619
620 {"DAC Left", NULL, "Beep"},
621 {"DAC Right", NULL, "Beep"},
622 {"DAC Left", NULL, "Playback"},
623 {"DAC Right", NULL, "Playback"},
624
625 {"Output Mux", "DSP", "Playback"},
626 {"Output Mux", "DSP", "Playback"},
627
628 {"AIFINL", NULL, "Playback"},
629 {"AIFINR", NULL, "Playback"},
630
631};
632
633struct cs42l52_clk_para {
634 u32 mclk;
635 u32 rate;
636 u8 speed;
637 u8 group;
638 u8 videoclk;
639 u8 ratio;
640 u8 mclkdiv2;
641};
642
643static const struct cs42l52_clk_para clk_map_table[] = {
644
645 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
646 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
647 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
648 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
649 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
650
651
652 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
653 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
654
655
656 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
657 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
658 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
659 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
660 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
661
662
663 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
664 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
665
666
667 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
668 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
669 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
670 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
671 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
672
673
674 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
675 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
676
677
678 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
679 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
680 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
681 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
682 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
683
684
685 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
686 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
687
688
689 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
690 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
691 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
692 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
693};
694
695static int cs42l52_get_clk(int mclk, int rate)
696{
697 int i, ret = -EINVAL;
698 u_int mclk1, mclk2 = 0;
699
700 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
701 if (clk_map_table[i].rate == rate) {
702 mclk1 = clk_map_table[i].mclk;
703 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
704 mclk2 = mclk1;
705 ret = i;
706 }
707 }
708 }
709 return ret;
710}
711
712static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
713 int clk_id, unsigned int freq, int dir)
714{
715 struct snd_soc_component *component = codec_dai->component;
716 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
717
718 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
719 cs42l52->sysclk = freq;
720 } else {
721 dev_err(component->dev, "Invalid freq parameter\n");
722 return -EINVAL;
723 }
724 return 0;
725}
726
727static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
728{
729 struct snd_soc_component *component = codec_dai->component;
730 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
731 u8 iface = 0;
732
733 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
734 case SND_SOC_DAIFMT_CBM_CFM:
735 iface = CS42L52_IFACE_CTL1_MASTER;
736 break;
737 case SND_SOC_DAIFMT_CBS_CFS:
738 iface = CS42L52_IFACE_CTL1_SLAVE;
739 break;
740 default:
741 return -EINVAL;
742 }
743
744
745 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
746 case SND_SOC_DAIFMT_I2S:
747 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
748 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
749 break;
750 case SND_SOC_DAIFMT_RIGHT_J:
751 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
752 break;
753 case SND_SOC_DAIFMT_LEFT_J:
754 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
755 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
756 break;
757 case SND_SOC_DAIFMT_DSP_A:
758 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
759 break;
760 case SND_SOC_DAIFMT_DSP_B:
761 break;
762 default:
763 return -EINVAL;
764 }
765
766
767 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
768 case SND_SOC_DAIFMT_NB_NF:
769 break;
770 case SND_SOC_DAIFMT_IB_IF:
771 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
772 break;
773 case SND_SOC_DAIFMT_IB_NF:
774 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
775 break;
776 case SND_SOC_DAIFMT_NB_IF:
777 break;
778 default:
779 return -EINVAL;
780 }
781 cs42l52->config.format = iface;
782 snd_soc_component_write(component, CS42L52_IFACE_CTL1, cs42l52->config.format);
783
784 return 0;
785}
786
787static int cs42l52_mute(struct snd_soc_dai *dai, int mute, int direction)
788{
789 struct snd_soc_component *component = dai->component;
790
791 if (mute)
792 snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
793 CS42L52_PB_CTL1_MUTE_MASK,
794 CS42L52_PB_CTL1_MUTE);
795 else
796 snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
797 CS42L52_PB_CTL1_MUTE_MASK,
798 CS42L52_PB_CTL1_UNMUTE);
799
800 return 0;
801}
802
803static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
804 struct snd_pcm_hw_params *params,
805 struct snd_soc_dai *dai)
806{
807 struct snd_soc_component *component = dai->component;
808 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
809 u32 clk = 0;
810 int index;
811
812 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
813 if (index >= 0) {
814 cs42l52->sysclk = clk_map_table[index].mclk;
815
816 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
817 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
818 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
819 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
820 clk_map_table[index].mclkdiv2;
821
822 snd_soc_component_write(component, CS42L52_CLK_CTL, clk);
823 } else {
824 dev_err(component->dev, "can't get correct mclk\n");
825 return -EINVAL;
826 }
827
828 return 0;
829}
830
831static int cs42l52_set_bias_level(struct snd_soc_component *component,
832 enum snd_soc_bias_level level)
833{
834 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
835
836 switch (level) {
837 case SND_SOC_BIAS_ON:
838 break;
839 case SND_SOC_BIAS_PREPARE:
840 snd_soc_component_update_bits(component, CS42L52_PWRCTL1,
841 CS42L52_PWRCTL1_PDN_CODEC, 0);
842 break;
843 case SND_SOC_BIAS_STANDBY:
844 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
845 regcache_cache_only(cs42l52->regmap, false);
846 regcache_sync(cs42l52->regmap);
847 }
848 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
849 break;
850 case SND_SOC_BIAS_OFF:
851 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
852 regcache_cache_only(cs42l52->regmap, true);
853 break;
854 }
855
856 return 0;
857}
858
859#define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
860
861#define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
862 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
863 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
864 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
865
866static const struct snd_soc_dai_ops cs42l52_ops = {
867 .hw_params = cs42l52_pcm_hw_params,
868 .mute_stream = cs42l52_mute,
869 .set_fmt = cs42l52_set_fmt,
870 .set_sysclk = cs42l52_set_sysclk,
871 .no_capture_mute = 1,
872};
873
874static struct snd_soc_dai_driver cs42l52_dai = {
875 .name = "cs42l52",
876 .playback = {
877 .stream_name = "Playback",
878 .channels_min = 1,
879 .channels_max = 2,
880 .rates = CS42L52_RATES,
881 .formats = CS42L52_FORMATS,
882 },
883 .capture = {
884 .stream_name = "Capture",
885 .channels_min = 1,
886 .channels_max = 2,
887 .rates = CS42L52_RATES,
888 .formats = CS42L52_FORMATS,
889 },
890 .ops = &cs42l52_ops,
891};
892
893static int beep_rates[] = {
894 261, 522, 585, 667, 706, 774, 889, 1000,
895 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
896};
897
898static void cs42l52_beep_work(struct work_struct *work)
899{
900 struct cs42l52_private *cs42l52 =
901 container_of(work, struct cs42l52_private, beep_work);
902 struct snd_soc_component *component = cs42l52->component;
903 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
904 int i;
905 int val = 0;
906 int best = 0;
907
908 if (cs42l52->beep_rate) {
909 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
910 if (abs(cs42l52->beep_rate - beep_rates[i]) <
911 abs(cs42l52->beep_rate - beep_rates[best]))
912 best = i;
913 }
914
915 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
916 beep_rates[best], cs42l52->beep_rate);
917
918 val = (best << CS42L52_BEEP_RATE_SHIFT);
919
920 snd_soc_dapm_enable_pin(dapm, "Beep");
921 } else {
922 dev_dbg(component->dev, "Disabling beep\n");
923 snd_soc_dapm_disable_pin(dapm, "Beep");
924 }
925
926 snd_soc_component_update_bits(component, CS42L52_BEEP_FREQ,
927 CS42L52_BEEP_RATE_MASK, val);
928
929 snd_soc_dapm_sync(dapm);
930}
931
932
933
934
935static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
936 unsigned int code, int hz)
937{
938 struct snd_soc_component *component = input_get_drvdata(dev);
939 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
940
941 dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
942
943 switch (code) {
944 case SND_BELL:
945 if (hz)
946 hz = 261;
947 break;
948 case SND_TONE:
949 break;
950 default:
951 return -1;
952 }
953
954
955 cs42l52->beep_rate = hz;
956 schedule_work(&cs42l52->beep_work);
957 return 0;
958}
959
960static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
961 const char *buf, size_t count)
962{
963 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
964 long int time;
965 int ret;
966
967 ret = kstrtol(buf, 10, &time);
968 if (ret != 0)
969 return ret;
970
971 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
972
973 return count;
974}
975
976static DEVICE_ATTR_WO(beep);
977
978static void cs42l52_init_beep(struct snd_soc_component *component)
979{
980 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
981 int ret;
982
983 cs42l52->beep = devm_input_allocate_device(component->dev);
984 if (!cs42l52->beep) {
985 dev_err(component->dev, "Failed to allocate beep device\n");
986 return;
987 }
988
989 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
990 cs42l52->beep_rate = 0;
991
992 cs42l52->beep->name = "CS42L52 Beep Generator";
993 cs42l52->beep->phys = dev_name(component->dev);
994 cs42l52->beep->id.bustype = BUS_I2C;
995
996 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
997 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
998 cs42l52->beep->event = cs42l52_beep_event;
999 cs42l52->beep->dev.parent = component->dev;
1000 input_set_drvdata(cs42l52->beep, component);
1001
1002 ret = input_register_device(cs42l52->beep);
1003 if (ret != 0) {
1004 cs42l52->beep = NULL;
1005 dev_err(component->dev, "Failed to register beep device\n");
1006 }
1007
1008 ret = device_create_file(component->dev, &dev_attr_beep);
1009 if (ret != 0) {
1010 dev_err(component->dev, "Failed to create keyclick file: %d\n",
1011 ret);
1012 }
1013}
1014
1015static void cs42l52_free_beep(struct snd_soc_component *component)
1016{
1017 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
1018
1019 device_remove_file(component->dev, &dev_attr_beep);
1020 cancel_work_sync(&cs42l52->beep_work);
1021 cs42l52->beep = NULL;
1022
1023 snd_soc_component_update_bits(component, CS42L52_BEEP_TONE_CTL,
1024 CS42L52_BEEP_EN_MASK, 0);
1025}
1026
1027static int cs42l52_probe(struct snd_soc_component *component)
1028{
1029 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
1030
1031 regcache_cache_only(cs42l52->regmap, true);
1032
1033 cs42l52_add_mic_controls(component);
1034
1035 cs42l52_init_beep(component);
1036
1037 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1038 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1039
1040 return 0;
1041}
1042
1043static void cs42l52_remove(struct snd_soc_component *component)
1044{
1045 cs42l52_free_beep(component);
1046}
1047
1048static const struct snd_soc_component_driver soc_component_dev_cs42l52 = {
1049 .probe = cs42l52_probe,
1050 .remove = cs42l52_remove,
1051 .set_bias_level = cs42l52_set_bias_level,
1052 .controls = cs42l52_snd_controls,
1053 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1054 .dapm_widgets = cs42l52_dapm_widgets,
1055 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1056 .dapm_routes = cs42l52_audio_map,
1057 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1058 .suspend_bias_off = 1,
1059 .idle_bias_on = 1,
1060 .use_pmdown_time = 1,
1061 .endianness = 1,
1062 .non_legacy_dai_naming = 1,
1063};
1064
1065
1066static const struct reg_sequence cs42l52_threshold_patch[] = {
1067
1068 { 0x00, 0x99 },
1069 { 0x3E, 0xBA },
1070 { 0x47, 0x80 },
1071 { 0x32, 0xBB },
1072 { 0x32, 0x3B },
1073 { 0x00, 0x00 },
1074
1075};
1076
1077static const struct regmap_config cs42l52_regmap = {
1078 .reg_bits = 8,
1079 .val_bits = 8,
1080
1081 .max_register = CS42L52_MAX_REGISTER,
1082 .reg_defaults = cs42l52_reg_defaults,
1083 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1084 .readable_reg = cs42l52_readable_register,
1085 .volatile_reg = cs42l52_volatile_register,
1086 .cache_type = REGCACHE_RBTREE,
1087};
1088
1089static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1090 const struct i2c_device_id *id)
1091{
1092 struct cs42l52_private *cs42l52;
1093 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1094 int ret;
1095 unsigned int devid;
1096 unsigned int reg;
1097 u32 val32;
1098
1099 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL);
1100 if (cs42l52 == NULL)
1101 return -ENOMEM;
1102 cs42l52->dev = &i2c_client->dev;
1103
1104 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1105 if (IS_ERR(cs42l52->regmap)) {
1106 ret = PTR_ERR(cs42l52->regmap);
1107 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1108 return ret;
1109 }
1110 if (pdata) {
1111 cs42l52->pdata = *pdata;
1112 } else {
1113 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1114 GFP_KERNEL);
1115 if (!pdata)
1116 return -ENOMEM;
1117
1118 if (i2c_client->dev.of_node) {
1119 if (of_property_read_bool(i2c_client->dev.of_node,
1120 "cirrus,mica-differential-cfg"))
1121 pdata->mica_diff_cfg = true;
1122
1123 if (of_property_read_bool(i2c_client->dev.of_node,
1124 "cirrus,micb-differential-cfg"))
1125 pdata->micb_diff_cfg = true;
1126
1127 if (of_property_read_u32(i2c_client->dev.of_node,
1128 "cirrus,micbias-lvl", &val32) >= 0)
1129 pdata->micbias_lvl = val32;
1130
1131 if (of_property_read_u32(i2c_client->dev.of_node,
1132 "cirrus,chgfreq-divisor", &val32) >= 0)
1133 pdata->chgfreq = val32;
1134
1135 pdata->reset_gpio =
1136 of_get_named_gpio(i2c_client->dev.of_node,
1137 "cirrus,reset-gpio", 0);
1138 }
1139 cs42l52->pdata = *pdata;
1140 }
1141
1142 if (cs42l52->pdata.reset_gpio) {
1143 ret = devm_gpio_request_one(&i2c_client->dev,
1144 cs42l52->pdata.reset_gpio,
1145 GPIOF_OUT_INIT_HIGH,
1146 "CS42L52 /RST");
1147 if (ret < 0) {
1148 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1149 cs42l52->pdata.reset_gpio, ret);
1150 return ret;
1151 }
1152 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1153 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1154 }
1155
1156 i2c_set_clientdata(i2c_client, cs42l52);
1157
1158 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1159 ARRAY_SIZE(cs42l52_threshold_patch));
1160 if (ret != 0)
1161 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1162 ret);
1163
1164 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
1165 if (ret) {
1166 dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
1167 return ret;
1168 }
1169
1170 devid = reg & CS42L52_CHIP_ID_MASK;
1171 if (devid != CS42L52_CHIP_ID) {
1172 ret = -ENODEV;
1173 dev_err(&i2c_client->dev,
1174 "CS42L52 Device ID (%X). Expected %X\n",
1175 devid, CS42L52_CHIP_ID);
1176 return ret;
1177 }
1178
1179 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1180 reg & CS42L52_CHIP_REV_MASK);
1181
1182
1183 if (cs42l52->pdata.mica_diff_cfg)
1184 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1185 CS42L52_MIC_CTL_TYPE_MASK,
1186 cs42l52->pdata.mica_diff_cfg <<
1187 CS42L52_MIC_CTL_TYPE_SHIFT);
1188
1189 if (cs42l52->pdata.micb_diff_cfg)
1190 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1191 CS42L52_MIC_CTL_TYPE_MASK,
1192 cs42l52->pdata.micb_diff_cfg <<
1193 CS42L52_MIC_CTL_TYPE_SHIFT);
1194
1195 if (cs42l52->pdata.chgfreq)
1196 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1197 CS42L52_CHARGE_PUMP_MASK,
1198 cs42l52->pdata.chgfreq <<
1199 CS42L52_CHARGE_PUMP_SHIFT);
1200
1201 if (cs42l52->pdata.micbias_lvl)
1202 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1203 CS42L52_IFACE_CTL2_BIAS_LVL,
1204 cs42l52->pdata.micbias_lvl);
1205
1206 return devm_snd_soc_register_component(&i2c_client->dev,
1207 &soc_component_dev_cs42l52, &cs42l52_dai, 1);
1208}
1209
1210static const struct of_device_id cs42l52_of_match[] = {
1211 { .compatible = "cirrus,cs42l52", },
1212 {},
1213};
1214MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1215
1216
1217static const struct i2c_device_id cs42l52_id[] = {
1218 { "cs42l52", 0 },
1219 { }
1220};
1221MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1222
1223static struct i2c_driver cs42l52_i2c_driver = {
1224 .driver = {
1225 .name = "cs42l52",
1226 .of_match_table = cs42l52_of_match,
1227 },
1228 .id_table = cs42l52_id,
1229 .probe = cs42l52_i2c_probe,
1230};
1231
1232module_i2c_driver(cs42l52_i2c_driver);
1233
1234MODULE_DESCRIPTION("ASoC CS42L52 driver");
1235MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1236MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1237MODULE_LICENSE("GPL");
1238
