LXR linux/sound/soc/codecs/cs43130.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * ALSA SoC CS43130 codec driver
   4 *
   5 * Copyright 2017 Cirrus Logic, Inc.
   6 *
   7 * Author: Li Xu <li.xu@cirrus.com>
   8 */
   9
  10#ifndef __CS43130_H__
  11#define __CS43130_H__
  12
  13/* CS43130 registers addresses */
  14/* all reg address is shifted by a byte for control byte to be LSB */
  15#define CS43130_FIRSTREG        0x010000
  16#define CS43130_LASTREG         0x190000
  17#define CS43130_CHIP_ID         0x00043130
  18#define CS4399_CHIP_ID          0x00043990
  19#define CS43131_CHIP_ID         0x00043131
  20#define CS43198_CHIP_ID         0x00043198
  21#define CS43130_DEVID_AB        0x010000        /* Device ID A & B [RO] */
  22#define CS43130_DEVID_CD        0x010001        /* Device ID C & D [RO] */
  23#define CS43130_DEVID_E         0x010002        /* Device ID E [RO] */
  24#define CS43130_FAB_ID          0x010003        /* Fab ID [RO] */
  25#define CS43130_REV_ID          0x010004        /* Revision ID [RO] */
  26#define CS43130_SUBREV_ID       0x010005        /* Subrevision ID */
  27#define CS43130_SYS_CLK_CTL_1   0x010006        /* System Clocking Ctl 1 */
  28#define CS43130_SP_SRATE        0x01000B        /* Serial Port Sample Rate */
  29#define CS43130_SP_BITSIZE      0x01000C        /* Serial Port Bit Size */
  30#define CS43130_PAD_INT_CFG     0x01000D        /* Pad Interface Config */
  31#define CS43130_DXD1            0x010010        /* DXD1 */
  32#define CS43130_DXD7            0x010025        /* DXD7 */
  33#define CS43130_DXD19           0x010026        /* DXD19 */
  34#define CS43130_DXD17           0x010027        /* DXD17 */
  35#define CS43130_DXD18           0x010028        /* DXD18 */
  36#define CS43130_DXD12           0x01002C        /* DXD12 */
  37#define CS43130_DXD8            0x01002E        /* DXD8 */
  38#define CS43130_PWDN_CTL        0x020000        /* Power Down Ctl */
  39#define CS43130_DXD2            0x020019        /* DXD2 */
  40#define CS43130_CRYSTAL_SET     0x020052        /* Crystal Setting */
  41#define CS43130_PLL_SET_1       0x030001        /* PLL Setting 1 */
  42#define CS43130_PLL_SET_2       0x030002        /* PLL Setting 2 */
  43#define CS43130_PLL_SET_3       0x030003        /* PLL Setting 3 */
  44#define CS43130_PLL_SET_4       0x030004        /* PLL Setting 4 */
  45#define CS43130_PLL_SET_5       0x030005        /* PLL Setting 5 */
  46#define CS43130_PLL_SET_6       0x030008        /* PLL Setting 6 */
  47#define CS43130_PLL_SET_7       0x03000A        /* PLL Setting 7 */
  48#define CS43130_PLL_SET_8       0x03001B        /* PLL Setting 8 */
  49#define CS43130_PLL_SET_9       0x040002        /* PLL Setting 9 */
  50#define CS43130_PLL_SET_10      0x040003        /* PLL Setting 10 */
  51#define CS43130_CLKOUT_CTL      0x040004        /* CLKOUT Ctl */
  52#define CS43130_ASP_NUM_1       0x040010        /* ASP Numerator 1 */
  53#define CS43130_ASP_NUM_2       0x040011        /* ASP Numerator 2 */
  54#define CS43130_ASP_DEN_1       0x040012        /* ASP Denominator 1 */
  55#define CS43130_ASP_DEN_2       0x040013        /* ASP Denominator 2 */
  56#define CS43130_ASP_LRCK_HI_TIME_1 0x040014     /* ASP LRCK High Time 1 */
  57#define CS43130_ASP_LRCK_HI_TIME_2 0x040015     /* ASP LRCK High Time 2 */
  58#define CS43130_ASP_LRCK_PERIOD_1  0x040016     /* ASP LRCK Period 1 */
  59#define CS43130_ASP_LRCK_PERIOD_2  0x040017     /* ASP LRCK Period 2 */
  60#define CS43130_ASP_CLOCK_CONF  0x040018        /* ASP Clock Config */
  61#define CS43130_ASP_FRAME_CONF  0x040019        /* ASP Frame Config */
  62#define CS43130_XSP_NUM_1       0x040020        /* XSP Numerator 1 */
  63#define CS43130_XSP_NUM_2       0x040021        /* XSP Numerator 2 */
  64#define CS43130_XSP_DEN_1       0x040022        /* XSP Denominator 1 */
  65#define CS43130_XSP_DEN_2       0x040023        /* XSP Denominator 2 */
  66#define CS43130_XSP_LRCK_HI_TIME_1 0x040024     /* XSP LRCK High Time 1 */
  67#define CS43130_XSP_LRCK_HI_TIME_2 0x040025     /* XSP LRCK High Time 2 */
  68#define CS43130_XSP_LRCK_PERIOD_1  0x040026     /* XSP LRCK Period 1 */
  69#define CS43130_XSP_LRCK_PERIOD_2  0x040027     /* XSP LRCK Period 2 */
  70#define CS43130_XSP_CLOCK_CONF  0x040028        /* XSP Clock Config */
  71#define CS43130_XSP_FRAME_CONF  0x040029        /* XSP Frame Config */
  72#define CS43130_ASP_CH_1_LOC    0x050000        /* ASP Chan 1 Location */
  73#define CS43130_ASP_CH_2_LOC    0x050001        /* ASP Chan 2 Location */
  74#define CS43130_ASP_CH_1_SZ_EN  0x05000A        /* ASP Chan 1 Size, Enable */
  75#define CS43130_ASP_CH_2_SZ_EN  0x05000B        /* ASP Chan 2 Size, Enable */
  76#define CS43130_XSP_CH_1_LOC    0x060000        /* XSP Chan 1 Location */
  77#define CS43130_XSP_CH_2_LOC    0x060001        /* XSP Chan 2 Location */
  78#define CS43130_XSP_CH_1_SZ_EN  0x06000A        /* XSP Chan 1 Size, Enable */
  79#define CS43130_XSP_CH_2_SZ_EN  0x06000B        /* XSP Chan 2 Size, Enable */
  80#define CS43130_DSD_VOL_B       0x070000        /* DSD Volume B */
  81#define CS43130_DSD_VOL_A       0x070001        /* DSD Volume A */
  82#define CS43130_DSD_PATH_CTL_1  0x070002        /* DSD Proc Path Sig Ctl 1 */
  83#define CS43130_DSD_INT_CFG     0x070003        /* DSD Interface Config */
  84#define CS43130_DSD_PATH_CTL_2  0x070004        /* DSD Proc Path Sig Ctl 2 */
  85#define CS43130_DSD_PCM_MIX_CTL 0x070005        /* DSD and PCM Mixing Ctl */
  86#define CS43130_DSD_PATH_CTL_3  0x070006        /* DSD Proc Path Sig Ctl 3 */
  87#define CS43130_HP_OUT_CTL_1    0x080000        /* HP Output Ctl 1 */
  88#define CS43130_DXD16           0x080024        /* DXD16 */
  89#define CS43130_DXD13           0x080032        /* DXD13 */
  90#define CS43130_PCM_FILT_OPT    0x090000        /* PCM Filter Option */
  91#define CS43130_PCM_VOL_B       0x090001        /* PCM Volume B */
  92#define CS43130_PCM_VOL_A       0x090002        /* PCM Volume A */
  93#define CS43130_PCM_PATH_CTL_1  0x090003        /* PCM Path Signal Ctl 1 */
  94#define CS43130_PCM_PATH_CTL_2  0x090004        /* PCM Path Signal Ctl 2 */
  95#define CS43130_DXD6            0x090097        /* DXD6 */
  96#define CS43130_CLASS_H_CTL     0x0B0000        /* Class H Ctl */
  97#define CS43130_DXD15           0x0B0005        /* DXD15 */
  98#define CS43130_DXD14           0x0B0006        /* DXD14 */
  99#define CS43130_DXD3            0x0C0002        /* DXD3 */
 100#define CS43130_DXD10           0x0C0003        /* DXD10 */
 101#define CS43130_DXD11           0x0C0005        /* DXD11 */
 102#define CS43130_DXD9            0x0C0006        /* DXD9 */
 103#define CS43130_DXD4            0x0C0009        /* DXD4 */
 104#define CS43130_DXD5            0x0C000E        /* DXD5 */
 105#define CS43130_HP_DETECT       0x0D0000        /* HP Detect */
 106#define CS43130_HP_STATUS       0x0D0001        /* HP Status [RO] */
 107#define CS43130_HP_LOAD_1       0x0E0000        /* HP Load 1 */
 108#define CS43130_HP_MEAS_LOAD_1  0x0E0003        /* HP Load Measurement 1 */
 109#define CS43130_HP_MEAS_LOAD_2  0x0E0004        /* HP Load Measurement 2 */
 110#define CS43130_HP_DC_STAT_1    0x0E000D        /* HP DC Load Status 0 [RO] */
 111#define CS43130_HP_DC_STAT_2    0x0E000E        /* HP DC Load Status 1 [RO] */
 112#define CS43130_HP_AC_STAT_1    0x0E0010        /* HP AC Load Status 0 [RO] */
 113#define CS43130_HP_AC_STAT_2    0x0E0011        /* HP AC Load Status 1 [RO] */
 114#define CS43130_HP_LOAD_STAT    0x0E001A        /* HP Load Status [RO] */
 115#define CS43130_INT_STATUS_1    0x0F0000        /* Interrupt Status 1 */
 116#define CS43130_INT_STATUS_2    0x0F0001        /* Interrupt Status 2 */
 117#define CS43130_INT_STATUS_3    0x0F0002        /* Interrupt Status 3 */
 118#define CS43130_INT_STATUS_4    0x0F0003        /* Interrupt Status 4 */
 119#define CS43130_INT_STATUS_5    0x0F0004        /* Interrupt Status 5 */
 120#define CS43130_INT_MASK_1      0x0F0010        /* Interrupt Mask 1 */
 121#define CS43130_INT_MASK_2      0x0F0011        /* Interrupt Mask 2 */
 122#define CS43130_INT_MASK_3      0x0F0012        /* Interrupt Mask 3 */
 123#define CS43130_INT_MASK_4      0x0F0013        /* Interrupt Mask 4 */
 124#define CS43130_INT_MASK_5      0x0F0014        /* Interrupt Mask 5 */
 125
 126#define CS43130_MCLK_SRC_SEL_MASK       0x03
 127#define CS43130_MCLK_SRC_SEL_SHIFT      0
 128#define CS43130_MCLK_INT_MASK           0x04
 129#define CS43130_MCLK_INT_SHIFT          2
 130#define CS43130_CH_BITSIZE_MASK         0x03
 131#define CS43130_CH_EN_MASK              0x04
 132#define CS43130_CH_EN_SHIFT             2
 133#define CS43130_ASP_BITSIZE_MASK        0x03
 134#define CS43130_XSP_BITSIZE_MASK        0x0C
 135#define CS43130_XSP_BITSIZE_SHIFT       2
 136#define CS43130_SP_BITSIZE_ASP_SHIFT    0
 137#define CS43130_HP_DETECT_CTRL_SHIFT    6
 138#define CS43130_HP_DETECT_CTRL_MASK     (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
 139#define CS43130_HP_DETECT_INV_SHIFT     5
 140#define CS43130_HP_DETECT_INV_MASK      (1 << CS43130_HP_DETECT_INV_SHIFT)
 141
 142/* CS43130_INT_MASK_1 */
 143#define CS43130_HP_PLUG_INT_SHIFT       6
 144#define CS43130_HP_PLUG_INT             (1 << CS43130_HP_PLUG_INT_SHIFT)
 145#define CS43130_HP_UNPLUG_INT_SHIFT     5
 146#define CS43130_HP_UNPLUG_INT           (1 << CS43130_HP_UNPLUG_INT_SHIFT)
 147#define CS43130_XTAL_RDY_INT_SHIFT      4
 148#define CS43130_XTAL_RDY_INT_MASK       0x10
 149#define CS43130_XTAL_RDY_INT            (1 << CS43130_XTAL_RDY_INT_SHIFT)
 150#define CS43130_XTAL_ERR_INT_SHIFT      3
 151#define CS43130_XTAL_ERR_INT            (1 << CS43130_XTAL_ERR_INT_SHIFT)
 152#define CS43130_PLL_RDY_INT_MASK        0x04
 153#define CS43130_PLL_RDY_INT_SHIFT       2
 154#define CS43130_PLL_RDY_INT             (1 << CS43130_PLL_RDY_INT_SHIFT)
 155
 156/* CS43130_INT_MASK_4 */
 157#define CS43130_INT_MASK_ALL            0xFF
 158#define CS43130_HPLOAD_NO_DC_INT_SHIFT  7
 159#define CS43130_HPLOAD_NO_DC_INT        (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)
 160#define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6
 161#define CS43130_HPLOAD_UNPLUG_INT       (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)
 162#define CS43130_HPLOAD_OOR_INT_SHIFT    4
 163#define CS43130_HPLOAD_OOR_INT          (1 << CS43130_HPLOAD_OOR_INT_SHIFT)
 164#define CS43130_HPLOAD_AC_INT_SHIFT     3
 165#define CS43130_HPLOAD_AC_INT           (1 << CS43130_HPLOAD_AC_INT_SHIFT)
 166#define CS43130_HPLOAD_DC_INT_SHIFT     2
 167#define CS43130_HPLOAD_DC_INT           (1 << CS43130_HPLOAD_DC_INT_SHIFT)
 168#define CS43130_HPLOAD_OFF_INT_SHIFT    1
 169#define CS43130_HPLOAD_OFF_INT          (1 << CS43130_HPLOAD_OFF_INT_SHIFT)
 170#define CS43130_HPLOAD_ON_INT           1
 171
 172/* CS43130_HP_LOAD_1 */
 173#define CS43130_HPLOAD_EN_SHIFT         7
 174#define CS43130_HPLOAD_EN               (1 << CS43130_HPLOAD_EN_SHIFT)
 175#define CS43130_HPLOAD_CHN_SEL_SHIFT    4
 176#define CS43130_HPLOAD_CHN_SEL          (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)
 177#define CS43130_HPLOAD_AC_START_SHIFT   1
 178#define CS43130_HPLOAD_AC_START         (1 << CS43130_HPLOAD_AC_START_SHIFT)
 179#define CS43130_HPLOAD_DC_START         1
 180
 181/* Reg CS43130_SP_BITSIZE */
 182#define CS43130_SP_BIT_SIZE_8   0x03
 183#define CS43130_SP_BIT_SIZE_16  0x02
 184#define CS43130_SP_BIT_SIZE_24  0x01
 185#define CS43130_SP_BIT_SIZE_32  0x00
 186
 187/* Reg CS43130_SP_CH_SZ_EN */
 188#define CS43130_CH_BIT_SIZE_8   0x00
 189#define CS43130_CH_BIT_SIZE_16  0x01
 190#define CS43130_CH_BIT_SIZE_24  0x02
 191#define CS43130_CH_BIT_SIZE_32  0x03
 192
 193/* PLL */
 194#define CS43130_PLL_START_MASK  0x01
 195#define CS43130_PLL_MODE_MASK   0x02
 196#define CS43130_PLL_MODE_SHIFT  1
 197
 198#define CS43130_PLL_REF_PREDIV_MASK     0x3
 199
 200#define CS43130_SP_STP_MASK     0x10
 201#define CS43130_SP_STP_SHIFT    4
 202#define CS43130_SP_5050_MASK    0x08
 203#define CS43130_SP_5050_SHIFT   3
 204#define CS43130_SP_FSD_MASK     0x07
 205
 206#define CS43130_SP_MODE_MASK    0x10
 207#define CS43130_SP_MODE_SHIFT   4
 208#define CS43130_SP_SCPOL_OUT_MASK       0x08
 209#define CS43130_SP_SCPOL_OUT_SHIFT      3
 210#define CS43130_SP_SCPOL_IN_MASK        0x04
 211#define CS43130_SP_SCPOL_IN_SHIFT       2
 212#define CS43130_SP_LCPOL_OUT_MASK       0x02
 213#define CS43130_SP_LCPOL_OUT_SHIFT      1
 214#define CS43130_SP_LCPOL_IN_MASK        0x01
 215#define CS43130_SP_LCPOL_IN_SHIFT       0
 216
 217/* Reg CS43130_PWDN_CTL */
 218#define CS43130_PDN_XSP_MASK    0x80
 219#define CS43130_PDN_XSP_SHIFT   7
 220#define CS43130_PDN_ASP_MASK    0x40
 221#define CS43130_PDN_ASP_SHIFT   6
 222#define CS43130_PDN_DSPIF_MASK  0x20
 223#define CS43130_PDN_DSDIF_SHIFT 5
 224#define CS43130_PDN_HP_MASK     0x10
 225#define CS43130_PDN_HP_SHIFT    4
 226#define CS43130_PDN_XTAL_MASK   0x08
 227#define CS43130_PDN_XTAL_SHIFT  3
 228#define CS43130_PDN_PLL_MASK    0x04
 229#define CS43130_PDN_PLL_SHIFT   2
 230#define CS43130_PDN_CLKOUT_MASK 0x02
 231#define CS43130_PDN_CLKOUT_SHIFT        1
 232
 233/* Reg CS43130_HP_OUT_CTL_1 */
 234#define CS43130_HP_IN_EN_SHIFT          3
 235#define CS43130_HP_IN_EN_MASK           0x08
 236
 237/* Reg CS43130_PAD_INT_CFG */
 238#define CS43130_ASP_3ST_MASK            0x01
 239#define CS43130_XSP_3ST_MASK            0x02
 240
 241/* Reg CS43130_PLL_SET_2 */
 242#define CS43130_PLL_DIV_DATA_MASK       0x000000FF
 243#define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT       0
 244
 245/* Reg CS43130_PLL_SET_3 */
 246#define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT       8
 247
 248/* Reg CS43130_PLL_SET_4 */
 249#define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT       16
 250
 251/* Reg CS43130_SP_DEN_1 */
 252#define CS43130_SP_M_LSB_DATA_MASK      0x00FF
 253#define CS43130_SP_M_LSB_DATA_SHIFT     0
 254
 255/* Reg CS43130_SP_DEN_2 */
 256#define CS43130_SP_M_MSB_DATA_MASK      0xFF00
 257#define CS43130_SP_M_MSB_DATA_SHIFT     8
 258
 259/* Reg CS43130_SP_NUM_1 */
 260#define CS43130_SP_N_LSB_DATA_MASK      0x00FF
 261#define CS43130_SP_N_LSB_DATA_SHIFT     0
 262
 263/* Reg CS43130_SP_NUM_2 */
 264#define CS43130_SP_N_MSB_DATA_MASK      0xFF00
 265#define CS43130_SP_N_MSB_DATA_SHIFT     8
 266
 267/* Reg CS43130_SP_LRCK_HI_TIME_1 */
 268#define CS43130_SP_LCHI_DATA_MASK       0x00FF
 269#define CS43130_SP_LCHI_LSB_DATA_SHIFT  0
 270
 271/* Reg CS43130_SP_LRCK_HI_TIME_2 */
 272#define CS43130_SP_LCHI_MSB_DATA_SHIFT  8
 273
 274/* Reg CS43130_SP_LRCK_PERIOD_1 */
 275#define CS43130_SP_LCPR_DATA_MASK       0x00FF
 276#define CS43130_SP_LCPR_LSB_DATA_SHIFT  0
 277
 278/* Reg CS43130_SP_LRCK_PERIOD_2 */
 279#define CS43130_SP_LCPR_MSB_DATA_SHIFT  8
 280
 281#define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8  | \
 282                        SNDRV_PCM_FMTBIT_S16_LE | \
 283                        SNDRV_PCM_FMTBIT_S24_LE | \
 284                        SNDRV_PCM_FMTBIT_S32_LE)
 285
 286#define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \
 287                             SNDRV_PCM_FMTBIT_DSD_U16_BE | \
 288                             SNDRV_PCM_FMTBIT_S24_LE)
 289
 290/* Reg CS43130_CRYSTAL_SET */
 291#define CS43130_XTAL_IBIAS_MASK         0x07
 292
 293/* Reg CS43130_PATH_CTL_1 */
 294#define CS43130_MUTE_MASK               0x03
 295#define CS43130_MUTE_EN                 0x03
 296
 297/* Reg CS43130_DSD_INT_CFG */
 298#define CS43130_DSD_MASTER              0x04
 299
 300/* Reg CS43130_DSD_PATH_CTL_2 */
 301#define CS43130_DSD_SRC_MASK            0x60
 302#define CS43130_DSD_SRC_SHIFT           5
 303#define CS43130_DSD_EN_SHIFT            4
 304#define CS43130_DSD_SPEED_MASK          0x04
 305#define CS43130_DSD_SPEED_SHIFT         2
 306
 307/* Reg CS43130_DSD_PCM_MIX_CTL  */
 308#define CS43130_MIX_PCM_PREP_SHIFT      1
 309#define CS43130_MIX_PCM_PREP_MASK       0x02
 310
 311#define CS43130_MIX_PCM_DSD_SHIFT       0
 312#define CS43130_MIX_PCM_DSD_MASK        0x01
 313
 314/* Reg CS43130_HP_MEAS_LOAD */
 315#define CS43130_HP_MEAS_LOAD_MASK       0x000000FF
 316#define CS43130_HP_MEAS_LOAD_1_SHIFT    0
 317#define CS43130_HP_MEAS_LOAD_2_SHIFT    8
 318
 319#define CS43130_MCLK_22M                22579200
 320#define CS43130_MCLK_24M                24576000
 321
 322#define CS43130_LINEOUT_LOAD            5000
 323#define CS43130_JACK_LINEOUT            (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
 324#define CS43130_JACK_HEADPHONE          (SND_JACK_MECHANICAL | \
 325                                         SND_JACK_HEADPHONE)
 326#define CS43130_JACK_MASK               (SND_JACK_MECHANICAL | \
 327                                         SND_JACK_LINEOUT | \
 328                                         SND_JACK_HEADPHONE)
 329
 330enum cs43130_dsd_src {
 331        CS43130_DSD_SRC_DSD = 0,
 332        CS43130_DSD_SRC_ASP = 2,
 333        CS43130_DSD_SRC_XSP = 3,
 334};
 335
 336enum cs43130_asp_rate {
 337        CS43130_ASP_SPRATE_32K = 0,
 338        CS43130_ASP_SPRATE_44_1K,
 339        CS43130_ASP_SPRATE_48K,
 340        CS43130_ASP_SPRATE_88_2K,
 341        CS43130_ASP_SPRATE_96K,
 342        CS43130_ASP_SPRATE_176_4K,
 343        CS43130_ASP_SPRATE_192K,
 344        CS43130_ASP_SPRATE_352_8K,
 345        CS43130_ASP_SPRATE_384K,
 346};
 347
 348enum cs43130_mclk_src_sel {
 349        CS43130_MCLK_SRC_EXT = 0,
 350        CS43130_MCLK_SRC_PLL,
 351        CS43130_MCLK_SRC_RCO
 352};
 353
 354enum cs43130_mclk_int_freq {
 355        CS43130_MCLK_24P5 = 0,
 356        CS43130_MCLK_22P5,
 357};
 358
 359enum cs43130_xtal_ibias {
 360        CS43130_XTAL_UNUSED = -1,
 361        CS43130_XTAL_IBIAS_15UA = 2,
 362        CS43130_XTAL_IBIAS_12_5UA = 4,
 363        CS43130_XTAL_IBIAS_7_5UA = 6,
 364};
 365
 366enum cs43130_dai_id {
 367        CS43130_ASP_PCM_DAI = 0,
 368        CS43130_ASP_DOP_DAI,
 369        CS43130_XSP_DOP_DAI,
 370        CS43130_XSP_DSD_DAI,
 371        CS43130_DAI_ID_MAX,
 372};
 373
 374struct cs43130_clk_gen {
 375        unsigned int    mclk_int;
 376        int             fs;
 377        u16             den;
 378        u16             num;
 379};
 380
 381/* frm_size = 16 */
 382static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
 383        {22579200,      32000,          441,            10,},
 384        {22579200,      44100,          32,             1,},
 385        {22579200,      48000,          147,            5,},
 386        {22579200,      88200,          16,             1,},
 387        {22579200,      96000,          147,            10,},
 388        {22579200,      176400,         8,              1,},
 389        {22579200,      192000,         147,            20,},
 390        {22579200,      352800,         4,              1,},
 391        {22579200,      384000,         147,            40,},
 392        {24576000,      32000,          48,             1,},
 393        {24576000,      44100,          5120,           147,},
 394        {24576000,      48000,          32,             1,},
 395        {24576000,      88200,          2560,           147,},
 396        {24576000,      96000,          16,             1,},
 397        {24576000,      176400,         1280,           147,},
 398        {24576000,      192000,         8,              1,},
 399        {24576000,      352800,         640,            147,},
 400        {24576000,      384000,         4,              1,},
 401};
 402
 403/* frm_size = 32 */
 404static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
 405        {22579200,      32000,          441,            20,},
 406        {22579200,      44100,          16,             1,},
 407        {22579200,      48000,          147,            10,},
 408        {22579200,      88200,          8,              1,},
 409        {22579200,      96000,          147,            20,},
 410        {22579200,      176400,         4,              1,},
 411        {22579200,      192000,         147,            40,},
 412        {22579200,      352800,         2,              1,},
 413        {22579200,      384000,         147,            80,},
 414        {24576000,      32000,          24,             1,},
 415        {24576000,      44100,          2560,           147,},
 416        {24576000,      48000,          16,             1,},
 417        {24576000,      88200,          1280,           147,},
 418        {24576000,      96000,          8,              1,},
 419        {24576000,      176400,         640,            147,},
 420        {24576000,      192000,         4,              1,},
 421        {24576000,      352800,         320,            147,},
 422        {24576000,      384000,         2,              1,},
 423};
 424
 425/* frm_size = 48 */
 426static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
 427        {22579200,      32000,          147,            100,},
 428        {22579200,      44100,          32,             3,},
 429        {22579200,      48000,          49,             5,},
 430        {22579200,      88200,          16,             3,},
 431        {22579200,      96000,          49,             10,},
 432        {22579200,      176400,         8,              3,},
 433        {22579200,      192000,         49,             20,},
 434        {22579200,      352800,         4,              3,},
 435        {22579200,      384000,         49,             40,},
 436        {24576000,      32000,          16,             1,},
 437        {24576000,      44100,          5120,           441,},
 438        {24576000,      48000,          32,             3,},
 439        {24576000,      88200,          2560,           441,},
 440        {24576000,      96000,          16,             3,},
 441        {24576000,      176400,         1280,           441,},
 442        {24576000,      192000,         8,              3,},
 443        {24576000,      352800,         640,            441,},
 444        {24576000,      384000,         4,              3,},
 445};
 446
 447/* frm_size = 64 */
 448static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
 449        {22579200,      32000,          441,            40,},
 450        {22579200,      44100,          8,              1,},
 451        {22579200,      48000,          147,            20,},
 452        {22579200,      88200,          4,              1,},
 453        {22579200,      96000,          147,            40,},
 454        {22579200,      176400,         2,              1,},
 455        {22579200,      192000,         147,            80,},
 456        {22579200,      352800,         1,              1,},
 457        {24576000,      32000,          12,             1,},
 458        {24576000,      44100,          1280,           147,},
 459        {24576000,      48000,          8,              1,},
 460        {24576000,      88200,          640,            147,},
 461        {24576000,      96000,          4,              1,},
 462        {24576000,      176400,         320,            147,},
 463        {24576000,      192000,         2,              1,},
 464        {24576000,      352800,         160,            147,},
 465        {24576000,      384000,         1,              1,},
 466};
 467
 468struct cs43130_bitwidth_map {
 469        unsigned int bitwidth;
 470        u8 sp_bit;
 471        u8 ch_bit;
 472};
 473
 474struct cs43130_rate_map {
 475        int fs;
 476        int val;
 477};
 478
 479#define HP_LEFT                 0
 480#define HP_RIGHT                1
 481#define CS43130_AC_FREQ         10
 482#define CS43130_DC_THRESHOLD    2
 483
 484#define CS43130_NUM_SUPPLIES    5
 485static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
 486        "VA",
 487        "VP",
 488        "VCP",
 489        "VD",
 490        "VL",
 491};
 492
 493#define CS43130_NUM_INT         5       /* number of interrupt status reg */
 494
 495struct cs43130_dai {
 496        unsigned int                    sclk;
 497        unsigned int                    dai_format;
 498        unsigned int                    dai_mode;
 499};
 500
 501struct  cs43130_private {
 502        struct snd_soc_component        *component;
 503        struct regmap                   *regmap;
 504        struct regulator_bulk_data      supplies[CS43130_NUM_SUPPLIES];
 505        struct gpio_desc                *reset_gpio;
 506        unsigned int                    dev_id; /* codec device ID */
 507        int                             xtal_ibias;
 508
 509        /* shared by both DAIs */
 510        struct mutex                    clk_mutex;
 511        int                             clk_req;
 512        bool                            pll_bypass;
 513        struct completion               xtal_rdy;
 514        struct completion               pll_rdy;
 515        unsigned int                    mclk;
 516        unsigned int                    mclk_int;
 517        int                             mclk_int_src;
 518
 519        /* DAI specific */
 520        struct cs43130_dai              dais[CS43130_DAI_ID_MAX];
 521
 522        /* HP load specific */
 523        bool                            dc_meas;
 524        bool                            ac_meas;
 525        bool                            hpload_done;
 526        struct completion               hpload_evt;
 527        unsigned int                    hpload_stat;
 528        u16                             hpload_dc[2];
 529        u16                             dc_threshold[CS43130_DC_THRESHOLD];
 530        u16                             ac_freq[CS43130_AC_FREQ];
 531        u16                             hpload_ac[CS43130_AC_FREQ][2];
 532        struct workqueue_struct         *wq;
 533        struct work_struct              work;
 534        struct snd_soc_jack             jack;
 535};
 536
 537#endif  /* __CS43130_H__ */
 538