1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * NAU88L24 ALSA SoC audio driver 4 * 5 * Copyright 2016 Nuvoton Technology Corp. 6 * Author: John Hsu <KCHSU0@nuvoton.com> 7 */ 8 9#ifndef __NAU8824_H__ 10#define __NAU8824_H__ 11 12#define NAU8824_REG_RESET 0x00 13#define NAU8824_REG_ENA_CTRL 0x01 14#define NAU8824_REG_CLK_GATING_ENA 0x02 15#define NAU8824_REG_CLK_DIVIDER 0x03 16#define NAU8824_REG_FLL1 0x04 17#define NAU8824_REG_FLL2 0x05 18#define NAU8824_REG_FLL3 0x06 19#define NAU8824_REG_FLL4 0x07 20#define NAU8824_REG_FLL5 0x08 21#define NAU8824_REG_FLL6 0x09 22#define NAU8824_REG_FLL_VCO_RSV 0x0A 23#define NAU8824_REG_JACK_DET_CTRL 0x0D 24#define NAU8824_REG_INTERRUPT_SETTING_1 0x0F 25#define NAU8824_REG_IRQ 0x10 26#define NAU8824_REG_CLEAR_INT_REG 0x11 27#define NAU8824_REG_INTERRUPT_SETTING 0x12 28#define NAU8824_REG_SAR_ADC 0x13 29#define NAU8824_REG_VDET_COEFFICIENT 0x14 30#define NAU8824_REG_VDET_THRESHOLD_1 0x15 31#define NAU8824_REG_VDET_THRESHOLD_2 0x16 32#define NAU8824_REG_VDET_THRESHOLD_3 0x17 33#define NAU8824_REG_VDET_THRESHOLD_4 0x18 34#define NAU8824_REG_GPIO_SEL 0x1A 35#define NAU8824_REG_PORT0_I2S_PCM_CTRL_1 0x1C 36#define NAU8824_REG_PORT0_I2S_PCM_CTRL_2 0x1D 37#define NAU8824_REG_PORT0_LEFT_TIME_SLOT 0x1E 38#define NAU8824_REG_PORT0_RIGHT_TIME_SLOT 0x1F 39#define NAU8824_REG_TDM_CTRL 0x20 40#define NAU8824_REG_ADC_HPF_FILTER 0x23 41#define NAU8824_REG_ADC_FILTER_CTRL 0x24 42#define NAU8824_REG_DAC_FILTER_CTRL_1 0x25 43#define NAU8824_REG_DAC_FILTER_CTRL_2 0x26 44#define NAU8824_REG_NOTCH_FILTER_1 0x27 45#define NAU8824_REG_NOTCH_FILTER_2 0x28 46#define NAU8824_REG_EQ1_LOW 0x29 47#define NAU8824_REG_EQ2_EQ3 0x2A 48#define NAU8824_REG_EQ4_EQ5 0x2B 49#define NAU8824_REG_ADC_CH0_DGAIN_CTRL 0x2D 50#define NAU8824_REG_ADC_CH1_DGAIN_CTRL 0x2E 51#define NAU8824_REG_ADC_CH2_DGAIN_CTRL 0x2F 52#define NAU8824_REG_ADC_CH3_DGAIN_CTRL 0x30 53#define NAU8824_REG_DAC_MUTE_CTRL 0x31 54#define NAU8824_REG_DAC_CH0_DGAIN_CTRL 0x32 55#define NAU8824_REG_DAC_CH1_DGAIN_CTRL 0x33 56#define NAU8824_REG_ADC_TO_DAC_ST 0x34 57#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 0x38 58#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01 0x39 59#define NAU8824_REG_DRC_SLOPE_ADC_CH01 0x3A 60#define NAU8824_REG_DRC_ATKDCY_ADC_CH01 0x3B 61#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23 0x3C 62#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23 0x3D 63#define NAU8824_REG_DRC_SLOPE_ADC_CH23 0x3E 64#define NAU8824_REG_DRC_ATKDCY_ADC_CH23 0x3F 65#define NAU8824_REG_DRC_GAINL_ADC0 0x40 66#define NAU8824_REG_DRC_GAINL_ADC1 0x41 67#define NAU8824_REG_DRC_GAINL_ADC2 0x42 68#define NAU8824_REG_DRC_GAINL_ADC3 0x43 69#define NAU8824_REG_DRC_KNEE_IP12_DAC 0x45 70#define NAU8824_REG_DRC_KNEE_IP34_DAC 0x46 71#define NAU8824_REG_DRC_SLOPE_DAC 0x47 72#define NAU8824_REG_DRC_ATKDCY_DAC 0x48 73#define NAU8824_REG_DRC_GAIN_DAC_CH0 0x49 74#define NAU8824_REG_DRC_GAIN_DAC_CH1 0x4A 75#define NAU8824_REG_MODE 0x4C 76#define NAU8824_REG_MODE1 0x4D 77#define NAU8824_REG_MODE2 0x4E 78#define NAU8824_REG_CLASSG 0x50 79#define NAU8824_REG_OTP_EFUSE 0x51 80#define NAU8824_REG_OTPDOUT_1 0x53 81#define NAU8824_REG_OTPDOUT_2 0x54 82#define NAU8824_REG_MISC_CTRL 0x55 83#define NAU8824_REG_I2C_TIMEOUT 0x56 84#define NAU8824_REG_TEST_MODE 0x57 85#define NAU8824_REG_I2C_DEVICE_ID 0x58 86#define NAU8824_REG_SAR_ADC_DATA_OUT 0x59 87#define NAU8824_REG_BIAS_ADJ 0x66 88#define NAU8824_REG_PGA_GAIN 0x67 89#define NAU8824_REG_TRIM_SETTINGS 0x68 90#define NAU8824_REG_ANALOG_CONTROL_1 0x69 91#define NAU8824_REG_ANALOG_CONTROL_2 0x6A 92#define NAU8824_REG_ENABLE_LO 0x6B 93#define NAU8824_REG_GAIN_LO 0x6C 94#define NAU8824_REG_CLASSD_GAIN_1 0x6D 95#define NAU8824_REG_CLASSD_GAIN_2 0x6E 96#define NAU8824_REG_ANALOG_ADC_1 0x71 97#define NAU8824_REG_ANALOG_ADC_2 0x72 98#define NAU8824_REG_RDAC 0x73 99#define NAU8824_REG_MIC_BIAS 0x74 100#define NAU8824_REG_HS_VOLUME_CONTROL 0x75 101#define NAU8824_REG_BOOST 0x76 102#define NAU8824_REG_FEPGA 0x77 103#define NAU8824_REG_FEPGA_II 0x78 104#define NAU8824_REG_FEPGA_SE 0x79 105#define NAU8824_REG_FEPGA_ATTENUATION 0x7A 106#define NAU8824_REG_ATT_PORT0 0x7B 107#define NAU8824_REG_ATT_PORT1 0x7C 108#define NAU8824_REG_POWER_UP_CONTROL 0x7F 109#define NAU8824_REG_CHARGE_PUMP_CONTROL 0x80 110#define NAU8824_REG_CHARGE_PUMP_INPUT 0x81 111#define NAU8824_REG_MAX NAU8824_REG_CHARGE_PUMP_INPUT 112/* 16-bit control register address, and 16-bits control register data */ 113#define NAU8824_REG_ADDR_LEN 16 114#define NAU8824_REG_DATA_LEN 16 115 116 117/* ENA_CTRL (0x1) */ 118#define NAU8824_DMIC_LCH_EDGE_CH23 (0x1 << 12) 119#define NAU8824_DMIC_LCH_EDGE_CH01 (0x1 << 11) 120#define NAU8824_JD_SLEEP_MODE (0x1 << 10) 121#define NAU8824_ADC_CH3_DMIC_SFT 9 122#define NAU8824_ADC_CH3_DMIC_EN (0x1 << NAU8824_ADC_CH3_DMIC_SFT) 123#define NAU8824_ADC_CH2_DMIC_SFT 8 124#define NAU8824_ADC_CH2_DMIC_EN (0x1 << NAU8824_ADC_CH2_DMIC_SFT) 125#define NAU8824_ADC_CH1_DMIC_SFT 7 126#define NAU8824_ADC_CH1_DMIC_EN (0x1 << NAU8824_ADC_CH1_DMIC_SFT) 127#define NAU8824_ADC_CH0_DMIC_SFT 6 128#define NAU8824_ADC_CH0_DMIC_EN (0x1 << NAU8824_ADC_CH0_DMIC_SFT) 129#define NAU8824_DAC_CH1_EN (0x1 << 5) 130#define NAU8824_DAC_CH0_EN (0x1 << 4) 131#define NAU8824_ADC_CH3_EN (0x1 << 3) 132#define NAU8824_ADC_CH2_EN (0x1 << 2) 133#define NAU8824_ADC_CH1_EN (0x1 << 1) 134#define NAU8824_ADC_CH0_EN 0x1 135 136/* CLK_GATING_ENA (0x02) */ 137#define NAU8824_CLK_ADC_CH23_EN (0x1 << 15) 138#define NAU8824_CLK_ADC_CH01_EN (0x1 << 14) 139#define NAU8824_CLK_DAC_CH1_EN (0x1 << 13) 140#define NAU8824_CLK_DAC_CH0_EN (0x1 << 12) 141#define NAU8824_CLK_I2S_EN (0x1 << 7) 142#define NAU8824_CLK_GAIN_EN (0x1 << 5) 143#define NAU8824_CLK_SAR_EN (0x1 << 3) 144#define NAU8824_CLK_DMIC_CH23_EN (0x1 << 1) 145 146/* CLK_DIVIDER (0x3) */ 147#define NAU8824_CLK_SRC_SFT 15 148#define NAU8824_CLK_SRC_MASK (1 << NAU8824_CLK_SRC_SFT) 149#define NAU8824_CLK_SRC_VCO (1 << NAU8824_CLK_SRC_SFT) 150#define NAU8824_CLK_SRC_MCLK (0 << NAU8824_CLK_SRC_SFT) 151#define NAU8824_CLK_MCLK_SRC_MASK (0xf << 0) 152#define NAU8824_CLK_DMIC_SRC_SFT 10 153#define NAU8824_CLK_DMIC_SRC_MASK (0x7 << NAU8824_CLK_DMIC_SRC_SFT) 154#define NAU8824_CLK_ADC_SRC_SFT 6 155#define NAU8824_CLK_ADC_SRC_MASK (0x3 << NAU8824_CLK_ADC_SRC_SFT) 156#define NAU8824_CLK_DAC_SRC_SFT 4 157#define NAU8824_CLK_DAC_SRC_MASK (0x3 << NAU8824_CLK_DAC_SRC_SFT) 158 159/* FLL1 (0x04) */ 160#define NAU8824_FLL_RATIO_MASK (0x7f << 0) 161 162/* FLL3 (0x06) */ 163#define NAU8824_FLL_INTEGER_MASK (0x3ff << 0) 164#define NAU8824_FLL_CLK_SRC_SFT 10 165#define NAU8824_FLL_CLK_SRC_MASK (0x3 << NAU8824_FLL_CLK_SRC_SFT) 166#define NAU8824_FLL_CLK_SRC_MCLK (0 << NAU8824_FLL_CLK_SRC_SFT) 167#define NAU8824_FLL_CLK_SRC_BLK (0x2 << NAU8824_FLL_CLK_SRC_SFT) 168#define NAU8824_FLL_CLK_SRC_FS (0x3 << NAU8824_FLL_CLK_SRC_SFT) 169 170/* FLL4 (0x07) */ 171#define NAU8824_FLL_REF_DIV_SFT 10 172#define NAU8824_FLL_REF_DIV_MASK (0x3 << NAU8824_FLL_REF_DIV_SFT) 173 174/* FLL5 (0x08) */ 175#define NAU8824_FLL_PDB_DAC_EN (0x1 << 15) 176#define NAU8824_FLL_LOOP_FTR_EN (0x1 << 14) 177#define NAU8824_FLL_CLK_SW_MASK (0x1 << 13) 178#define NAU8824_FLL_CLK_SW_N2 (0x1 << 13) 179#define NAU8824_FLL_CLK_SW_REF (0x0 << 13) 180#define NAU8824_FLL_FTR_SW_MASK (0x1 << 12) 181#define NAU8824_FLL_FTR_SW_ACCU (0x1 << 12) 182#define NAU8824_FLL_FTR_SW_FILTER (0x0 << 12) 183 184/* FLL6 (0x9) */ 185#define NAU8824_DCO_EN (0x1 << 15) 186#define NAU8824_SDM_EN (0x1 << 14) 187 188/* IRQ (0x10) */ 189#define NAU8824_SHORT_CIRCUIT_IRQ (0x1 << 7) 190#define NAU8824_IMPEDANCE_MEAS_IRQ (0x1 << 6) 191#define NAU8824_KEY_RELEASE_IRQ (0x1 << 5) 192#define NAU8824_KEY_LONG_PRESS_IRQ (0x1 << 4) 193#define NAU8824_KEY_SHORT_PRESS_IRQ (0x1 << 3) 194#define NAU8824_JACK_EJECTION_DETECTED (0x1 << 1) 195#define NAU8824_JACK_INSERTION_DETECTED 0x1 196 197/* JACK_DET_CTRL (0x0D) */ 198#define NAU8824_JACK_EJECT_DT_SFT 2 199#define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT) 200#define NAU8824_JACK_LOGIC 0x1 201 202 203/* INTERRUPT_SETTING_1 (0x0F) */ 204#define NAU8824_IRQ_EJECT_EN (0x1 << 9) 205#define NAU8824_IRQ_INSERT_EN (0x1 << 8) 206 207/* INTERRUPT_SETTING (0x12) */ 208#define NAU8824_IRQ_KEY_RELEASE_DIS (0x1 << 5) 209#define NAU8824_IRQ_KEY_SHORT_PRESS_DIS (0x1 << 3) 210#define NAU8824_IRQ_EJECT_DIS (0x1 << 1) 211#define NAU8824_IRQ_INSERT_DIS 0x1 212 213/* SAR_ADC (0x13) */ 214#define NAU8824_SAR_ADC_EN_SFT 12 215#define NAU8824_SAR_TRACKING_GAIN_SFT 8 216#define NAU8824_SAR_TRACKING_GAIN_MASK (0x7 << NAU8824_SAR_TRACKING_GAIN_SFT) 217#define NAU8824_SAR_COMPARE_TIME_SFT 2 218#define NAU8824_SAR_COMPARE_TIME_MASK (3 << 2) 219#define NAU8824_SAR_SAMPLING_TIME_SFT 0 220#define NAU8824_SAR_SAMPLING_TIME_MASK (3 << 0) 221 222/* VDET_COEFFICIENT (0x14) */ 223#define NAU8824_SHORTKEY_DEBOUNCE_SFT 12 224#define NAU8824_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT) 225#define NAU8824_LEVELS_NR_SFT 8 226#define NAU8824_LEVELS_NR_MASK (0x7 << 8) 227#define NAU8824_HYSTERESIS_SFT 0 228#define NAU8824_HYSTERESIS_MASK 0xf 229 230/* PORT0_I2S_PCM_CTRL_1 (0x1C) */ 231#define NAU8824_I2S_BP_SFT 7 232#define NAU8824_I2S_BP_MASK (1 << NAU8824_I2S_BP_SFT) 233#define NAU8824_I2S_BP_INV (1 << NAU8824_I2S_BP_SFT) 234#define NAU8824_I2S_PCMB_SFT 6 235#define NAU8824_I2S_PCMB_EN (1 << NAU8824_I2S_PCMB_SFT) 236#define NAU8824_I2S_DL_SFT 2 237#define NAU8824_I2S_DL_MASK (0x3 << NAU8824_I2S_DL_SFT) 238#define NAU8824_I2S_DL_16 (0 << NAU8824_I2S_DL_SFT) 239#define NAU8824_I2S_DL_20 (1 << NAU8824_I2S_DL_SFT) 240#define NAU8824_I2S_DL_24 (2 << NAU8824_I2S_DL_SFT) 241#define NAU8824_I2S_DL_32 (3 << NAU8824_I2S_DL_SFT) 242#define NAU8824_I2S_DF_MASK 0x3 243#define NAU8824_I2S_DF_RIGTH 0 244#define NAU8824_I2S_DF_LEFT 1 245#define NAU8824_I2S_DF_I2S 2 246#define NAU8824_I2S_DF_PCM_AB 3 247 248 249/* PORT0_I2S_PCM_CTRL_2 (0x1D) */ 250#define NAU8824_I2S_LRC_DIV_SFT 12 251#define NAU8824_I2S_LRC_DIV_MASK (0x3 << NAU8824_I2S_LRC_DIV_SFT) 252#define NAU8824_I2S_MS_SFT 3 253#define NAU8824_I2S_MS_MASK (1 << NAU8824_I2S_MS_SFT) 254#define NAU8824_I2S_MS_MASTER (1 << NAU8824_I2S_MS_SFT) 255#define NAU8824_I2S_MS_SLAVE (0 << NAU8824_I2S_MS_SFT) 256#define NAU8824_I2S_BLK_DIV_MASK 0x7 257 258/* PORT0_LEFT_TIME_SLOT (0x1E) */ 259#define NAU8824_TSLOT_L_MASK 0x3ff 260 261/* TDM_CTRL (0x20) */ 262#define NAU8824_TDM_MODE (0x1 << 15) 263#define NAU8824_TDM_OFFSET_EN (0x1 << 14) 264#define NAU8824_TDM_DACL_RX_SFT 6 265#define NAU8824_TDM_DACL_RX_MASK (0x3 << NAU8824_TDM_DACL_RX_SFT) 266#define NAU8824_TDM_DACR_RX_SFT 4 267#define NAU8824_TDM_DACR_RX_MASK (0x3 << NAU8824_TDM_DACR_RX_SFT) 268#define NAU8824_TDM_TX_MASK 0xf 269 270/* ADC_FILTER_CTRL (0x24) */ 271#define NAU8824_ADC_SYNC_DOWN_MASK 0x3 272#define NAU8824_ADC_SYNC_DOWN_32 0 273#define NAU8824_ADC_SYNC_DOWN_64 1 274#define NAU8824_ADC_SYNC_DOWN_128 2 275#define NAU8824_ADC_SYNC_DOWN_256 3 276 277/* DAC_FILTER_CTRL_1 (0x25) */ 278#define NAU8824_DAC_CICCLP_OFF (0x1 << 7) 279#define NAU8824_DAC_OVERSAMPLE_MASK 0x7 280#define NAU8824_DAC_OVERSAMPLE_64 0 281#define NAU8824_DAC_OVERSAMPLE_256 1 282#define NAU8824_DAC_OVERSAMPLE_128 2 283#define NAU8824_DAC_OVERSAMPLE_32 4 284 285/* DAC_MUTE_CTRL (0x31) */ 286#define NAU8824_DAC_CH01_MIX 0x3 287#define NAU8824_DAC_ZC_EN (0x1 << 11) 288 289/* DAC_CH0_DGAIN_CTRL (0x32) */ 290#define NAU8824_DAC_CH0_SEL_SFT 9 291#define NAU8824_DAC_CH0_SEL_MASK (0x1 << NAU8824_DAC_CH0_SEL_SFT) 292#define NAU8824_DAC_CH0_SEL_I2S0 (0x0 << NAU8824_DAC_CH0_SEL_SFT) 293#define NAU8824_DAC_CH0_SEL_I2S1 (0x1 << NAU8824_DAC_CH0_SEL_SFT) 294#define NAU8824_DAC_CH0_VOL_MASK 0x1ff 295 296/* DAC_CH1_DGAIN_CTRL (0x33) */ 297#define NAU8824_DAC_CH1_SEL_SFT 9 298#define NAU8824_DAC_CH1_SEL_MASK (0x1 << NAU8824_DAC_CH1_SEL_SFT) 299#define NAU8824_DAC_CH1_SEL_I2S0 (0x0 << NAU8824_DAC_CH1_SEL_SFT) 300#define NAU8824_DAC_CH1_SEL_I2S1 (0x1 << NAU8824_DAC_CH1_SEL_SFT) 301#define NAU8824_DAC_CH1_VOL_MASK 0x1ff 302 303/* CLASSG (0x50) */ 304#define NAU8824_CLASSG_TIMER_SFT 8 305#define NAU8824_CLASSG_TIMER_MASK (0x3f << NAU8824_CLASSG_TIMER_SFT) 306#define NAU8824_CLASSG_LDAC_EN_SFT 2 307#define NAU8824_CLASSG_RDAC_EN_SFT 1 308#define NAU8824_CLASSG_EN_SFT 0 309 310/* SAR_ADC_DATA_OUT (0x59) */ 311#define NAU8824_SAR_ADC_DATA_MASK 0xff 312 313/* BIAS_ADJ (0x66) */ 314#define NAU8824_VMID (1 << 6) 315#define NAU8824_VMID_SEL_SFT 4 316#define NAU8824_VMID_SEL_MASK (3 << NAU8824_VMID_SEL_SFT) 317#define NAU8824_DMIC2_EN_SFT 3 318#define NAU8824_DMIC1_EN_SFT 2 319 320/* TRIM_SETTINGS (0x68) */ 321#define NAU8824_DRV_CURR_INC (1 << 15) 322 323/* ANALOG_CONTROL_1 (0x69) */ 324#define NAU8824_DMIC_CLK_DRV_STRG (1 << 3) 325#define NAU8824_DMIC_CLK_SLEW_FAST (0x7) 326 327/* ANALOG_CONTROL_2 (0x6A) */ 328#define NAU8824_CLASSD_CLAMP_DIS_SFT 3 329#define NAU8824_CLASSD_CLAMP_DIS (0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT) 330 331/* ENABLE_LO (0x6B) */ 332#define NAU8824_TEST_DAC_SFT 14 333#define NAU8824_TEST_DAC_EN (0x3 << NAU8824_TEST_DAC_SFT) 334#define NAU8824_DACL_HPR_EN_SFT 3 335#define NAU8824_DACL_HPR_EN (0x1 << NAU8824_DACL_HPR_EN_SFT) 336#define NAU8824_DACR_HPR_EN_SFT 2 337#define NAU8824_DACR_HPR_EN (0x1 << NAU8824_DACR_HPR_EN_SFT) 338#define NAU8824_DACR_HPL_EN_SFT 1 339#define NAU8824_DACR_HPL_EN (0x1 << NAU8824_DACR_HPL_EN_SFT) 340#define NAU8824_DACL_HPL_EN_SFT 0 341#define NAU8824_DACL_HPL_EN 0x1 342 343/* CLASSD_GAIN_1 (0x6D) */ 344#define NAU8824_CLASSD_GAIN_1R_SFT 8 345#define NAU8824_CLASSD_GAIN_1R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT) 346#define NAU8824_CLASSD_EN_SFT 7 347#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT) 348#define NAU8824_CLASSD_GAIN_1L_MASK 0x1f 349 350/* CLASSD_GAIN_2 (0x6E) */ 351#define NAU8824_CLASSD_GAIN_2R_SFT 8 352#define NAU8824_CLASSD_GAIN_2R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT) 353#define NAU8824_CLASSD_EN_SFT 7 354#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT) 355#define NAU8824_CLASSD_GAIN_2L_MASK 0x1f 356 357/* ANALOG_ADC_2 (0x72) */ 358#define NAU8824_ADCR_EN_SFT 7 359#define NAU8824_ADCL_EN_SFT 6 360 361/* RDAC (0x73) */ 362#define NAU8824_DACR_EN_SFT 13 363#define NAU8824_DACL_EN_SFT 12 364#define NAU8824_DACR_CLK_SFT 9 365#define NAU8824_DACL_CLK_SFT 8 366#define NAU8824_RDAC_CLK_DELAY_SFT 4 367#define NAU8824_RDAC_CLK_DELAY_MASK (0x7 << NAU8824_RDAC_CLK_DELAY_SFT) 368#define NAU8824_RDAC_VREF_SFT 2 369#define NAU8824_RDAC_VREF_MASK (0x3 << NAU8824_RDAC_VREF_SFT) 370 371/* MIC_BIAS (0x74) */ 372#define NAU8824_MICBIAS_JKSLV (1 << 14) 373#define NAU8824_MICBIAS_JKR2 (1 << 12) 374#define NAU8824_MICBIAS_POWERUP_SFT 8 375#define NAU8824_MICBIAS_VOLTAGE_SFT 0 376#define NAU8824_MICBIAS_VOLTAGE_MASK 0x7 377 378/* BOOST (0x76) */ 379#define NAU8824_PRECHARGE_DIS (0x1 << 13) 380#define NAU8824_GLOBAL_BIAS_EN (0x1 << 12) 381#define NAU8824_HP_BOOST_DIS_SFT 9 382#define NAU8824_HP_BOOST_DIS (0x1 << NAU8824_HP_BOOST_DIS_SFT) 383#define NAU8824_HP_BOOST_G_DIS_SFT 8 384#define NAU8824_HP_BOOST_G_DIS (0x1 << NAU8824_HP_BOOST_G_DIS_SFT) 385#define NAU8824_SHORT_SHUTDOWN_DIG_EN (1 << 7) 386#define NAU8824_SHORT_SHUTDOWN_EN (1 << 6) 387 388/* FEPGA (0x77) */ 389#define NAU8824_FEPGA_MODER_SHORT_SFT 7 390#define NAU8824_FEPGA_MODER_SHORT_EN (0x1 << NAU8824_FEPGA_MODER_SHORT_SFT) 391#define NAU8824_FEPGA_MODER_MIC2_SFT 5 392#define NAU8824_FEPGA_MODER_MIC2_EN (0x1 << NAU8824_FEPGA_MODER_MIC2_SFT) 393#define NAU8824_FEPGA_MODER_HSMIC_SFT 4 394#define NAU8824_FEPGA_MODER_HSMIC_EN (0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT) 395#define NAU8824_FEPGA_MODEL_SHORT_SFT 3 396#define NAU8824_FEPGA_MODEL_SHORT_EN (0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT) 397#define NAU8824_FEPGA_MODEL_MIC1_SFT 1 398#define NAU8824_FEPGA_MODEL_MIC1_EN (0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT) 399#define NAU8824_FEPGA_MODEL_HSMIC_SFT 0 400#define NAU8824_FEPGA_MODEL_HSMIC_EN (0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT) 401 402/* FEPGA_II (0x78) */ 403#define NAU8824_FEPGA_GAINR_SFT 5 404#define NAU8824_FEPGA_GAINR_MASK (0x1f << NAU8824_FEPGA_GAINR_SFT) 405#define NAU8824_FEPGA_GAINL_SFT 0 406#define NAU8824_FEPGA_GAINL_MASK 0x1f 407 408/* CHARGE_PUMP_CONTROL (0x80) */ 409#define NAU8824_JAMNODCLOW (0x1 << 15) 410#define NAU8824_SPKR_PULL_DOWN (0x1 << 13) 411#define NAU8824_SPKL_PULL_DOWN (0x1 << 12) 412#define NAU8824_POWER_DOWN_DACR (0x1 << 9) 413#define NAU8824_POWER_DOWN_DACL (0x1 << 8) 414#define NAU8824_CHARGE_PUMP_EN_SFT 5 415#define NAU8824_CHARGE_PUMP_EN (0x1 << NAU8824_CHARGE_PUMP_EN_SFT) 416 417 418#define NAU8824_CODEC_DAI "nau8824-hifi" 419 420/* System Clock Source */ 421enum { 422 NAU8824_CLK_DIS, 423 NAU8824_CLK_MCLK, 424 NAU8824_CLK_INTERNAL, 425 NAU8824_CLK_FLL_MCLK, 426 NAU8824_CLK_FLL_BLK, 427 NAU8824_CLK_FLL_FS, 428}; 429 430struct nau8824 { 431 struct device *dev; 432 struct regmap *regmap; 433 struct snd_soc_dapm_context *dapm; 434 struct snd_soc_jack *jack; 435 struct work_struct jdet_work; 436 struct semaphore jd_sem; 437 int fs; 438 int irq; 439 int micbias_voltage; 440 int vref_impedance; 441 int jkdet_polarity; 442 int sar_threshold_num; 443 int sar_threshold[8]; 444 int sar_hysteresis; 445 int sar_voltage; 446 int sar_compare_time; 447 int sar_sampling_time; 448 int key_debounce; 449 int jack_eject_debounce; 450}; 451 452struct nau8824_fll { 453 int mclk_src; 454 int ratio; 455 int fll_frac; 456 int fll_int; 457 int clk_ref_div; 458}; 459 460struct nau8824_fll_attr { 461 unsigned int param; 462 unsigned int val; 463}; 464 465struct nau8824_osr_attr { 466 unsigned int osr; 467 unsigned int clk_src; 468}; 469 470 471int nau8824_enable_jack_detect(struct snd_soc_component *component, 472 struct snd_soc_jack *jack); 473 474#endif /* _NAU8824_H */ 475 476