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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/module.h>
14#include <linux/of_gpio.h>
15#include <linux/pm_runtime.h>
16#include <linux/regulator/consumer.h>
17
18#include <sound/pcm_params.h>
19#include <sound/soc.h>
20#include <sound/tlv.h>
21
22#include "pcm3168a.h"
23
24#define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
25 SNDRV_PCM_FMTBIT_S24_3LE | \
26 SNDRV_PCM_FMTBIT_S24_LE)
27
28#define PCM3168A_FMT_I2S 0x0
29#define PCM3168A_FMT_LEFT_J 0x1
30#define PCM3168A_FMT_RIGHT_J 0x2
31#define PCM3168A_FMT_RIGHT_J_16 0x3
32#define PCM3168A_FMT_DSP_A 0x4
33#define PCM3168A_FMT_DSP_B 0x5
34#define PCM3168A_FMT_I2S_TDM 0x6
35#define PCM3168A_FMT_LEFT_J_TDM 0x7
36#define PCM3168A_FMT_DSP_MASK 0x4
37
38#define PCM3168A_NUM_SUPPLIES 6
39static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = {
40 "VDD1",
41 "VDD2",
42 "VCCAD1",
43 "VCCAD2",
44 "VCCDA1",
45 "VCCDA2"
46};
47
48#define PCM3168A_DAI_DAC 0
49#define PCM3168A_DAI_ADC 1
50
51
52struct pcm3168a_io_params {
53 bool master_mode;
54 unsigned int fmt;
55 int tdm_slots;
56 u32 tdm_mask;
57 int slot_width;
58};
59
60struct pcm3168a_priv {
61 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES];
62 struct regmap *regmap;
63 struct clk *scki;
64 struct gpio_desc *gpio_rst;
65 unsigned long sysclk;
66
67 struct pcm3168a_io_params io_params[2];
68 struct snd_soc_dai_driver dai_drv[2];
69};
70
71static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
72
73static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
74 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
75static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
76 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
77static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
78 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
79static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
80 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
81
82static const char *const pcm3168a_volume_type[] = {
83 "Individual", "Master + Individual" };
84
85static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
86 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
87
88static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
89
90static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
91 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
92
93static const char *const pcm3168a_demp[] = {
94 "Disabled", "48khz", "44.1khz", "32khz" };
95
96static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
97 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
98
99static const char *const pcm3168a_zf_func[] = {
100 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
101 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
102
103static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
104 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
105
106static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
107
108static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
109 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
110
111static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
112
113static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
114 0, 1, pcm3168a_con);
115static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
116 2, 3, pcm3168a_con);
117static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
118 4, 5, pcm3168a_con);
119
120static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
121 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
122
123static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
124 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
125
126static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
127 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
128
129
130static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
131
132
133static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
134
135static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
136 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
137 PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
138 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
139 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
140 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
141 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
142 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
143 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
144 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
145 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
146 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
147 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
148 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
149 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
150 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
151 SOC_SINGLE_RANGE_TLV("Master Playback Volume",
152 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
153 pcm3168a_dac_tlv),
154 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
155 PCM3168A_DAC_VOL_CHAN_START,
156 PCM3168A_DAC_VOL_CHAN_START + 1,
157 0, 54, 255, 0, pcm3168a_dac_tlv),
158 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
159 PCM3168A_DAC_VOL_CHAN_START + 2,
160 PCM3168A_DAC_VOL_CHAN_START + 3,
161 0, 54, 255, 0, pcm3168a_dac_tlv),
162 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
163 PCM3168A_DAC_VOL_CHAN_START + 4,
164 PCM3168A_DAC_VOL_CHAN_START + 5,
165 0, 54, 255, 0, pcm3168a_dac_tlv),
166 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
167 PCM3168A_DAC_VOL_CHAN_START + 6,
168 PCM3168A_DAC_VOL_CHAN_START + 7,
169 0, 54, 255, 0, pcm3168a_dac_tlv),
170 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
171 PCM3168A_ADC_BYP_SHIFT, 1, 1),
172 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
173 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
174 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
175 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
176 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
177 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
178 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
179 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
180 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
181 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
182 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
183 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
184 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
185 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
186 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
187 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
188 SOC_SINGLE_RANGE_TLV("Master Capture Volume",
189 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
190 pcm3168a_adc_tlv),
191 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
192 PCM3168A_ADC_VOL_CHAN_START,
193 PCM3168A_ADC_VOL_CHAN_START + 1,
194 0, 14, 255, 0, pcm3168a_adc_tlv),
195 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
196 PCM3168A_ADC_VOL_CHAN_START + 2,
197 PCM3168A_ADC_VOL_CHAN_START + 3,
198 0, 14, 255, 0, pcm3168a_adc_tlv),
199 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
200 PCM3168A_ADC_VOL_CHAN_START + 4,
201 PCM3168A_ADC_VOL_CHAN_START + 5,
202 0, 14, 255, 0, pcm3168a_adc_tlv)
203};
204
205static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
206 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
207 PCM3168A_DAC_OPEDA_SHIFT, 1),
208 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
209 PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
210 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
211 PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
212 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
213 PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
214
215 SND_SOC_DAPM_OUTPUT("AOUT1L"),
216 SND_SOC_DAPM_OUTPUT("AOUT1R"),
217 SND_SOC_DAPM_OUTPUT("AOUT2L"),
218 SND_SOC_DAPM_OUTPUT("AOUT2R"),
219 SND_SOC_DAPM_OUTPUT("AOUT3L"),
220 SND_SOC_DAPM_OUTPUT("AOUT3R"),
221 SND_SOC_DAPM_OUTPUT("AOUT4L"),
222 SND_SOC_DAPM_OUTPUT("AOUT4R"),
223
224 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
225 PCM3168A_ADC_PSVAD_SHIFT, 1),
226 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
227 PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
228 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
229 PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
230
231 SND_SOC_DAPM_INPUT("AIN1L"),
232 SND_SOC_DAPM_INPUT("AIN1R"),
233 SND_SOC_DAPM_INPUT("AIN2L"),
234 SND_SOC_DAPM_INPUT("AIN2R"),
235 SND_SOC_DAPM_INPUT("AIN3L"),
236 SND_SOC_DAPM_INPUT("AIN3R")
237};
238
239static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
240
241 { "AOUT1L", NULL, "DAC1" },
242 { "AOUT1R", NULL, "DAC1" },
243
244 { "AOUT2L", NULL, "DAC2" },
245 { "AOUT2R", NULL, "DAC2" },
246
247 { "AOUT3L", NULL, "DAC3" },
248 { "AOUT3R", NULL, "DAC3" },
249
250 { "AOUT4L", NULL, "DAC4" },
251 { "AOUT4R", NULL, "DAC4" },
252
253
254 { "ADC1", NULL, "AIN1L" },
255 { "ADC1", NULL, "AIN1R" },
256
257 { "ADC2", NULL, "AIN2L" },
258 { "ADC2", NULL, "AIN2R" },
259
260 { "ADC3", NULL, "AIN3L" },
261 { "ADC3", NULL, "AIN3R" }
262};
263
264static unsigned int pcm3168a_scki_ratios[] = {
265 768,
266 512,
267 384,
268 256,
269 192,
270 128
271};
272
273#define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
274#define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
275
276#define PCM3168A_MAX_SYSCLK 36864000
277
278static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
279{
280 int ret;
281
282 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
283 if (ret)
284 return ret;
285
286
287 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
288
289 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
290 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
291}
292
293static int pcm3168a_mute(struct snd_soc_dai *dai, int mute, int direction)
294{
295 struct snd_soc_component *component = dai->component;
296 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
297
298 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
299
300 return 0;
301}
302
303static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
304 int clk_id, unsigned int freq, int dir)
305{
306 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
307 int ret;
308
309
310
311
312
313 if (freq == 0)
314 return 0;
315
316 if (freq > PCM3168A_MAX_SYSCLK)
317 return -EINVAL;
318
319 ret = clk_set_rate(pcm3168a->scki, freq);
320 if (ret)
321 return ret;
322
323 pcm3168a->sysclk = freq;
324
325 return 0;
326}
327
328static void pcm3168a_update_fixup_pcm_stream(struct snd_soc_dai *dai)
329{
330 struct snd_soc_component *component = dai->component;
331 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
332 u64 formats = SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE;
333 unsigned int channel_max = dai->id == PCM3168A_DAI_DAC ? 8 : 6;
334
335 if (pcm3168a->io_params[dai->id].fmt == PCM3168A_FMT_RIGHT_J) {
336
337 formats |= SNDRV_PCM_FMTBIT_S16_LE;
338
339
340
341
342
343 if (pcm3168a->io_params[dai->id].tdm_slots != 2)
344 channel_max = 2;
345 }
346
347 if (dai->id == PCM3168A_DAI_DAC) {
348 dai->driver->playback.channels_max = channel_max;
349 dai->driver->playback.formats = formats;
350 } else {
351 dai->driver->capture.channels_max = channel_max;
352 dai->driver->capture.formats = formats;
353 }
354}
355
356static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format)
357{
358 struct snd_soc_component *component = dai->component;
359 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
360 u32 fmt, reg, mask, shift;
361 bool master_mode;
362
363 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
364 case SND_SOC_DAIFMT_LEFT_J:
365 fmt = PCM3168A_FMT_LEFT_J;
366 break;
367 case SND_SOC_DAIFMT_I2S:
368 fmt = PCM3168A_FMT_I2S;
369 break;
370 case SND_SOC_DAIFMT_RIGHT_J:
371 fmt = PCM3168A_FMT_RIGHT_J;
372 break;
373 case SND_SOC_DAIFMT_DSP_A:
374 fmt = PCM3168A_FMT_DSP_A;
375 break;
376 case SND_SOC_DAIFMT_DSP_B:
377 fmt = PCM3168A_FMT_DSP_B;
378 break;
379 default:
380 dev_err(component->dev, "unsupported dai format\n");
381 return -EINVAL;
382 }
383
384 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
385 case SND_SOC_DAIFMT_CBS_CFS:
386 master_mode = false;
387 break;
388 case SND_SOC_DAIFMT_CBM_CFM:
389 master_mode = true;
390 break;
391 default:
392 dev_err(component->dev, "unsupported master/slave mode\n");
393 return -EINVAL;
394 }
395
396 switch (format & SND_SOC_DAIFMT_INV_MASK) {
397 case SND_SOC_DAIFMT_NB_NF:
398 break;
399 default:
400 return -EINVAL;
401 }
402
403 if (dai->id == PCM3168A_DAI_DAC) {
404 reg = PCM3168A_DAC_PWR_MST_FMT;
405 mask = PCM3168A_DAC_FMT_MASK;
406 shift = PCM3168A_DAC_FMT_SHIFT;
407 } else {
408 reg = PCM3168A_ADC_MST_FMT;
409 mask = PCM3168A_ADC_FMTAD_MASK;
410 shift = PCM3168A_ADC_FMTAD_SHIFT;
411 }
412
413 pcm3168a->io_params[dai->id].master_mode = master_mode;
414 pcm3168a->io_params[dai->id].fmt = fmt;
415
416 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
417
418 pcm3168a_update_fixup_pcm_stream(dai);
419
420 return 0;
421}
422
423static int pcm3168a_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
424 unsigned int rx_mask, int slots,
425 int slot_width)
426{
427 struct snd_soc_component *component = dai->component;
428 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
429 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
430
431 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
432 dev_err(component->dev,
433 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
434 tx_mask, rx_mask, slots);
435 return -EINVAL;
436 }
437
438 if (slot_width &&
439 (slot_width != 16 && slot_width != 24 && slot_width != 32 )) {
440 dev_err(component->dev, "Unsupported slot_width %d\n",
441 slot_width);
442 return -EINVAL;
443 }
444
445 io_params->tdm_slots = slots;
446 io_params->slot_width = slot_width;
447
448 if (dai->id == PCM3168A_DAI_DAC)
449 io_params->tdm_mask = tx_mask;
450 else
451 io_params->tdm_mask = rx_mask;
452
453 pcm3168a_update_fixup_pcm_stream(dai);
454
455 return 0;
456}
457
458static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
459 struct snd_pcm_hw_params *params,
460 struct snd_soc_dai *dai)
461{
462 struct snd_soc_component *component = dai->component;
463 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
464 struct pcm3168a_io_params *io_params = &pcm3168a->io_params[dai->id];
465 bool master_mode;
466 u32 val, mask, shift, reg;
467 unsigned int rate, fmt, ratio, max_ratio;
468 unsigned int tdm_slots;
469 int i, slot_width;
470
471 rate = params_rate(params);
472
473 ratio = pcm3168a->sysclk / rate;
474
475 if (dai->id == PCM3168A_DAI_DAC) {
476 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC;
477 reg = PCM3168A_DAC_PWR_MST_FMT;
478 mask = PCM3168A_DAC_MSDA_MASK;
479 shift = PCM3168A_DAC_MSDA_SHIFT;
480 } else {
481 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC;
482 reg = PCM3168A_ADC_MST_FMT;
483 mask = PCM3168A_ADC_MSAD_MASK;
484 shift = PCM3168A_ADC_MSAD_SHIFT;
485 }
486
487 master_mode = io_params->master_mode;
488 fmt = io_params->fmt;
489
490 for (i = 0; i < max_ratio; i++) {
491 if (pcm3168a_scki_ratios[i] == ratio)
492 break;
493 }
494
495 if (i == max_ratio) {
496 dev_err(component->dev, "unsupported sysclk ratio\n");
497 return -EINVAL;
498 }
499
500 if (io_params->slot_width)
501 slot_width = io_params->slot_width;
502 else
503 slot_width = params_width(params);
504
505 switch (slot_width) {
506 case 16:
507 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) {
508 dev_err(component->dev, "16-bit slots are supported only for slave mode using right justified\n");
509 return -EINVAL;
510 }
511 fmt = PCM3168A_FMT_RIGHT_J_16;
512 break;
513 case 24:
514 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) {
515 dev_err(component->dev, "24-bit slots not supported in master mode, or slave mode using DSP\n");
516 return -EINVAL;
517 }
518 break;
519 case 32:
520 break;
521 default:
522 dev_err(component->dev, "unsupported frame size: %d\n", slot_width);
523 return -EINVAL;
524 }
525
526 if (io_params->tdm_slots)
527 tdm_slots = io_params->tdm_slots;
528 else
529 tdm_slots = params_channels(params);
530
531
532
533
534
535
536
537
538
539 if (tdm_slots > 2) {
540 switch (fmt) {
541 case PCM3168A_FMT_I2S:
542 case PCM3168A_FMT_DSP_A:
543 fmt = PCM3168A_FMT_I2S_TDM;
544 break;
545 case PCM3168A_FMT_LEFT_J:
546 case PCM3168A_FMT_DSP_B:
547 fmt = PCM3168A_FMT_LEFT_J_TDM;
548 break;
549 default:
550 dev_err(component->dev,
551 "TDM is supported under DSP/I2S/Left_J only\n");
552 return -EINVAL;
553 }
554 }
555
556 if (master_mode)
557 val = ((i + 1) << shift);
558 else
559 val = 0;
560
561 regmap_update_bits(pcm3168a->regmap, reg, mask, val);
562
563 if (dai->id == PCM3168A_DAI_DAC) {
564 mask = PCM3168A_DAC_FMT_MASK;
565 shift = PCM3168A_DAC_FMT_SHIFT;
566 } else {
567 mask = PCM3168A_ADC_FMTAD_MASK;
568 shift = PCM3168A_ADC_FMTAD_SHIFT;
569 }
570
571 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
572
573 return 0;
574}
575
576static u64 pcm3168a_dai_formats[] = {
577
578
579
580
581
582
583
584
585
586 SND_SOC_POSSIBLE_DAIFMT_I2S |
587 SND_SOC_POSSIBLE_DAIFMT_LEFT_J,
588
589
590
591
592
593
594
595 SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
596 SND_SOC_POSSIBLE_DAIFMT_DSP_A |
597 SND_SOC_POSSIBLE_DAIFMT_DSP_B,
598};
599
600static const struct snd_soc_dai_ops pcm3168a_dai_ops = {
601 .set_fmt = pcm3168a_set_dai_fmt,
602 .set_sysclk = pcm3168a_set_dai_sysclk,
603 .hw_params = pcm3168a_hw_params,
604 .mute_stream = pcm3168a_mute,
605 .set_tdm_slot = pcm3168a_set_tdm_slot,
606 .no_capture_mute = 1,
607 .auto_selectable_formats = pcm3168a_dai_formats,
608 .num_auto_selectable_formats = ARRAY_SIZE(pcm3168a_dai_formats),
609};
610
611static struct snd_soc_dai_driver pcm3168a_dais[] = {
612 {
613 .name = "pcm3168a-dac",
614 .id = PCM3168A_DAI_DAC,
615 .playback = {
616 .stream_name = "Playback",
617 .channels_min = 1,
618 .channels_max = 8,
619 .rates = SNDRV_PCM_RATE_8000_192000,
620 .formats = PCM3168A_FORMATS
621 },
622 .ops = &pcm3168a_dai_ops
623 },
624 {
625 .name = "pcm3168a-adc",
626 .id = PCM3168A_DAI_ADC,
627 .capture = {
628 .stream_name = "Capture",
629 .channels_min = 1,
630 .channels_max = 6,
631 .rates = SNDRV_PCM_RATE_8000_96000,
632 .formats = PCM3168A_FORMATS
633 },
634 .ops = &pcm3168a_dai_ops
635 },
636};
637
638static const struct reg_default pcm3168a_reg_default[] = {
639 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
640 { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
641 { PCM3168A_DAC_OP_FLT, 0x00 },
642 { PCM3168A_DAC_INV, 0x00 },
643 { PCM3168A_DAC_MUTE, 0x00 },
644 { PCM3168A_DAC_ZERO, 0x00 },
645 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
646 { PCM3168A_DAC_VOL_MASTER, 0xff },
647 { PCM3168A_DAC_VOL_CHAN_START, 0xff },
648 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
649 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
650 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
651 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
652 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
653 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
654 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
655 { PCM3168A_ADC_SMODE, 0x00 },
656 { PCM3168A_ADC_MST_FMT, 0x00 },
657 { PCM3168A_ADC_PWR_HPFB, 0x00 },
658 { PCM3168A_ADC_SEAD, 0x00 },
659 { PCM3168A_ADC_INV, 0x00 },
660 { PCM3168A_ADC_MUTE, 0x00 },
661 { PCM3168A_ADC_OV, 0x00 },
662 { PCM3168A_ADC_ATT_OVF, 0x00 },
663 { PCM3168A_ADC_VOL_MASTER, 0xd3 },
664 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
665 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
666 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
667 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
668 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
669 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
670};
671
672static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
673{
674 if (reg >= PCM3168A_RST_SMODE)
675 return true;
676 else
677 return false;
678}
679
680static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
681{
682 switch (reg) {
683 case PCM3168A_RST_SMODE:
684 case PCM3168A_DAC_ZERO:
685 case PCM3168A_ADC_OV:
686 return true;
687 default:
688 return false;
689 }
690}
691
692static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
693{
694 if (reg < PCM3168A_RST_SMODE)
695 return false;
696
697 switch (reg) {
698 case PCM3168A_DAC_ZERO:
699 case PCM3168A_ADC_OV:
700 return false;
701 default:
702 return true;
703 }
704}
705
706const struct regmap_config pcm3168a_regmap = {
707 .reg_bits = 8,
708 .val_bits = 8,
709
710 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
711 .reg_defaults = pcm3168a_reg_default,
712 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
713 .readable_reg = pcm3168a_readable_register,
714 .volatile_reg = pcm3168a_volatile_register,
715 .writeable_reg = pcm3168a_writeable_register,
716 .cache_type = REGCACHE_FLAT
717};
718EXPORT_SYMBOL_GPL(pcm3168a_regmap);
719
720static const struct snd_soc_component_driver pcm3168a_driver = {
721 .controls = pcm3168a_snd_controls,
722 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
723 .dapm_widgets = pcm3168a_dapm_widgets,
724 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
725 .dapm_routes = pcm3168a_dapm_routes,
726 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes),
727 .use_pmdown_time = 1,
728 .endianness = 1,
729 .non_legacy_dai_naming = 1,
730};
731
732int pcm3168a_probe(struct device *dev, struct regmap *regmap)
733{
734 struct pcm3168a_priv *pcm3168a;
735 int ret, i;
736
737 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
738 if (pcm3168a == NULL)
739 return -ENOMEM;
740
741 dev_set_drvdata(dev, pcm3168a);
742
743
744
745
746
747
748
749
750
751 pcm3168a->gpio_rst = devm_gpiod_get_optional(dev, "reset",
752 GPIOD_OUT_LOW |
753 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
754 if (IS_ERR(pcm3168a->gpio_rst)) {
755 ret = PTR_ERR(pcm3168a->gpio_rst);
756 if (ret != -EPROBE_DEFER )
757 dev_err(dev, "failed to acquire RST gpio: %d\n", ret);
758
759 return ret;
760 }
761
762 pcm3168a->scki = devm_clk_get(dev, "scki");
763 if (IS_ERR(pcm3168a->scki)) {
764 ret = PTR_ERR(pcm3168a->scki);
765 if (ret != -EPROBE_DEFER)
766 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret);
767 return ret;
768 }
769
770 ret = clk_prepare_enable(pcm3168a->scki);
771 if (ret) {
772 dev_err(dev, "Failed to enable mclk: %d\n", ret);
773 return ret;
774 }
775
776 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
777
778 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
779 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
780
781 ret = devm_regulator_bulk_get(dev,
782 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
783 if (ret) {
784 if (ret != -EPROBE_DEFER)
785 dev_err(dev, "failed to request supplies: %d\n", ret);
786 goto err_clk;
787 }
788
789 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
790 pcm3168a->supplies);
791 if (ret) {
792 dev_err(dev, "failed to enable supplies: %d\n", ret);
793 goto err_clk;
794 }
795
796 pcm3168a->regmap = regmap;
797 if (IS_ERR(pcm3168a->regmap)) {
798 ret = PTR_ERR(pcm3168a->regmap);
799 dev_err(dev, "failed to allocate regmap: %d\n", ret);
800 goto err_regulator;
801 }
802
803 if (pcm3168a->gpio_rst) {
804
805
806
807
808 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
809 } else {
810 ret = pcm3168a_reset(pcm3168a);
811 if (ret) {
812 dev_err(dev, "Failed to reset device: %d\n", ret);
813 goto err_regulator;
814 }
815 }
816
817 pm_runtime_set_active(dev);
818 pm_runtime_enable(dev);
819 pm_runtime_idle(dev);
820
821 memcpy(pcm3168a->dai_drv, pcm3168a_dais, sizeof(pcm3168a->dai_drv));
822 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver,
823 pcm3168a->dai_drv,
824 ARRAY_SIZE(pcm3168a->dai_drv));
825 if (ret) {
826 dev_err(dev, "failed to register component: %d\n", ret);
827 goto err_regulator;
828 }
829
830 return 0;
831
832err_regulator:
833 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
834 pcm3168a->supplies);
835err_clk:
836 clk_disable_unprepare(pcm3168a->scki);
837
838 return ret;
839}
840EXPORT_SYMBOL_GPL(pcm3168a_probe);
841
842static void pcm3168a_disable(struct device *dev)
843{
844 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
845
846 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
847 pcm3168a->supplies);
848 clk_disable_unprepare(pcm3168a->scki);
849}
850
851void pcm3168a_remove(struct device *dev)
852{
853 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
854
855
856
857
858
859
860
861 gpiod_set_value_cansleep(pcm3168a->gpio_rst, 1);
862 pm_runtime_disable(dev);
863#ifndef CONFIG_PM
864 pcm3168a_disable(dev);
865#endif
866}
867EXPORT_SYMBOL_GPL(pcm3168a_remove);
868
869#ifdef CONFIG_PM
870static int pcm3168a_rt_resume(struct device *dev)
871{
872 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
873 int ret;
874
875 ret = clk_prepare_enable(pcm3168a->scki);
876 if (ret) {
877 dev_err(dev, "Failed to enable mclk: %d\n", ret);
878 return ret;
879 }
880
881 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
882 pcm3168a->supplies);
883 if (ret) {
884 dev_err(dev, "Failed to enable supplies: %d\n", ret);
885 goto err_clk;
886 }
887
888 ret = pcm3168a_reset(pcm3168a);
889 if (ret) {
890 dev_err(dev, "Failed to reset device: %d\n", ret);
891 goto err_regulator;
892 }
893
894 regcache_cache_only(pcm3168a->regmap, false);
895
896 regcache_mark_dirty(pcm3168a->regmap);
897
898 ret = regcache_sync(pcm3168a->regmap);
899 if (ret) {
900 dev_err(dev, "Failed to sync regmap: %d\n", ret);
901 goto err_regulator;
902 }
903
904 return 0;
905
906err_regulator:
907 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
908 pcm3168a->supplies);
909err_clk:
910 clk_disable_unprepare(pcm3168a->scki);
911
912 return ret;
913}
914
915static int pcm3168a_rt_suspend(struct device *dev)
916{
917 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
918
919 regcache_cache_only(pcm3168a->regmap, true);
920
921 pcm3168a_disable(dev);
922
923 return 0;
924}
925#endif
926
927const struct dev_pm_ops pcm3168a_pm_ops = {
928 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
929};
930EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
931
932MODULE_DESCRIPTION("PCM3168A codec driver");
933MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
934MODULE_LICENSE("GPL v2");
935
