LXR linux/sound/soc/codecs/rk817

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// rk817 ALSA SoC Audio driver
   4//
   5// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
   6
   7#include <linux/clk.h>
   8#include <linux/device.h>
   9#include <linux/delay.h>
  10#include <linux/mfd/rk808.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/of_gpio.h>
  14#include <linux/platform_device.h>
  15#include <linux/regmap.h>
  16#include <sound/core.h>
  17#include <sound/pcm_params.h>
  18#include <sound/soc.h>
  19#include <sound/tlv.h>
  20
  21struct rk817_codec_priv {
  22        struct snd_soc_component *component;
  23        struct rk808 *rk808;
  24        struct clk *mclk;
  25        unsigned int stereo_sysclk;
  26        bool mic_in_differential;
  27};
  28
  29/*
  30 * This sets the codec up with the values defined in the default implementation including the APLL
  31 * from the Rockchip vendor kernel. I do not know if these values are universal despite differing
  32 * from the default values defined above and taken from the datasheet, or implementation specific.
  33 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
  34 * Additionally, I do not know according to the documentation the units accepted for the clock
  35 * values, so for the moment those are left unvalidated.
  36 */
  37
  38static int rk817_init(struct snd_soc_component *component)
  39{
  40        struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
  41
  42        snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02);
  43        snd_soc_component_write(component, RK817_CODEC_DDAC_SR_LMT0, 0x02);
  44        snd_soc_component_write(component, RK817_CODEC_DADC_SR_ACL0, 0x02);
  45        snd_soc_component_write(component, RK817_CODEC_DTOP_VUCTIME, 0xf4);
  46        if (rk817->mic_in_differential) {
  47                snd_soc_component_update_bits(component, RK817_CODEC_AMIC_CFG0, MIC_DIFF_MASK,
  48                        MIC_DIFF_EN);
  49        }
  50
  51        return 0;
  52}
  53
  54static int rk817_set_component_pll(struct snd_soc_component *component,
  55                int pll_id, int source, unsigned int freq_in,
  56                unsigned int freq_out)
  57{
  58        /* Set resistor value and charge pump current for PLL. */
  59        snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58);
  60        /* Set the PLL feedback clock divide value (values not documented). */
  61        snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d);
  62        /* Set the PLL pre-divide value (values not documented). */
  63        snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c);
  64        /* Set the PLL VCO output clock divide and PLL divided ratio of PLL High Clk (values not
  65         * documented).
  66         */
  67        snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
  68
  69        return 0;
  70}
  71
  72/*
  73 * DDAC/DADC L/R volume setting
  74 * 0db~-95db, 0.375db/step, for example:
  75 * 0x00: 0dB
  76 * 0xff: -95dB
  77 */
  78
  79static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
  80
  81/*
  82 * PGA GAIN L/R volume setting
  83 * 27db~-18db, 3db/step, for example:
  84 * 0x0: -18dB
  85 * 0xf: 27dB
  86 */
  87
  88static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
  89
  90static const struct snd_kcontrol_new rk817_volume_controls[] = {
  91        SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume", RK817_CODEC_DDAC_VOLL,
  92                RK817_CODEC_DDAC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv),
  93        SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume", RK817_CODEC_DADC_VOLL,
  94                RK817_CODEC_DADC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv),
  95        SOC_DOUBLE_TLV("Mic Capture Gain", RK817_CODEC_DMIC_PGA_GAIN, 4, 0, 0xf, 0,
  96                rk817_gain_tlv),
  97};
  98
  99/* Since the speaker output and L headphone pin are internally the same, make audio path mutually
 100 * exclusive with a mux.
 101 */
 102
 103static const char *dac_mux_text[] = {
 104        "HP",
 105        "SPK",
 106};
 107
 108static SOC_ENUM_SINGLE_VIRT_DECL(dac_enum, dac_mux_text);
 109
 110static const struct snd_kcontrol_new dac_mux =
 111        SOC_DAPM_ENUM("Playback Mux", dac_enum);
 112
 113static const struct snd_soc_dapm_widget rk817_dapm_widgets[] = {
 114
 115        /* capture/playback common */
 116        SND_SOC_DAPM_SUPPLY("LDO Regulator", RK817_CODEC_AREF_RTCFG1, 6, 0, NULL, 0),
 117        SND_SOC_DAPM_SUPPLY("IBIAS Block", RK817_CODEC_AREF_RTCFG1, 2, 1, NULL, 0),
 118        SND_SOC_DAPM_SUPPLY("VAvg Buffer", RK817_CODEC_AREF_RTCFG1, 1, 1, NULL, 0),
 119        SND_SOC_DAPM_SUPPLY("PLL Power", RK817_CODEC_APLL_CFG5, 0, 1, NULL, 0),
 120        SND_SOC_DAPM_SUPPLY("I2S TX1 Transfer Start", RK817_CODEC_DI2S_RXCMD_TSD, 5, 0, NULL, 0),
 121
 122        /* capture path common */
 123        SND_SOC_DAPM_SUPPLY("ADC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 7, 0, NULL, 0),
 124        SND_SOC_DAPM_SUPPLY("I2S TX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 6, 0, NULL, 0),
 125        SND_SOC_DAPM_SUPPLY("ADC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 5, 0, NULL, 0),
 126        SND_SOC_DAPM_SUPPLY("I2S TX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 4, 0, NULL, 0),
 127        SND_SOC_DAPM_SUPPLY("MIC Power On", RK817_CODEC_AMIC_CFG0, 6, 1, NULL, 0),
 128        SND_SOC_DAPM_SUPPLY("I2S TX3 Transfer Start", RK817_CODEC_DI2S_TXCR3_TXCMD, 7, 0, NULL, 0),
 129        SND_SOC_DAPM_SUPPLY("I2S TX3 Right Justified", RK817_CODEC_DI2S_TXCR3_TXCMD, 3, 0, NULL, 0),
 130
 131        /* capture path L */
 132        SND_SOC_DAPM_ADC("ADC L", "Capture", RK817_CODEC_AADC_CFG0, 7, 1),
 133        SND_SOC_DAPM_SUPPLY("PGA L Power On", RK817_CODEC_AMIC_CFG0, 5, 1, NULL, 0),
 134        SND_SOC_DAPM_SUPPLY("Mic Boost L1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
 135        SND_SOC_DAPM_SUPPLY("Mic Boost L2", RK817_CODEC_AMIC_CFG0, 2, 0, NULL, 0),
 136
 137        /* capture path R */
 138        SND_SOC_DAPM_ADC("ADC R", "Capture", RK817_CODEC_AADC_CFG0, 6, 1),
 139        SND_SOC_DAPM_SUPPLY("PGA R Power On", RK817_CODEC_AMIC_CFG0, 4, 1, NULL, 0),
 140        SND_SOC_DAPM_SUPPLY("Mic Boost R1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
 141        SND_SOC_DAPM_SUPPLY("Mic Boost R2", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0),
 142
 143        /* playback path common */
 144        SND_SOC_DAPM_SUPPLY("DAC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 3, 0, NULL, 0),
 145        SND_SOC_DAPM_SUPPLY("I2S RX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 2, 0, NULL, 0),
 146        SND_SOC_DAPM_SUPPLY("DAC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 1, 0, NULL, 0),
 147        SND_SOC_DAPM_SUPPLY("I2S RX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 0, 0, NULL, 0),
 148        SND_SOC_DAPM_SUPPLY("DAC Bias", RK817_CODEC_ADAC_CFG1, 3, 1, NULL, 0),
 149        SND_SOC_DAPM_SUPPLY("DAC Mute Off", RK817_CODEC_DDAC_MUTE_MIXCTL, 0, 1, NULL, 0),
 150
 151        /* playback path speaker */
 152        SND_SOC_DAPM_SUPPLY("Class D Mode", RK817_CODEC_DDAC_MUTE_MIXCTL, 4, 0, NULL, 0),
 153        SND_SOC_DAPM_SUPPLY("High Pass Filter", RK817_CODEC_DDAC_MUTE_MIXCTL, 7, 0, NULL, 0),
 154        SND_SOC_DAPM_DAC("SPK DAC", "Playback", RK817_CODEC_ADAC_CFG1, 2, 1),
 155        SND_SOC_DAPM_SUPPLY("Enable Class D", RK817_CODEC_ACLASSD_CFG1, 7, 0, NULL, 0),
 156        SND_SOC_DAPM_SUPPLY("Disable Class D Mute Ramp", RK817_CODEC_ACLASSD_CFG1, 6, 1, NULL, 0),
 157        SND_SOC_DAPM_SUPPLY("Class D Mute Rate 1", RK817_CODEC_ACLASSD_CFG1, 3, 0, NULL, 0),
 158        SND_SOC_DAPM_SUPPLY("Class D Mute Rate 2", RK817_CODEC_ACLASSD_CFG1, 2, 1, NULL, 0),
 159        SND_SOC_DAPM_SUPPLY("Class D OCPP 2", RK817_CODEC_ACLASSD_CFG2, 5, 0, NULL, 0),
 160        SND_SOC_DAPM_SUPPLY("Class D OCPP 3", RK817_CODEC_ACLASSD_CFG2, 4, 0, NULL, 0),
 161        SND_SOC_DAPM_SUPPLY("Class D OCPN 2", RK817_CODEC_ACLASSD_CFG2, 1, 0, NULL, 0),
 162        SND_SOC_DAPM_SUPPLY("Class D OCPN 3", RK817_CODEC_ACLASSD_CFG2, 0, 0, NULL, 0),
 163
 164        /* playback path headphones */
 165        SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", RK817_CODEC_AHP_CP, 4, 0, NULL, 0),
 166        SND_SOC_DAPM_SUPPLY("Headphone CP Discharge LDO", RK817_CODEC_AHP_CP, 3, 1, NULL, 0),
 167        SND_SOC_DAPM_SUPPLY("Headphone OStage", RK817_CODEC_AHP_CFG0, 6, 1, NULL, 0),
 168        SND_SOC_DAPM_SUPPLY("Headphone Pre Amp", RK817_CODEC_AHP_CFG0, 5, 1, NULL, 0),
 169        SND_SOC_DAPM_DAC("DAC L", "Playback", RK817_CODEC_ADAC_CFG1, 1, 1),
 170        SND_SOC_DAPM_DAC("DAC R", "Playback", RK817_CODEC_ADAC_CFG1, 0, 1),
 171
 172        /* Mux for input/output path selection */
 173        SND_SOC_DAPM_MUX("Playback Mux", SND_SOC_NOPM, 1, 0, &dac_mux),
 174
 175        /* Pins for Simple Card Bindings */
 176        SND_SOC_DAPM_INPUT("MICL"),
 177        SND_SOC_DAPM_INPUT("MICR"),
 178        SND_SOC_DAPM_OUTPUT("HPOL"),
 179        SND_SOC_DAPM_OUTPUT("HPOR"),
 180        SND_SOC_DAPM_OUTPUT("SPKO"),
 181};
 182
 183static const struct snd_soc_dapm_route rk817_dapm_routes[] = {
 184
 185        /* capture path */
 186        /* left mic */
 187        {"ADC L", NULL, "LDO Regulator"},
 188        {"ADC L", NULL, "IBIAS Block"},
 189        {"ADC L", NULL, "VAvg Buffer"},
 190        {"ADC L", NULL, "PLL Power"},
 191        {"ADC L", NULL, "ADC Clock"},
 192        {"ADC L", NULL, "I2S TX Clock"},
 193        {"ADC L", NULL, "ADC Channel Enable"},
 194        {"ADC L", NULL, "I2S TX Channel Enable"},
 195        {"ADC L", NULL, "I2S TX1 Transfer Start"},
 196        {"MICL", NULL, "MIC Power On"},
 197        {"MICL", NULL, "PGA L Power On"},
 198        {"MICL", NULL, "Mic Boost L1"},
 199        {"MICL", NULL, "Mic Boost L2"},
 200        {"MICL", NULL, "I2S TX3 Transfer Start"},
 201        {"MICL", NULL, "I2S TX3 Right Justified"},
 202        {"ADC L", NULL, "MICL"},
 203
 204        /* right mic */
 205        {"ADC R", NULL, "LDO Regulator"},
 206        {"ADC R", NULL, "IBIAS Block"},
 207        {"ADC R", NULL, "VAvg Buffer"},
 208        {"ADC R", NULL, "PLL Power"},
 209        {"ADC R", NULL, "ADC Clock"},
 210        {"ADC R", NULL, "I2S TX Clock"},
 211        {"ADC R", NULL, "ADC Channel Enable"},
 212        {"ADC R", NULL, "I2S TX Channel Enable"},
 213        {"ADC R", NULL, "I2S TX1 Transfer Start"},
 214        {"MICR", NULL, "MIC Power On"},
 215        {"MICR", NULL, "PGA R Power On"},
 216        {"MICR", NULL, "Mic Boost R1"},
 217        {"MICR", NULL, "Mic Boost R2"},
 218        {"MICR", NULL, "I2S TX3 Transfer Start"},
 219        {"MICR", NULL, "I2S TX3 Right Justified"},
 220        {"ADC R", NULL, "MICR"},
 221
 222        /* playback path */
 223        /* speaker path */
 224        {"SPK DAC", NULL, "LDO Regulator"},
 225        {"SPK DAC", NULL, "IBIAS Block"},
 226        {"SPK DAC", NULL, "VAvg Buffer"},
 227        {"SPK DAC", NULL, "PLL Power"},
 228        {"SPK DAC", NULL, "I2S TX1 Transfer Start"},
 229        {"SPK DAC", NULL, "DAC Clock"},
 230        {"SPK DAC", NULL, "I2S RX Clock"},
 231        {"SPK DAC", NULL, "DAC Channel Enable"},
 232        {"SPK DAC", NULL, "I2S RX Channel Enable"},
 233        {"SPK DAC", NULL, "Class D Mode"},
 234        {"SPK DAC", NULL, "DAC Bias"},
 235        {"SPK DAC", NULL, "DAC Mute Off"},
 236        {"SPK DAC", NULL, "Enable Class D"},
 237        {"SPK DAC", NULL, "Disable Class D Mute Ramp"},
 238        {"SPK DAC", NULL, "Class D Mute Rate 1"},
 239        {"SPK DAC", NULL, "Class D Mute Rate 2"},
 240        {"SPK DAC", NULL, "Class D OCPP 2"},
 241        {"SPK DAC", NULL, "Class D OCPP 3"},
 242        {"SPK DAC", NULL, "Class D OCPN 2"},
 243        {"SPK DAC", NULL, "Class D OCPN 3"},
 244        {"SPK DAC", NULL, "High Pass Filter"},
 245
 246        /* headphone path L */
 247        {"DAC L", NULL, "LDO Regulator"},
 248        {"DAC L", NULL, "IBIAS Block"},
 249        {"DAC L", NULL, "VAvg Buffer"},
 250        {"DAC L", NULL, "PLL Power"},
 251        {"DAC L", NULL, "I2S TX1 Transfer Start"},
 252        {"DAC L", NULL, "DAC Clock"},
 253        {"DAC L", NULL, "I2S RX Clock"},
 254        {"DAC L", NULL, "DAC Channel Enable"},
 255        {"DAC L", NULL, "I2S RX Channel Enable"},
 256        {"DAC L", NULL, "DAC Bias"},
 257        {"DAC L", NULL, "DAC Mute Off"},
 258        {"DAC L", NULL, "Headphone Charge Pump"},
 259        {"DAC L", NULL, "Headphone CP Discharge LDO"},
 260        {"DAC L", NULL, "Headphone OStage"},
 261        {"DAC L", NULL, "Headphone Pre Amp"},
 262
 263        /* headphone path R */
 264        {"DAC R", NULL, "LDO Regulator"},
 265        {"DAC R", NULL, "IBIAS Block"},
 266        {"DAC R", NULL, "VAvg Buffer"},
 267        {"DAC R", NULL, "PLL Power"},
 268        {"DAC R", NULL, "I2S TX1 Transfer Start"},
 269        {"DAC R", NULL, "DAC Clock"},
 270        {"DAC R", NULL, "I2S RX Clock"},
 271        {"DAC R", NULL, "DAC Channel Enable"},
 272        {"DAC R", NULL, "I2S RX Channel Enable"},
 273        {"DAC R", NULL, "DAC Bias"},
 274        {"DAC R", NULL, "DAC Mute Off"},
 275        {"DAC R", NULL, "Headphone Charge Pump"},
 276        {"DAC R", NULL, "Headphone CP Discharge LDO"},
 277        {"DAC R", NULL, "Headphone OStage"},
 278        {"DAC R", NULL, "Headphone Pre Amp"},
 279
 280        /* mux path for output selection */
 281        {"Playback Mux", "HP", "DAC L"},
 282        {"Playback Mux", "HP", "DAC R"},
 283        {"Playback Mux", "SPK", "SPK DAC"},
 284        {"SPKO", NULL, "Playback Mux"},
 285        {"HPOL", NULL, "Playback Mux"},
 286        {"HPOR", NULL, "Playback Mux"},
 287};
 288
 289static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 290                                int clk_id, unsigned int freq, int dir)
 291{
 292        struct snd_soc_component *component = codec_dai->component;
 293        struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
 294
 295        rk817->stereo_sysclk = freq;
 296
 297        return 0;
 298}
 299
 300static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai,
 301                             unsigned int fmt)
 302{
 303        struct snd_soc_component *component = codec_dai->component;
 304        unsigned int i2s_mst = 0;
 305
 306        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 307        case SND_SOC_DAIFMT_CBS_CFS:
 308                i2s_mst |= RK817_I2S_MODE_SLV;
 309                break;
 310        case SND_SOC_DAIFMT_CBM_CFM:
 311                i2s_mst |= RK817_I2S_MODE_MST;
 312                break;
 313        default:
 314                dev_err(component->dev, "%s : set master mask failed!\n", __func__);
 315                return -EINVAL;
 316        }
 317
 318        snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM,
 319                                      RK817_I2S_MODE_MASK, i2s_mst);
 320
 321        return 0;
 322}
 323
 324static int rk817_hw_params(struct snd_pcm_substream *substream,
 325                           struct snd_pcm_hw_params *params,
 326                            struct snd_soc_dai *dai)
 327{
 328        struct snd_soc_component *component = dai->component;
 329
 330        switch (params_format(params)) {
 331        case SNDRV_PCM_FORMAT_S16_LE:
 332                snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
 333                                        VDW_RX_16BITS);
 334                snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
 335                                        VDW_TX_16BITS);
 336                break;
 337        case SNDRV_PCM_FORMAT_S24_LE:
 338        case SNDRV_PCM_FORMAT_S32_LE:
 339                snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
 340                                        VDW_RX_24BITS);
 341                snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
 342                                        VDW_TX_24BITS);
 343                break;
 344        default:
 345                return -EINVAL;
 346        }
 347
 348        return 0;
 349}
 350
 351static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
 352{
 353        struct snd_soc_component *component = dai->component;
 354
 355        if (mute)
 356                snd_soc_component_update_bits(component,
 357                                              RK817_CODEC_DDAC_MUTE_MIXCTL,
 358                                              DACMT_MASK, DACMT_ENABLE);
 359        else
 360                snd_soc_component_update_bits(component,
 361                                              RK817_CODEC_DDAC_MUTE_MIXCTL,
 362                                              DACMT_MASK, DACMT_DISABLE);
 363
 364        return 0;
 365}
 366
 367#define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
 368                              SNDRV_PCM_RATE_16000 |    \
 369                              SNDRV_PCM_RATE_32000 |    \
 370                              SNDRV_PCM_RATE_44100 |    \
 371                              SNDRV_PCM_RATE_48000 |    \
 372                              SNDRV_PCM_RATE_96000)
 373
 374#define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
 375                              SNDRV_PCM_RATE_16000 |    \
 376                              SNDRV_PCM_RATE_32000 |    \
 377                              SNDRV_PCM_RATE_44100 |    \
 378                              SNDRV_PCM_RATE_48000 |    \
 379                              SNDRV_PCM_RATE_96000)
 380
 381#define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 382                        SNDRV_PCM_FMTBIT_S20_3LE |\
 383                        SNDRV_PCM_FMTBIT_S24_LE |\
 384                        SNDRV_PCM_FMTBIT_S32_LE)
 385
 386static const struct snd_soc_dai_ops rk817_dai_ops = {
 387        .hw_params      = rk817_hw_params,
 388        .set_fmt        = rk817_set_dai_fmt,
 389        .set_sysclk     = rk817_set_dai_sysclk,
 390        .mute_stream    = rk817_digital_mute,
 391        .no_capture_mute        = 1,
 392};
 393
 394static struct snd_soc_dai_driver rk817_dai[] = {
 395        {
 396                .name = "rk817-hifi",
 397                .playback = {
 398                        .stream_name = "Playback",
 399                        .channels_min = 2,
 400                        .channels_max = 8,
 401                        .rates = RK817_PLAYBACK_RATES,
 402                        .formats = RK817_FORMATS,
 403                },
 404                .capture = {
 405                        .stream_name = "Capture",
 406                        .channels_min = 1,
 407                        .channels_max = 2,
 408                        .rates = RK817_CAPTURE_RATES,
 409                        .formats = RK817_FORMATS,
 410                },
 411                .ops = &rk817_dai_ops,
 412        },
 413};
 414
 415static int rk817_probe(struct snd_soc_component *component)
 416{
 417        struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
 418        struct rk808 *rk808 = dev_get_drvdata(component->dev->parent);
 419
 420        snd_soc_component_init_regmap(component, rk808->regmap);
 421        rk817->component = component;
 422
 423        snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40);
 424
 425        rk817_init(component);
 426
 427        /* setting initial pll values so that we can continue to leverage simple-audio-card.
 428         * The values aren't important since no parameters are used.
 429         */
 430
 431        snd_soc_component_set_pll(component, 0, 0, 0, 0);
 432
 433        return 0;
 434}
 435
 436static void rk817_remove(struct snd_soc_component *component)
 437{
 438        snd_soc_component_exit_regmap(component);
 439}
 440
 441static const struct snd_soc_component_driver soc_codec_dev_rk817 = {
 442        .probe = rk817_probe,
 443        .remove = rk817_remove,
 444        .idle_bias_on = 1,
 445        .use_pmdown_time = 1,
 446        .endianness = 1,
 447        .non_legacy_dai_naming = 1,
 448        .controls = rk817_volume_controls,
 449        .num_controls = ARRAY_SIZE(rk817_volume_controls),
 450        .dapm_routes = rk817_dapm_routes,
 451        .num_dapm_routes = ARRAY_SIZE(rk817_dapm_routes),
 452        .dapm_widgets = rk817_dapm_widgets,
 453        .num_dapm_widgets = ARRAY_SIZE(rk817_dapm_widgets),
 454        .set_pll = rk817_set_component_pll,
 455};
 456
 457static void rk817_codec_parse_dt_property(struct device *dev,
 458                                         struct rk817_codec_priv *rk817)
 459{
 460        struct device_node *node;
 461
 462        node = of_get_child_by_name(dev->parent->of_node, "codec");
 463        if (!node) {
 464                dev_dbg(dev, "%s() Can not get child: codec\n",
 465                        __func__);
 466        }
 467
 468        rk817->mic_in_differential =
 469                        of_property_read_bool(node, "rockchip,mic-in-differential");
 470
 471        of_node_put(node);
 472}
 473
 474static int rk817_platform_probe(struct platform_device *pdev)
 475{
 476        struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
 477        struct rk817_codec_priv *rk817_codec_data;
 478        int ret;
 479
 480        rk817_codec_data = devm_kzalloc(&pdev->dev,
 481                                        sizeof(struct rk817_codec_priv),
 482                                        GFP_KERNEL);
 483        if (!rk817_codec_data)
 484                return -ENOMEM;
 485
 486        platform_set_drvdata(pdev, rk817_codec_data);
 487
 488        rk817_codec_data->rk808 = rk808;
 489
 490        rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data);
 491
 492        rk817_codec_data->mclk = clk_get(pdev->dev.parent, "mclk");
 493        if (IS_ERR(rk817_codec_data->mclk)) {
 494                dev_dbg(&pdev->dev, "Unable to get mclk\n");
 495                ret = -ENXIO;
 496                goto err_;
 497        }
 498
 499        ret = clk_prepare_enable(rk817_codec_data->mclk);
 500        if (ret < 0) {
 501                dev_err(&pdev->dev, "%s() clock prepare error %d\n",
 502                        __func__, ret);
 503                goto err_;
 504        }
 505
 506        ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817,
 507                                              rk817_dai, ARRAY_SIZE(rk817_dai));
 508        if (ret < 0) {
 509                dev_err(&pdev->dev, "%s() register codec error %d\n",
 510                        __func__, ret);
 511                goto err_;
 512        }
 513
 514        return 0;
 515err_:
 516
 517        return ret;
 518}
 519
 520static int rk817_platform_remove(struct platform_device *pdev)
 521{
 522        struct rk817_codec_priv *rk817 = platform_get_drvdata(pdev);
 523
 524        clk_disable_unprepare(rk817->mclk);
 525
 526        return 0;
 527}
 528
 529static struct platform_driver rk817_codec_driver = {
 530        .driver = {
 531                   .name = "rk817-codec",
 532                   },
 533        .probe = rk817_platform_probe,
 534        .remove = rk817_platform_remove,
 535};
 536
 537module_platform_driver(rk817_codec_driver);
 538
 539MODULE_DESCRIPTION("ASoC RK817 codec driver");
 540MODULE_AUTHOR("binyuan <kevan.lan@rock-chips.com>");
 541MODULE_LICENSE("GPL v2");
 542