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8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/pm_runtime.h>
11#include <linux/mod_devicetable.h>
12#include <linux/soundwire/sdw.h>
13#include <linux/soundwire/sdw_type.h>
14#include <linux/soundwire/sdw_registers.h>
15#include <linux/module.h>
16#include <linux/regmap.h>
17#include <sound/core.h>
18#include <sound/pcm.h>
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include <sound/soc-dapm.h>
22#include <sound/initval.h>
23
24#include "rt1308.h"
25#include "rt1308-sdw.h"
26
27static bool rt1308_readable_register(struct device *dev, unsigned int reg)
28{
29 switch (reg) {
30 case 0x00e0:
31 case 0x00f0:
32 case 0x2f01 ... 0x2f07:
33 case 0x3000 ... 0x3001:
34 case 0x3004 ... 0x3005:
35 case 0x3008:
36 case 0x300a:
37 case 0xc000 ... 0xcff3:
38 return true;
39 default:
40 return false;
41 }
42}
43
44static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
45{
46 switch (reg) {
47 case 0x2f01 ... 0x2f07:
48 case 0x3000 ... 0x3001:
49 case 0x3004 ... 0x3005:
50 case 0x3008:
51 case 0x300a:
52 case 0xc000:
53 return true;
54 default:
55 return false;
56 }
57}
58
59static const struct regmap_config rt1308_sdw_regmap = {
60 .reg_bits = 32,
61 .val_bits = 8,
62 .readable_reg = rt1308_readable_register,
63 .volatile_reg = rt1308_volatile_register,
64 .max_register = 0xcfff,
65 .reg_defaults = rt1308_reg_defaults,
66 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
67 .cache_type = REGCACHE_RBTREE,
68 .use_single_read = true,
69 .use_single_write = true,
70};
71
72
73#define RT1308_CLK_FREQ_9600000HZ 9600000
74#define RT1308_CLK_FREQ_12000000HZ 12000000
75#define RT1308_CLK_FREQ_6000000HZ 6000000
76#define RT1308_CLK_FREQ_4800000HZ 4800000
77#define RT1308_CLK_FREQ_2400000HZ 2400000
78#define RT1308_CLK_FREQ_12288000HZ 12288000
79
80static int rt1308_clock_config(struct device *dev)
81{
82 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
83 unsigned int clk_freq, value;
84
85 clk_freq = (rt1308->params.curr_dr_freq >> 1);
86
87 switch (clk_freq) {
88 case RT1308_CLK_FREQ_12000000HZ:
89 value = 0x0;
90 break;
91 case RT1308_CLK_FREQ_6000000HZ:
92 value = 0x1;
93 break;
94 case RT1308_CLK_FREQ_9600000HZ:
95 value = 0x2;
96 break;
97 case RT1308_CLK_FREQ_4800000HZ:
98 value = 0x3;
99 break;
100 case RT1308_CLK_FREQ_2400000HZ:
101 value = 0x4;
102 break;
103 case RT1308_CLK_FREQ_12288000HZ:
104 value = 0x5;
105 break;
106 default:
107 return -EINVAL;
108 }
109
110 regmap_write(rt1308->regmap, 0xe0, value);
111 regmap_write(rt1308->regmap, 0xf0, value);
112
113 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
114
115 return 0;
116}
117
118static int rt1308_read_prop(struct sdw_slave *slave)
119{
120 struct sdw_slave_prop *prop = &slave->prop;
121 int nval, i;
122 u32 bit;
123 unsigned long addr;
124 struct sdw_dpn_prop *dpn;
125
126 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
127 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
128
129 prop->paging_support = true;
130
131
132 prop->source_ports = 0x00;
133 prop->sink_ports = 0x2;
134
135
136 nval = hweight32(prop->sink_ports);
137 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
138 sizeof(*prop->sink_dpn_prop),
139 GFP_KERNEL);
140 if (!prop->sink_dpn_prop)
141 return -ENOMEM;
142
143 i = 0;
144 dpn = prop->sink_dpn_prop;
145 addr = prop->sink_ports;
146 for_each_set_bit(bit, &addr, 32) {
147 dpn[i].num = bit;
148 dpn[i].type = SDW_DPN_FULL;
149 dpn[i].simple_ch_prep_sm = true;
150 dpn[i].ch_prep_timeout = 10;
151 i++;
152 }
153
154
155 prop->clk_stop_timeout = 20;
156
157 dev_dbg(&slave->dev, "%s\n", __func__);
158
159 return 0;
160}
161
162static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
163{
164 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
165 int ret = 0;
166 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
167 unsigned int efuse_c_btl_l, efuse_c_btl_r;
168
169 if (rt1308->hw_init)
170 return 0;
171
172 if (rt1308->first_hw_init) {
173 regcache_cache_only(rt1308->regmap, false);
174 regcache_cache_bypass(rt1308->regmap, true);
175 }
176
177
178
179
180 if (!rt1308->first_hw_init) {
181
182 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
183 pm_runtime_use_autosuspend(&slave->dev);
184
185
186 pm_runtime_set_active(&slave->dev);
187
188
189 pm_runtime_mark_last_busy(&slave->dev);
190
191 pm_runtime_enable(&slave->dev);
192 }
193
194 pm_runtime_get_noresume(&slave->dev);
195
196
197 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
198
199
200 regmap_write(rt1308->regmap, 0xc360, 0x01);
201 regmap_write(rt1308->regmap, 0xc361, 0x80);
202 regmap_write(rt1308->regmap, 0xc7f0, 0x04);
203 regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
204 msleep(100);
205 regmap_write(rt1308->regmap, 0xc7f0, 0x44);
206 msleep(20);
207 regmap_write(rt1308->regmap, 0xc240, 0x10);
208
209 regmap_read(rt1308->regmap, 0xc861, &tmp);
210 efuse_m_btl_l = tmp;
211 regmap_read(rt1308->regmap, 0xc860, &tmp);
212 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
213 regmap_read(rt1308->regmap, 0xc863, &tmp);
214 efuse_c_btl_l = tmp;
215 regmap_read(rt1308->regmap, 0xc862, &tmp);
216 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
217 regmap_read(rt1308->regmap, 0xc871, &tmp);
218 efuse_m_btl_r = tmp;
219 regmap_read(rt1308->regmap, 0xc870, &tmp);
220 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
221 regmap_read(rt1308->regmap, 0xc873, &tmp);
222 efuse_c_btl_r = tmp;
223 regmap_read(rt1308->regmap, 0xc872, &tmp);
224 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
225 dev_dbg(&slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
226 efuse_m_btl_l, efuse_m_btl_r);
227 dev_dbg(&slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
228 efuse_c_btl_l, efuse_c_btl_r);
229
230
231 regmap_write(rt1308->regmap, 0xc103, 0xc0);
232 regmap_write(rt1308->regmap, 0xc030, 0x17);
233 regmap_write(rt1308->regmap, 0xc031, 0x81);
234 regmap_write(rt1308->regmap, 0xc032, 0x26);
235 regmap_write(rt1308->regmap, 0xc040, 0x80);
236 regmap_write(rt1308->regmap, 0xc041, 0x80);
237 regmap_write(rt1308->regmap, 0xc042, 0x06);
238 regmap_write(rt1308->regmap, 0xc052, 0x0a);
239 regmap_write(rt1308->regmap, 0xc080, 0x0a);
240 regmap_write(rt1308->regmap, 0xc060, 0x02);
241 regmap_write(rt1308->regmap, 0xc061, 0x75);
242 regmap_write(rt1308->regmap, 0xc062, 0x05);
243 regmap_write(rt1308->regmap, 0xc171, 0x07);
244 regmap_write(rt1308->regmap, 0xc173, 0x0d);
245 regmap_write(rt1308->regmap, 0xc311, 0x7f);
246 regmap_write(rt1308->regmap, 0xc900, 0x90);
247 regmap_write(rt1308->regmap, 0xc1a0, 0x84);
248 regmap_write(rt1308->regmap, 0xc1a1, 0x01);
249 regmap_write(rt1308->regmap, 0xc360, 0x78);
250 regmap_write(rt1308->regmap, 0xc361, 0x87);
251 regmap_write(rt1308->regmap, 0xc0a1, 0x71);
252 regmap_write(rt1308->regmap, 0xc210, 0x00);
253 regmap_write(rt1308->regmap, 0xc070, 0x00);
254 regmap_write(rt1308->regmap, 0xc100, 0xd7);
255 regmap_write(rt1308->regmap, 0xc101, 0xd7);
256 regmap_write(rt1308->regmap, 0xc300, 0x09);
257
258 if (rt1308->first_hw_init) {
259 regcache_cache_bypass(rt1308->regmap, false);
260 regcache_mark_dirty(rt1308->regmap);
261 } else
262 rt1308->first_hw_init = true;
263
264
265 rt1308->hw_init = true;
266
267 pm_runtime_mark_last_busy(&slave->dev);
268 pm_runtime_put_autosuspend(&slave->dev);
269
270 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
271
272 return ret;
273}
274
275static int rt1308_update_status(struct sdw_slave *slave,
276 enum sdw_slave_status status)
277{
278 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
279
280
281 rt1308->status = status;
282
283 if (status == SDW_SLAVE_UNATTACHED)
284 rt1308->hw_init = false;
285
286
287
288
289
290 if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED)
291 return 0;
292
293
294 return rt1308_io_init(&slave->dev, slave);
295}
296
297static int rt1308_bus_config(struct sdw_slave *slave,
298 struct sdw_bus_params *params)
299{
300 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
301 int ret;
302
303 memcpy(&rt1308->params, params, sizeof(*params));
304
305 ret = rt1308_clock_config(&slave->dev);
306 if (ret < 0)
307 dev_err(&slave->dev, "Invalid clk config");
308
309 return ret;
310}
311
312static int rt1308_interrupt_callback(struct sdw_slave *slave,
313 struct sdw_slave_intr_status *status)
314{
315 dev_dbg(&slave->dev,
316 "%s control_port_stat=%x", __func__, status->control_port);
317
318 return 0;
319}
320
321static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
322 struct snd_kcontrol *kcontrol, int event)
323{
324 struct snd_soc_component *component =
325 snd_soc_dapm_to_component(w->dapm);
326
327 switch (event) {
328 case SND_SOC_DAPM_POST_PMU:
329 msleep(30);
330 snd_soc_component_update_bits(component,
331 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
332 0x3, 0x3);
333 msleep(40);
334 break;
335 case SND_SOC_DAPM_PRE_PMD:
336 snd_soc_component_update_bits(component,
337 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
338 0x3, 0);
339 usleep_range(150000, 200000);
340 break;
341
342 default:
343 break;
344 }
345
346 return 0;
347}
348
349static const char * const rt1308_rx_data_ch_select[] = {
350 "LR",
351 "LL",
352 "RL",
353 "RR",
354};
355
356static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
357 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
358 rt1308_rx_data_ch_select);
359
360static const struct snd_kcontrol_new rt1308_snd_controls[] = {
361
362
363 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
364};
365
366static const struct snd_kcontrol_new rt1308_sto_dac_l =
367 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
368 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
369 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
370
371static const struct snd_kcontrol_new rt1308_sto_dac_r =
372 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
373 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
374 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
375
376static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
377
378 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
379
380
381 SND_SOC_DAPM_SUPPLY("MBIAS20U",
382 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0),
383 SND_SOC_DAPM_SUPPLY("ALDO",
384 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0),
385 SND_SOC_DAPM_SUPPLY("DBG",
386 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0),
387 SND_SOC_DAPM_SUPPLY("DACL",
388 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0),
389 SND_SOC_DAPM_SUPPLY("CLK25M",
390 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0),
391 SND_SOC_DAPM_SUPPLY("ADC_R",
392 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0),
393 SND_SOC_DAPM_SUPPLY("ADC_L",
394 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0),
395 SND_SOC_DAPM_SUPPLY("DAC Power",
396 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0),
397
398 SND_SOC_DAPM_SUPPLY("DLDO",
399 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0),
400 SND_SOC_DAPM_SUPPLY("VREF",
401 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0),
402 SND_SOC_DAPM_SUPPLY("MIXER_R",
403 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0),
404 SND_SOC_DAPM_SUPPLY("MIXER_L",
405 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0),
406 SND_SOC_DAPM_SUPPLY("MBIAS4U",
407 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0),
408
409 SND_SOC_DAPM_SUPPLY("PLL2_LDO",
410 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
411 SND_SOC_DAPM_SUPPLY("PLL2B",
412 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
413 SND_SOC_DAPM_SUPPLY("PLL2F",
414 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
415 SND_SOC_DAPM_SUPPLY("PLL2F2",
416 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
417 SND_SOC_DAPM_SUPPLY("PLL2B2",
418 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
419
420
421 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
423 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
424
425
426 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
427 rt1308_classd_event,
428 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
429 SND_SOC_DAPM_OUTPUT("SPOL"),
430 SND_SOC_DAPM_OUTPUT("SPOR"),
431};
432
433static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
434
435 { "DAC", NULL, "AIF1RX" },
436
437 { "DAC", NULL, "MBIAS20U" },
438 { "DAC", NULL, "ALDO" },
439 { "DAC", NULL, "DBG" },
440 { "DAC", NULL, "DACL" },
441 { "DAC", NULL, "CLK25M" },
442 { "DAC", NULL, "ADC_R" },
443 { "DAC", NULL, "ADC_L" },
444 { "DAC", NULL, "DLDO" },
445 { "DAC", NULL, "VREF" },
446 { "DAC", NULL, "MIXER_R" },
447 { "DAC", NULL, "MIXER_L" },
448 { "DAC", NULL, "MBIAS4U" },
449 { "DAC", NULL, "PLL2_LDO" },
450 { "DAC", NULL, "PLL2B" },
451 { "DAC", NULL, "PLL2F" },
452 { "DAC", NULL, "PLL2F2" },
453 { "DAC", NULL, "PLL2B2" },
454
455 { "DAC L", "Switch", "DAC" },
456 { "DAC R", "Switch", "DAC" },
457 { "DAC L", NULL, "DAC Power" },
458 { "DAC R", NULL, "DAC Power" },
459
460 { "CLASS D", NULL, "DAC L" },
461 { "CLASS D", NULL, "DAC R" },
462 { "SPOL", NULL, "CLASS D" },
463 { "SPOR", NULL, "CLASS D" },
464};
465
466static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
467 int direction)
468{
469 struct sdw_stream_data *stream;
470
471 if (!sdw_stream)
472 return 0;
473
474 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
475 if (!stream)
476 return -ENOMEM;
477
478 stream->sdw_stream = sdw_stream;
479
480
481 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
482 dai->playback_dma_data = stream;
483 else
484 dai->capture_dma_data = stream;
485
486 return 0;
487}
488
489static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
490 struct snd_soc_dai *dai)
491{
492 struct sdw_stream_data *stream;
493
494 stream = snd_soc_dai_get_dma_data(dai, substream);
495 snd_soc_dai_set_dma_data(dai, substream, NULL);
496 kfree(stream);
497}
498
499static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
500 unsigned int tx_mask,
501 unsigned int rx_mask,
502 int slots, int slot_width)
503{
504 struct snd_soc_component *component = dai->component;
505 struct rt1308_sdw_priv *rt1308 =
506 snd_soc_component_get_drvdata(component);
507
508 if (tx_mask)
509 return -EINVAL;
510
511 if (slots > 2)
512 return -EINVAL;
513
514 rt1308->rx_mask = rx_mask;
515 rt1308->slots = slots;
516
517
518 return 0;
519}
520
521static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
522 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
523{
524 struct snd_soc_component *component = dai->component;
525 struct rt1308_sdw_priv *rt1308 =
526 snd_soc_component_get_drvdata(component);
527 struct sdw_stream_config stream_config;
528 struct sdw_port_config port_config;
529 enum sdw_data_direction direction;
530 struct sdw_stream_data *stream;
531 int retval, port, num_channels, ch_mask;
532
533 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
534 stream = snd_soc_dai_get_dma_data(dai, substream);
535
536 if (!stream)
537 return -EINVAL;
538
539 if (!rt1308->sdw_slave)
540 return -EINVAL;
541
542
543
544 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
545 direction = SDW_DATA_DIR_RX;
546 port = 1;
547 } else {
548 return -EINVAL;
549 }
550
551 if (rt1308->slots) {
552 num_channels = rt1308->slots;
553 ch_mask = rt1308->rx_mask;
554 } else {
555 num_channels = params_channels(params);
556 ch_mask = (1 << num_channels) - 1;
557 }
558
559 stream_config.frame_rate = params_rate(params);
560 stream_config.ch_count = num_channels;
561 stream_config.bps = snd_pcm_format_width(params_format(params));
562 stream_config.direction = direction;
563
564 port_config.ch_mask = ch_mask;
565 port_config.num = port;
566
567 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
568 &port_config, 1, stream->sdw_stream);
569 if (retval) {
570 dev_err(dai->dev, "Unable to configure port\n");
571 return retval;
572 }
573
574 return retval;
575}
576
577static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
578 struct snd_soc_dai *dai)
579{
580 struct snd_soc_component *component = dai->component;
581 struct rt1308_sdw_priv *rt1308 =
582 snd_soc_component_get_drvdata(component);
583 struct sdw_stream_data *stream =
584 snd_soc_dai_get_dma_data(dai, substream);
585
586 if (!rt1308->sdw_slave)
587 return -EINVAL;
588
589 sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream);
590 return 0;
591}
592
593
594
595
596
597static const struct sdw_slave_ops rt1308_slave_ops = {
598 .read_prop = rt1308_read_prop,
599 .interrupt_callback = rt1308_interrupt_callback,
600 .update_status = rt1308_update_status,
601 .bus_config = rt1308_bus_config,
602};
603
604static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
605 .controls = rt1308_snd_controls,
606 .num_controls = ARRAY_SIZE(rt1308_snd_controls),
607 .dapm_widgets = rt1308_dapm_widgets,
608 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
609 .dapm_routes = rt1308_dapm_routes,
610 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
611};
612
613static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
614 .hw_params = rt1308_sdw_hw_params,
615 .hw_free = rt1308_sdw_pcm_hw_free,
616 .set_sdw_stream = rt1308_set_sdw_stream,
617 .shutdown = rt1308_sdw_shutdown,
618 .set_tdm_slot = rt1308_sdw_set_tdm_slot,
619};
620
621#define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
622#define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
623 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
624 SNDRV_PCM_FMTBIT_S24_LE)
625
626static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
627 {
628 .name = "rt1308-aif",
629 .playback = {
630 .stream_name = "DP1 Playback",
631 .channels_min = 1,
632 .channels_max = 2,
633 .rates = RT1308_STEREO_RATES,
634 .formats = RT1308_FORMATS,
635 },
636 .ops = &rt1308_aif_dai_ops,
637 },
638};
639
640static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
641 struct sdw_slave *slave)
642{
643 struct rt1308_sdw_priv *rt1308;
644 int ret;
645
646 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
647 if (!rt1308)
648 return -ENOMEM;
649
650 dev_set_drvdata(dev, rt1308);
651 rt1308->sdw_slave = slave;
652 rt1308->regmap = regmap;
653
654
655
656
657
658 rt1308->hw_init = false;
659 rt1308->first_hw_init = false;
660
661 ret = devm_snd_soc_register_component(dev,
662 &soc_component_sdw_rt1308,
663 rt1308_sdw_dai,
664 ARRAY_SIZE(rt1308_sdw_dai));
665
666 dev_dbg(&slave->dev, "%s\n", __func__);
667
668 return ret;
669}
670
671static int rt1308_sdw_probe(struct sdw_slave *slave,
672 const struct sdw_device_id *id)
673{
674 struct regmap *regmap;
675
676
677 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
678 if (IS_ERR(regmap))
679 return PTR_ERR(regmap);
680
681 rt1308_sdw_init(&slave->dev, regmap, slave);
682
683 return 0;
684}
685
686static const struct sdw_device_id rt1308_id[] = {
687 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
688 {},
689};
690MODULE_DEVICE_TABLE(sdw, rt1308_id);
691
692static int __maybe_unused rt1308_dev_suspend(struct device *dev)
693{
694 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
695
696 if (!rt1308->hw_init)
697 return 0;
698
699 regcache_cache_only(rt1308->regmap, true);
700
701 return 0;
702}
703
704#define RT1308_PROBE_TIMEOUT 5000
705
706static int __maybe_unused rt1308_dev_resume(struct device *dev)
707{
708 struct sdw_slave *slave = dev_to_sdw_dev(dev);
709 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
710 unsigned long time;
711
712 if (!rt1308->first_hw_init)
713 return 0;
714
715 if (!slave->unattach_request)
716 goto regmap_sync;
717
718 time = wait_for_completion_timeout(&slave->initialization_complete,
719 msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
720 if (!time) {
721 dev_err(&slave->dev, "Initialization not complete, timed out\n");
722 return -ETIMEDOUT;
723 }
724
725regmap_sync:
726 slave->unattach_request = 0;
727 regcache_cache_only(rt1308->regmap, false);
728 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
729
730 return 0;
731}
732
733static const struct dev_pm_ops rt1308_pm = {
734 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
735 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
736};
737
738static struct sdw_driver rt1308_sdw_driver = {
739 .driver = {
740 .name = "rt1308",
741 .owner = THIS_MODULE,
742 .pm = &rt1308_pm,
743 },
744 .probe = rt1308_sdw_probe,
745 .ops = &rt1308_slave_ops,
746 .id_table = rt1308_id,
747};
748module_sdw_driver(rt1308_sdw_driver);
749
750MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
751MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
752MODULE_LICENSE("GPL v2");
753
