1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * rt1308.h -- RT1308 ALSA SoC amplifier component driver 4 * 5 * Copyright 2019 Realtek Semiconductor Corp. 6 * Author: Derek Fang <derek.fang@realtek.com> 7 * 8 */ 9 10#ifndef _RT1308_H_ 11#define _RT1308_H_ 12 13#define RT1308_DEVICE_ID_NUM 0x10ec1300 14 15#define RT1308_RESET 0x00 16#define RT1308_RESET_N 0x01 17#define RT1308_CLK_GATING 0x02 18#define RT1308_PLL_1 0x03 19#define RT1308_PLL_2 0x04 20#define RT1308_PLL_INT 0x05 21#define RT1308_CLK_1 0x06 22#define RT1308_DATA_PATH 0x07 23#define RT1308_CLK_2 0x08 24#define RT1308_SIL_DET 0x09 25#define RT1308_CLK_DET 0x0a 26#define RT1308_DC_DET 0x0b 27#define RT1308_DC_DET_THRES 0x0c 28#define RT1308_DAC_SET 0x10 29#define RT1308_SRC_SET 0x11 30#define RT1308_DAC_BUF 0x12 31#define RT1308_ADC_SET 0x13 32#define RT1308_ADC_SET_INT 0x14 33#define RT1308_I2S_SET_1 0x15 34#define RT1308_I2S_SET_2 0x16 35#define RT1308_I2C_I2S_SDW_SET 0x17 36#define RT1308_SDW_REG_RW 0x18 37#define RT1308_SDW_REG_RDATA 0x19 38#define RT1308_IV_SENSE 0x1a 39#define RT1308_I2S_TX_DAC_SET 0x1b 40#define RT1308_AD_FILTER_SET 0x1c 41#define RT1308_DC_CAL_1 0x20 42#define RT1308_DC_CAL_2 0x21 43#define RT1308_DC_CAL_L_OFFSET 0x22 44#define RT1308_DC_CAL_R_OFFSET 0x23 45#define RT1308_PVDD_OFFSET_CTL 0x24 46#define RT1308_PVDD_OFFSET_L 0x25 47#define RT1308_PVDD_OFFSET_R 0x26 48#define RT1308_PVDD_OFFSET_PBTL 0x27 49#define RT1308_PVDD_OFFSET_PVDD 0x28 50#define RT1308_CAL_OFFSET_DAC_PBTL 0x29 51#define RT1308_CAL_OFFSET_DAC_L 0x2a 52#define RT1308_CAL_OFFSET_DAC_R 0x2b 53#define RT1308_CAL_OFFSET_PWM_L 0x2c 54#define RT1308_CAL_OFFSET_PWM_R 0x2d 55#define RT1308_CAL_PWM_VOS_ADC_L 0x2e 56#define RT1308_CAL_PWM_VOS_ADC_R 0x2f 57#define RT1308_CLASS_D_SET_1 0x30 58#define RT1308_CLASS_D_SET_2 0x31 59#define RT1308_POWER 0x32 60#define RT1308_LDO 0x33 61#define RT1308_VREF 0x34 62#define RT1308_MBIAS 0x35 63#define RT1308_POWER_STATUS 0x36 64#define RT1308_POWER_INT 0x37 65#define RT1308_SINE_TONE_GEN_1 0x50 66#define RT1308_SINE_TONE_GEN_2 0x51 67#define RT1308_BQ_SET 0x54 68#define RT1308_BQ_PARA_UPDATE 0x55 69#define RT1308_BQ_PRE_VOL_L 0x56 70#define RT1308_BQ_PRE_VOL_R 0x57 71#define RT1308_BQ_POST_VOL_L 0x58 72#define RT1308_BQ_POST_VOL_R 0x59 73#define RT1308_BQ1_L_H0 0x5b 74#define RT1308_BQ1_L_B1 0x5c 75#define RT1308_BQ1_L_B2 0x5d 76#define RT1308_BQ1_L_A1 0x5e 77#define RT1308_BQ1_L_A2 0x5f 78#define RT1308_BQ1_R_H0 0x60 79#define RT1308_BQ1_R_B1 0x61 80#define RT1308_BQ1_R_B2 0x62 81#define RT1308_BQ1_R_A1 0x63 82#define RT1308_BQ1_R_A2 0x64 83#define RT1308_BQ2_L_H0 0x65 84#define RT1308_BQ2_L_B1 0x66 85#define RT1308_BQ2_L_B2 0x67 86#define RT1308_BQ2_L_A1 0x68 87#define RT1308_BQ2_L_A2 0x69 88#define RT1308_BQ2_R_H0 0x6a 89#define RT1308_BQ2_R_B1 0x6b 90#define RT1308_BQ2_R_B2 0x6c 91#define RT1308_BQ2_R_A1 0x6d 92#define RT1308_BQ2_R_A2 0x6e 93#define RT1308_VEN_DEV_ID 0x70 94#define RT1308_VERSION_ID 0x71 95#define RT1308_SPK_BOUND 0x72 96#define RT1308_BQ1_EQ_L_1 0x73 97#define RT1308_BQ1_EQ_L_2 0x74 98#define RT1308_BQ1_EQ_L_3 0x75 99#define RT1308_BQ1_EQ_R_1 0x76 100#define RT1308_BQ1_EQ_R_2 0x77 101#define RT1308_BQ1_EQ_R_3 0x78 102#define RT1308_BQ2_EQ_L_1 0x79 103#define RT1308_BQ2_EQ_L_2 0x7a 104#define RT1308_BQ2_EQ_L_3 0x7b 105#define RT1308_BQ2_EQ_R_1 0x7c 106#define RT1308_BQ2_EQ_R_2 0x7d 107#define RT1308_BQ2_EQ_R_3 0x7e 108#define RT1308_EFUSE_1 0x7f 109#define RT1308_EFUSE_2 0x80 110#define RT1308_EFUSE_PROG_PVDD_L 0x81 111#define RT1308_EFUSE_PROG_PVDD_R 0x82 112#define RT1308_EFUSE_PROG_R0_L 0x83 113#define RT1308_EFUSE_PROG_R0_R 0x84 114#define RT1308_EFUSE_PROG_DEV 0x85 115#define RT1308_EFUSE_READ_PVDD_L 0x86 116#define RT1308_EFUSE_READ_PVDD_R 0x87 117#define RT1308_EFUSE_READ_PVDD_PTBL 0x88 118#define RT1308_EFUSE_READ_DEV 0x89 119#define RT1308_EFUSE_READ_R0 0x8a 120#define RT1308_EFUSE_READ_ADC_L 0x8b 121#define RT1308_EFUSE_READ_ADC_R 0x8c 122#define RT1308_EFUSE_READ_ADC_PBTL 0x8d 123#define RT1308_EFUSE_RESERVE 0x8e 124#define RT1308_PADS_1 0x90 125#define RT1308_PADS_2 0x91 126#define RT1308_TEST_MODE 0xa0 127#define RT1308_TEST_1 0xa1 128#define RT1308_TEST_2 0xa2 129#define RT1308_TEST_3 0xa3 130#define RT1308_TEST_4 0xa4 131#define RT1308_EFUSE_DATA_0_MSB 0xb0 132#define RT1308_EFUSE_DATA_0_LSB 0xb1 133#define RT1308_EFUSE_DATA_1_MSB 0xb2 134#define RT1308_EFUSE_DATA_1_LSB 0xb3 135#define RT1308_EFUSE_DATA_2_MSB 0xb4 136#define RT1308_EFUSE_DATA_2_LSB 0xb5 137#define RT1308_EFUSE_DATA_3_MSB 0xb6 138#define RT1308_EFUSE_DATA_3_LSB 0xb7 139#define RT1308_EFUSE_DATA_TEST_MSB 0xb8 140#define RT1308_EFUSE_DATA_TEST_LSB 0xb9 141#define RT1308_EFUSE_STATUS_1 0xba 142#define RT1308_EFUSE_STATUS_2 0xbb 143#define RT1308_TCON_1 0xc0 144#define RT1308_TCON_2 0xc1 145#define RT1308_DUMMY_REG 0xf0 146#define RT1308_MAX_REG 0xff 147 148/* PLL1 M/N/K Code-1 (0x03) */ 149#define RT1308_PLL1_K_SFT 24 150#define RT1308_PLL1_K_MASK (0x1f << 24) 151#define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23) 152#define RT1308_PLL1_M_BYPASS_SFT 23 153#define RT1308_PLL1_M_BYPASS (0x1 << 23) 154#define RT1308_PLL1_M_MASK (0x3f << 16) 155#define RT1308_PLL1_M_SFT 16 156#define RT1308_PLL1_N_MASK (0x7f << 8) 157#define RT1308_PLL1_N_SFT 8 158 159/* CLOCK-1 (0x06) */ 160#define RT1308_DIV_FS_SYS_MASK (0xf << 28) 161#define RT1308_DIV_FS_SYS_SFT 28 162#define RT1308_SEL_FS_SYS_MASK (0x7 << 24) 163#define RT1308_SEL_FS_SYS_SFT 24 164#define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24) 165#define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24) 166#define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24) 167#define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24) 168 169/* CLOCK-2 (0x08) */ 170#define RT1308_DIV_PRE_PLL_MASK (0xf << 28) 171#define RT1308_DIV_PRE_PLL_SFT 28 172#define RT1308_SEL_PLL_SRC_MASK (0x7 << 24) 173#define RT1308_SEL_PLL_SRC_SFT 24 174#define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24) 175#define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24) 176#define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24) 177 178/* Clock Detect (0x0a) */ 179#define RT1308_MCLK_DET_EN_MASK (0x1 << 25) 180#define RT1308_MCLK_DET_EN_SFT 25 181#define RT1308_MCLK_DET_EN (0x1 << 25) 182#define RT1308_BCLK_DET_EN_MASK (0x1 << 24) 183#define RT1308_BCLK_DET_EN_SFT 24 184#define RT1308_BCLK_DET_EN (0x1 << 24) 185 186/* DAC Setting (0x10) */ 187#define RT1308_DVOL_MUTE_R_EN_SFT 7 188#define RT1308_DVOL_MUTE_L_EN_SFT 6 189 190/* I2S Setting-1 (0x15) */ 191#define RT1308_I2S_DF_SEL_MASK (0x3 << 12) 192#define RT1308_I2S_DF_SEL_SFT 12 193#define RT1308_I2S_DF_SEL_I2S (0x0 << 12) 194#define RT1308_I2S_DF_SEL_LEFT (0x1 << 12) 195#define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12) 196#define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12) 197#define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4) 198#define RT1308_I2S_DL_RX_SEL_SFT 4 199#define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4) 200#define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4) 201#define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4) 202#define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4) 203#define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4) 204#define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0) 205#define RT1308_I2S_DL_TX_SEL_SFT 0 206#define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0) 207#define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0) 208#define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0) 209#define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0) 210#define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0) 211 212/* I2S Setting-2 (0x16) */ 213#define RT1308_I2S_DL_SEL_MASK (0x7 << 24) 214#define RT1308_I2S_DL_SEL_SFT 24 215#define RT1308_I2S_DL_SEL_16B (0x0 << 24) 216#define RT1308_I2S_DL_SEL_20B (0x1 << 24) 217#define RT1308_I2S_DL_SEL_24B (0x2 << 24) 218#define RT1308_I2S_DL_SEL_32B (0x3 << 24) 219#define RT1308_I2S_DL_SEL_8B (0x4 << 24) 220#define RT1308_I2S_BCLK_MASK (0x1 << 14) 221#define RT1308_I2S_BCLK_SFT 14 222#define RT1308_I2S_BCLK_NORMAL (0x0 << 14) 223#define RT1308_I2S_BCLK_INV (0x1 << 14) 224 225/* Power Control-1 (0x32) */ 226#define RT1308_POW_MBIAS20U (0x1 << 31) 227#define RT1308_POW_MBIAS20U_BIT 31 228#define RT1308_POW_ALDO (0x1 << 30) 229#define RT1308_POW_ALDO_BIT 30 230#define RT1308_POW_DBG (0x1 << 29) 231#define RT1308_POW_DBG_BIT 29 232#define RT1308_POW_DACL (0x1 << 28) 233#define RT1308_POW_DACL_BIT 28 234#define RT1308_POW_DAC1 (0x1 << 27) 235#define RT1308_POW_DAC1_BIT 27 236#define RT1308_POW_CLK25M (0x1 << 26) 237#define RT1308_POW_CLK25M_BIT 26 238#define RT1308_POW_ADC_R (0x1 << 25) 239#define RT1308_POW_ADC_R_BIT 25 240#define RT1308_POW_ADC_L (0x1 << 24) 241#define RT1308_POW_ADC_L_BIT 24 242#define RT1308_POW_DLDO (0x1 << 21) 243#define RT1308_POW_DLDO_BIT 21 244#define RT1308_POW_VREF (0x1 << 20) 245#define RT1308_POW_VREF_BIT 20 246#define RT1308_POW_MIXER_R (0x1 << 18) 247#define RT1308_POW_MIXER_R_BIT 18 248#define RT1308_POW_MIXER_L (0x1 << 17) 249#define RT1308_POW_MIXER_L_BIT 17 250#define RT1308_POW_MBIAS4U (0x1 << 16) 251#define RT1308_POW_MBIAS4U_BIT 16 252#define RT1308_POW_PLL2_LDO_EN (0x1 << 12) 253#define RT1308_POW_PLL2_LDO_EN_BIT 12 254#define RT1308_POW_PLL2B_EN (0x1 << 11) 255#define RT1308_POW_PLL2B_EN_BIT 11 256#define RT1308_POW_PLL2F_EN (0x1 << 10) 257#define RT1308_POW_PLL2F_EN_BIT 10 258#define RT1308_POW_PLL2F2_EN (0x1 << 9) 259#define RT1308_POW_PLL2F2_EN_BIT 9 260#define RT1308_POW_PLL2B2_EN (0x1 << 8) 261#define RT1308_POW_PLL2B2_EN_BIT 8 262 263/* Power Control-2 (0x36) */ 264#define RT1308_POW_PDB_SRC_BIT (0x1 << 27) 265#define RT1308_POW_PDB_MN_BIT (0x1 << 25) 266#define RT1308_POW_PDB_REG_BIT (0x1 << 24) 267 268 269/* System Clock Source */ 270enum { 271 RT1308_FS_SYS_S_MCLK, 272 RT1308_FS_SYS_S_BCLK, 273 RT1308_FS_SYS_S_PLL, 274 RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */ 275}; 276 277/* PLL Source */ 278enum { 279 RT1308_PLL_S_MCLK, 280 RT1308_PLL_S_BCLK, 281 RT1308_PLL_S_RCCLK, 282}; 283 284enum { 285 RT1308_AIF1, 286 RT1308_AIFS 287}; 288 289#endif /* end of _RT1308_H_ */ 290