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9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/pm_runtime.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/acpi.h>
18#include <linux/gpio.h>
19#include <linux/of_gpio.h>
20#include <linux/mutex.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/rt5682.h>
30
31#include "rl6231.h"
32#include "rt5682.h"
33
34const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38};
39EXPORT_SYMBOL_GPL(rt5682_supply_names);
40
41static const struct reg_sequence patch_list[] = {
42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44 {RT5682_I2C_CTRL, 0x000f},
45 {RT5682_PLL2_INTERNAL, 0x8266},
46 {RT5682_SAR_IL_CMD_1, 0x22b7},
47 {RT5682_SAR_IL_CMD_3, 0x0365},
48 {RT5682_SAR_IL_CMD_6, 0x0110},
49};
50
51void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
52{
53 int ret;
54
55 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
56 ARRAY_SIZE(patch_list));
57 if (ret)
58 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
59}
60EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
61
62const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
63 {0x0002, 0x8080},
64 {0x0003, 0x8000},
65 {0x0005, 0x0000},
66 {0x0006, 0x0000},
67 {0x0008, 0x800f},
68 {0x000b, 0x0000},
69 {0x0010, 0x4040},
70 {0x0011, 0x0000},
71 {0x0012, 0x1404},
72 {0x0013, 0x1000},
73 {0x0014, 0xa00a},
74 {0x0015, 0x0404},
75 {0x0016, 0x0404},
76 {0x0019, 0xafaf},
77 {0x001c, 0x2f2f},
78 {0x001f, 0x0000},
79 {0x0022, 0x5757},
80 {0x0023, 0x0039},
81 {0x0024, 0x000b},
82 {0x0026, 0xc0c4},
83 {0x0029, 0x8080},
84 {0x002a, 0xa0a0},
85 {0x002b, 0x0300},
86 {0x0030, 0x0000},
87 {0x003c, 0x0080},
88 {0x0044, 0x0c0c},
89 {0x0049, 0x0000},
90 {0x0061, 0x0000},
91 {0x0062, 0x0000},
92 {0x0063, 0x003f},
93 {0x0064, 0x0000},
94 {0x0065, 0x0000},
95 {0x0066, 0x0030},
96 {0x0067, 0x0000},
97 {0x006b, 0x0000},
98 {0x006c, 0x0000},
99 {0x006d, 0x2200},
100 {0x006e, 0x0a10},
101 {0x0070, 0x8000},
102 {0x0071, 0x8000},
103 {0x0073, 0x0000},
104 {0x0074, 0x0000},
105 {0x0075, 0x0002},
106 {0x0076, 0x0001},
107 {0x0079, 0x0000},
108 {0x007a, 0x0000},
109 {0x007b, 0x0000},
110 {0x007c, 0x0100},
111 {0x007e, 0x0000},
112 {0x0080, 0x0000},
113 {0x0081, 0x0000},
114 {0x0082, 0x0000},
115 {0x0083, 0x0000},
116 {0x0084, 0x0000},
117 {0x0085, 0x0000},
118 {0x0086, 0x0005},
119 {0x0087, 0x0000},
120 {0x0088, 0x0000},
121 {0x008c, 0x0003},
122 {0x008d, 0x0000},
123 {0x008e, 0x0060},
124 {0x008f, 0x1000},
125 {0x0091, 0x0c26},
126 {0x0092, 0x0073},
127 {0x0093, 0x0000},
128 {0x0094, 0x0080},
129 {0x0098, 0x0000},
130 {0x009a, 0x0000},
131 {0x009b, 0x0000},
132 {0x009c, 0x0000},
133 {0x009d, 0x0000},
134 {0x009e, 0x100c},
135 {0x009f, 0x0000},
136 {0x00a0, 0x0000},
137 {0x00a3, 0x0002},
138 {0x00a4, 0x0001},
139 {0x00ae, 0x2040},
140 {0x00af, 0x0000},
141 {0x00b6, 0x0000},
142 {0x00b7, 0x0000},
143 {0x00b8, 0x0000},
144 {0x00b9, 0x0002},
145 {0x00be, 0x0000},
146 {0x00c0, 0x0160},
147 {0x00c1, 0x82a0},
148 {0x00c2, 0x0000},
149 {0x00d0, 0x0000},
150 {0x00d1, 0x2244},
151 {0x00d2, 0x3300},
152 {0x00d3, 0x2200},
153 {0x00d4, 0x0000},
154 {0x00d9, 0x0009},
155 {0x00da, 0x0000},
156 {0x00db, 0x0000},
157 {0x00dc, 0x00c0},
158 {0x00dd, 0x2220},
159 {0x00de, 0x3131},
160 {0x00df, 0x3131},
161 {0x00e0, 0x3131},
162 {0x00e2, 0x0000},
163 {0x00e3, 0x4000},
164 {0x00e4, 0x0aa0},
165 {0x00e5, 0x3131},
166 {0x00e6, 0x3131},
167 {0x00e7, 0x3131},
168 {0x00e8, 0x3131},
169 {0x00ea, 0xb320},
170 {0x00eb, 0x0000},
171 {0x00f0, 0x0000},
172 {0x00f1, 0x00d0},
173 {0x00f2, 0x00d0},
174 {0x00f6, 0x0000},
175 {0x00fa, 0x0000},
176 {0x00fb, 0x0000},
177 {0x00fc, 0x0000},
178 {0x00fd, 0x0000},
179 {0x00fe, 0x10ec},
180 {0x00ff, 0x6530},
181 {0x0100, 0xa0a0},
182 {0x010b, 0x0000},
183 {0x010c, 0xae00},
184 {0x010d, 0xaaa0},
185 {0x010e, 0x8aa2},
186 {0x010f, 0x02a2},
187 {0x0110, 0xc000},
188 {0x0111, 0x04a2},
189 {0x0112, 0x2800},
190 {0x0113, 0x0000},
191 {0x0117, 0x0100},
192 {0x0125, 0x0410},
193 {0x0132, 0x6026},
194 {0x0136, 0x5555},
195 {0x0138, 0x3700},
196 {0x013a, 0x2000},
197 {0x013b, 0x2000},
198 {0x013c, 0x2005},
199 {0x013f, 0x0000},
200 {0x0142, 0x0000},
201 {0x0145, 0x0002},
202 {0x0146, 0x0000},
203 {0x0147, 0x0000},
204 {0x0148, 0x0000},
205 {0x0149, 0x0000},
206 {0x0150, 0x79a1},
207 {0x0156, 0xaaaa},
208 {0x0160, 0x4ec0},
209 {0x0161, 0x0080},
210 {0x0162, 0x0200},
211 {0x0163, 0x0800},
212 {0x0164, 0x0000},
213 {0x0165, 0x0000},
214 {0x0166, 0x0000},
215 {0x0167, 0x000f},
216 {0x0168, 0x000f},
217 {0x0169, 0x0021},
218 {0x0190, 0x413d},
219 {0x0194, 0x0000},
220 {0x0195, 0x0000},
221 {0x0197, 0x0022},
222 {0x0198, 0x0000},
223 {0x0199, 0x0000},
224 {0x01af, 0x0000},
225 {0x01b0, 0x0400},
226 {0x01b1, 0x0000},
227 {0x01b2, 0x0000},
228 {0x01b3, 0x0000},
229 {0x01b4, 0x0000},
230 {0x01b5, 0x0000},
231 {0x01b6, 0x01c3},
232 {0x01b7, 0x02a0},
233 {0x01b8, 0x03e9},
234 {0x01b9, 0x1389},
235 {0x01ba, 0xc351},
236 {0x01bb, 0x0009},
237 {0x01bc, 0x0018},
238 {0x01bd, 0x002a},
239 {0x01be, 0x004c},
240 {0x01bf, 0x0097},
241 {0x01c0, 0x433d},
242 {0x01c2, 0x0000},
243 {0x01c3, 0x0000},
244 {0x01c4, 0x0000},
245 {0x01c5, 0x0000},
246 {0x01c6, 0x0000},
247 {0x01c7, 0x0000},
248 {0x01c8, 0x40af},
249 {0x01c9, 0x0702},
250 {0x01ca, 0x0000},
251 {0x01cb, 0x0000},
252 {0x01cc, 0x5757},
253 {0x01cd, 0x5757},
254 {0x01ce, 0x5757},
255 {0x01cf, 0x5757},
256 {0x01d0, 0x5757},
257 {0x01d1, 0x5757},
258 {0x01d2, 0x5757},
259 {0x01d3, 0x5757},
260 {0x01d4, 0x5757},
261 {0x01d5, 0x5757},
262 {0x01d6, 0x0000},
263 {0x01d7, 0x0008},
264 {0x01d8, 0x0029},
265 {0x01d9, 0x3333},
266 {0x01da, 0x0000},
267 {0x01db, 0x0004},
268 {0x01dc, 0x0000},
269 {0x01de, 0x7c00},
270 {0x01df, 0x0320},
271 {0x01e0, 0x06a1},
272 {0x01e1, 0x0000},
273 {0x01e2, 0x0000},
274 {0x01e3, 0x0000},
275 {0x01e4, 0x0000},
276 {0x01e6, 0x0001},
277 {0x01e7, 0x0000},
278 {0x01e8, 0x0000},
279 {0x01ea, 0x0000},
280 {0x01eb, 0x0000},
281 {0x01ec, 0x0000},
282 {0x01ed, 0x0000},
283 {0x01ee, 0x0000},
284 {0x01ef, 0x0000},
285 {0x01f0, 0x0000},
286 {0x01f1, 0x0000},
287 {0x01f2, 0x0000},
288 {0x01f3, 0x0000},
289 {0x01f4, 0x0000},
290 {0x0210, 0x6297},
291 {0x0211, 0xa005},
292 {0x0212, 0x824c},
293 {0x0213, 0xf7ff},
294 {0x0214, 0xf24c},
295 {0x0215, 0x0102},
296 {0x0216, 0x00a3},
297 {0x0217, 0x0048},
298 {0x0218, 0xa2c0},
299 {0x0219, 0x0400},
300 {0x021a, 0x00c8},
301 {0x021b, 0x00c0},
302 {0x021c, 0x0000},
303 {0x0250, 0x4500},
304 {0x0251, 0x40b3},
305 {0x0252, 0x0000},
306 {0x0253, 0x0000},
307 {0x0254, 0x0000},
308 {0x0255, 0x0000},
309 {0x0256, 0x0000},
310 {0x0257, 0x0000},
311 {0x0258, 0x0000},
312 {0x0259, 0x0000},
313 {0x025a, 0x0005},
314 {0x0270, 0x0000},
315 {0x02ff, 0x0110},
316 {0x0300, 0x001f},
317 {0x0301, 0x032c},
318 {0x0302, 0x5f21},
319 {0x0303, 0x4000},
320 {0x0304, 0x4000},
321 {0x0305, 0x06d5},
322 {0x0306, 0x8000},
323 {0x0307, 0x0700},
324 {0x0310, 0x4560},
325 {0x0311, 0xa4a8},
326 {0x0312, 0x7418},
327 {0x0313, 0x0000},
328 {0x0314, 0x0006},
329 {0x0315, 0xffff},
330 {0x0316, 0xc400},
331 {0x0317, 0x0000},
332 {0x03c0, 0x7e00},
333 {0x03c1, 0x8000},
334 {0x03c2, 0x8000},
335 {0x03c3, 0x8000},
336 {0x03c4, 0x8000},
337 {0x03c5, 0x8000},
338 {0x03c6, 0x8000},
339 {0x03c7, 0x8000},
340 {0x03c8, 0x8000},
341 {0x03c9, 0x8000},
342 {0x03ca, 0x8000},
343 {0x03cb, 0x8000},
344 {0x03cc, 0x8000},
345 {0x03d0, 0x0000},
346 {0x03d1, 0x0000},
347 {0x03d2, 0x0000},
348 {0x03d3, 0x0000},
349 {0x03d4, 0x2000},
350 {0x03d5, 0x2000},
351 {0x03d6, 0x0000},
352 {0x03d7, 0x0000},
353 {0x03d8, 0x2000},
354 {0x03d9, 0x2000},
355 {0x03da, 0x2000},
356 {0x03db, 0x2000},
357 {0x03dc, 0x0000},
358 {0x03dd, 0x0000},
359 {0x03de, 0x0000},
360 {0x03df, 0x2000},
361 {0x03e0, 0x0000},
362 {0x03e1, 0x0000},
363 {0x03e2, 0x0000},
364 {0x03e3, 0x0000},
365 {0x03e4, 0x0000},
366 {0x03e5, 0x0000},
367 {0x03e6, 0x0000},
368 {0x03e7, 0x0000},
369 {0x03e8, 0x0000},
370 {0x03e9, 0x0000},
371 {0x03ea, 0x0000},
372 {0x03eb, 0x0000},
373 {0x03ec, 0x0000},
374 {0x03ed, 0x0000},
375 {0x03ee, 0x0000},
376 {0x03ef, 0x0000},
377 {0x03f0, 0x0800},
378 {0x03f1, 0x0800},
379 {0x03f2, 0x0800},
380 {0x03f3, 0x0800},
381};
382EXPORT_SYMBOL_GPL(rt5682_reg);
383
384bool rt5682_volatile_register(struct device *dev, unsigned int reg)
385{
386 switch (reg) {
387 case RT5682_RESET:
388 case RT5682_CBJ_CTRL_2:
389 case RT5682_INT_ST_1:
390 case RT5682_4BTN_IL_CMD_1:
391 case RT5682_AJD1_CTRL:
392 case RT5682_HP_CALIB_CTRL_1:
393 case RT5682_DEVICE_ID:
394 case RT5682_I2C_MODE:
395 case RT5682_HP_CALIB_CTRL_10:
396 case RT5682_EFUSE_CTRL_2:
397 case RT5682_JD_TOP_VC_VTRL:
398 case RT5682_HP_IMP_SENS_CTRL_19:
399 case RT5682_IL_CMD_1:
400 case RT5682_SAR_IL_CMD_2:
401 case RT5682_SAR_IL_CMD_4:
402 case RT5682_SAR_IL_CMD_10:
403 case RT5682_SAR_IL_CMD_11:
404 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
405 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
406 return true;
407 default:
408 return false;
409 }
410}
411EXPORT_SYMBOL_GPL(rt5682_volatile_register);
412
413bool rt5682_readable_register(struct device *dev, unsigned int reg)
414{
415 switch (reg) {
416 case RT5682_RESET:
417 case RT5682_VERSION_ID:
418 case RT5682_VENDOR_ID:
419 case RT5682_DEVICE_ID:
420 case RT5682_HP_CTRL_1:
421 case RT5682_HP_CTRL_2:
422 case RT5682_HPL_GAIN:
423 case RT5682_HPR_GAIN:
424 case RT5682_I2C_CTRL:
425 case RT5682_CBJ_BST_CTRL:
426 case RT5682_CBJ_CTRL_1:
427 case RT5682_CBJ_CTRL_2:
428 case RT5682_CBJ_CTRL_3:
429 case RT5682_CBJ_CTRL_4:
430 case RT5682_CBJ_CTRL_5:
431 case RT5682_CBJ_CTRL_6:
432 case RT5682_CBJ_CTRL_7:
433 case RT5682_DAC1_DIG_VOL:
434 case RT5682_STO1_ADC_DIG_VOL:
435 case RT5682_STO1_ADC_BOOST:
436 case RT5682_HP_IMP_GAIN_1:
437 case RT5682_HP_IMP_GAIN_2:
438 case RT5682_SIDETONE_CTRL:
439 case RT5682_STO1_ADC_MIXER:
440 case RT5682_AD_DA_MIXER:
441 case RT5682_STO1_DAC_MIXER:
442 case RT5682_A_DAC1_MUX:
443 case RT5682_DIG_INF2_DATA:
444 case RT5682_REC_MIXER:
445 case RT5682_CAL_REC:
446 case RT5682_ALC_BACK_GAIN:
447 case RT5682_PWR_DIG_1:
448 case RT5682_PWR_DIG_2:
449 case RT5682_PWR_ANLG_1:
450 case RT5682_PWR_ANLG_2:
451 case RT5682_PWR_ANLG_3:
452 case RT5682_PWR_MIXER:
453 case RT5682_PWR_VOL:
454 case RT5682_CLK_DET:
455 case RT5682_RESET_LPF_CTRL:
456 case RT5682_RESET_HPF_CTRL:
457 case RT5682_DMIC_CTRL_1:
458 case RT5682_I2S1_SDP:
459 case RT5682_I2S2_SDP:
460 case RT5682_ADDA_CLK_1:
461 case RT5682_ADDA_CLK_2:
462 case RT5682_I2S1_F_DIV_CTRL_1:
463 case RT5682_I2S1_F_DIV_CTRL_2:
464 case RT5682_TDM_CTRL:
465 case RT5682_TDM_ADDA_CTRL_1:
466 case RT5682_TDM_ADDA_CTRL_2:
467 case RT5682_DATA_SEL_CTRL_1:
468 case RT5682_TDM_TCON_CTRL:
469 case RT5682_GLB_CLK:
470 case RT5682_PLL_CTRL_1:
471 case RT5682_PLL_CTRL_2:
472 case RT5682_PLL_TRACK_1:
473 case RT5682_PLL_TRACK_2:
474 case RT5682_PLL_TRACK_3:
475 case RT5682_PLL_TRACK_4:
476 case RT5682_PLL_TRACK_5:
477 case RT5682_PLL_TRACK_6:
478 case RT5682_PLL_TRACK_11:
479 case RT5682_SDW_REF_CLK:
480 case RT5682_DEPOP_1:
481 case RT5682_DEPOP_2:
482 case RT5682_HP_CHARGE_PUMP_1:
483 case RT5682_HP_CHARGE_PUMP_2:
484 case RT5682_MICBIAS_1:
485 case RT5682_MICBIAS_2:
486 case RT5682_PLL_TRACK_12:
487 case RT5682_PLL_TRACK_14:
488 case RT5682_PLL2_CTRL_1:
489 case RT5682_PLL2_CTRL_2:
490 case RT5682_PLL2_CTRL_3:
491 case RT5682_PLL2_CTRL_4:
492 case RT5682_RC_CLK_CTRL:
493 case RT5682_I2S_M_CLK_CTRL_1:
494 case RT5682_I2S2_F_DIV_CTRL_1:
495 case RT5682_I2S2_F_DIV_CTRL_2:
496 case RT5682_EQ_CTRL_1:
497 case RT5682_EQ_CTRL_2:
498 case RT5682_IRQ_CTRL_1:
499 case RT5682_IRQ_CTRL_2:
500 case RT5682_IRQ_CTRL_3:
501 case RT5682_IRQ_CTRL_4:
502 case RT5682_INT_ST_1:
503 case RT5682_GPIO_CTRL_1:
504 case RT5682_GPIO_CTRL_2:
505 case RT5682_GPIO_CTRL_3:
506 case RT5682_HP_AMP_DET_CTRL_1:
507 case RT5682_HP_AMP_DET_CTRL_2:
508 case RT5682_MID_HP_AMP_DET:
509 case RT5682_LOW_HP_AMP_DET:
510 case RT5682_DELAY_BUF_CTRL:
511 case RT5682_SV_ZCD_1:
512 case RT5682_SV_ZCD_2:
513 case RT5682_IL_CMD_1:
514 case RT5682_IL_CMD_2:
515 case RT5682_IL_CMD_3:
516 case RT5682_IL_CMD_4:
517 case RT5682_IL_CMD_5:
518 case RT5682_IL_CMD_6:
519 case RT5682_4BTN_IL_CMD_1:
520 case RT5682_4BTN_IL_CMD_2:
521 case RT5682_4BTN_IL_CMD_3:
522 case RT5682_4BTN_IL_CMD_4:
523 case RT5682_4BTN_IL_CMD_5:
524 case RT5682_4BTN_IL_CMD_6:
525 case RT5682_4BTN_IL_CMD_7:
526 case RT5682_ADC_STO1_HP_CTRL_1:
527 case RT5682_ADC_STO1_HP_CTRL_2:
528 case RT5682_AJD1_CTRL:
529 case RT5682_JD1_THD:
530 case RT5682_JD2_THD:
531 case RT5682_JD_CTRL_1:
532 case RT5682_DUMMY_1:
533 case RT5682_DUMMY_2:
534 case RT5682_DUMMY_3:
535 case RT5682_DAC_ADC_DIG_VOL1:
536 case RT5682_BIAS_CUR_CTRL_2:
537 case RT5682_BIAS_CUR_CTRL_3:
538 case RT5682_BIAS_CUR_CTRL_4:
539 case RT5682_BIAS_CUR_CTRL_5:
540 case RT5682_BIAS_CUR_CTRL_6:
541 case RT5682_BIAS_CUR_CTRL_7:
542 case RT5682_BIAS_CUR_CTRL_8:
543 case RT5682_BIAS_CUR_CTRL_9:
544 case RT5682_BIAS_CUR_CTRL_10:
545 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
546 case RT5682_CHARGE_PUMP_1:
547 case RT5682_DIG_IN_CTRL_1:
548 case RT5682_PAD_DRIVING_CTRL:
549 case RT5682_SOFT_RAMP_DEPOP:
550 case RT5682_CHOP_DAC:
551 case RT5682_CHOP_ADC:
552 case RT5682_CALIB_ADC_CTRL:
553 case RT5682_VOL_TEST:
554 case RT5682_SPKVDD_DET_STA:
555 case RT5682_TEST_MODE_CTRL_1:
556 case RT5682_TEST_MODE_CTRL_2:
557 case RT5682_TEST_MODE_CTRL_3:
558 case RT5682_TEST_MODE_CTRL_4:
559 case RT5682_TEST_MODE_CTRL_5:
560 case RT5682_PLL1_INTERNAL:
561 case RT5682_PLL2_INTERNAL:
562 case RT5682_STO_NG2_CTRL_1:
563 case RT5682_STO_NG2_CTRL_2:
564 case RT5682_STO_NG2_CTRL_3:
565 case RT5682_STO_NG2_CTRL_4:
566 case RT5682_STO_NG2_CTRL_5:
567 case RT5682_STO_NG2_CTRL_6:
568 case RT5682_STO_NG2_CTRL_7:
569 case RT5682_STO_NG2_CTRL_8:
570 case RT5682_STO_NG2_CTRL_9:
571 case RT5682_STO_NG2_CTRL_10:
572 case RT5682_STO1_DAC_SIL_DET:
573 case RT5682_SIL_PSV_CTRL1:
574 case RT5682_SIL_PSV_CTRL2:
575 case RT5682_SIL_PSV_CTRL3:
576 case RT5682_SIL_PSV_CTRL4:
577 case RT5682_SIL_PSV_CTRL5:
578 case RT5682_HP_IMP_SENS_CTRL_01:
579 case RT5682_HP_IMP_SENS_CTRL_02:
580 case RT5682_HP_IMP_SENS_CTRL_03:
581 case RT5682_HP_IMP_SENS_CTRL_04:
582 case RT5682_HP_IMP_SENS_CTRL_05:
583 case RT5682_HP_IMP_SENS_CTRL_06:
584 case RT5682_HP_IMP_SENS_CTRL_07:
585 case RT5682_HP_IMP_SENS_CTRL_08:
586 case RT5682_HP_IMP_SENS_CTRL_09:
587 case RT5682_HP_IMP_SENS_CTRL_10:
588 case RT5682_HP_IMP_SENS_CTRL_11:
589 case RT5682_HP_IMP_SENS_CTRL_12:
590 case RT5682_HP_IMP_SENS_CTRL_13:
591 case RT5682_HP_IMP_SENS_CTRL_14:
592 case RT5682_HP_IMP_SENS_CTRL_15:
593 case RT5682_HP_IMP_SENS_CTRL_16:
594 case RT5682_HP_IMP_SENS_CTRL_17:
595 case RT5682_HP_IMP_SENS_CTRL_18:
596 case RT5682_HP_IMP_SENS_CTRL_19:
597 case RT5682_HP_IMP_SENS_CTRL_20:
598 case RT5682_HP_IMP_SENS_CTRL_21:
599 case RT5682_HP_IMP_SENS_CTRL_22:
600 case RT5682_HP_IMP_SENS_CTRL_23:
601 case RT5682_HP_IMP_SENS_CTRL_24:
602 case RT5682_HP_IMP_SENS_CTRL_25:
603 case RT5682_HP_IMP_SENS_CTRL_26:
604 case RT5682_HP_IMP_SENS_CTRL_27:
605 case RT5682_HP_IMP_SENS_CTRL_28:
606 case RT5682_HP_IMP_SENS_CTRL_29:
607 case RT5682_HP_IMP_SENS_CTRL_30:
608 case RT5682_HP_IMP_SENS_CTRL_31:
609 case RT5682_HP_IMP_SENS_CTRL_32:
610 case RT5682_HP_IMP_SENS_CTRL_33:
611 case RT5682_HP_IMP_SENS_CTRL_34:
612 case RT5682_HP_IMP_SENS_CTRL_35:
613 case RT5682_HP_IMP_SENS_CTRL_36:
614 case RT5682_HP_IMP_SENS_CTRL_37:
615 case RT5682_HP_IMP_SENS_CTRL_38:
616 case RT5682_HP_IMP_SENS_CTRL_39:
617 case RT5682_HP_IMP_SENS_CTRL_40:
618 case RT5682_HP_IMP_SENS_CTRL_41:
619 case RT5682_HP_IMP_SENS_CTRL_42:
620 case RT5682_HP_IMP_SENS_CTRL_43:
621 case RT5682_HP_LOGIC_CTRL_1:
622 case RT5682_HP_LOGIC_CTRL_2:
623 case RT5682_HP_LOGIC_CTRL_3:
624 case RT5682_HP_CALIB_CTRL_1:
625 case RT5682_HP_CALIB_CTRL_2:
626 case RT5682_HP_CALIB_CTRL_3:
627 case RT5682_HP_CALIB_CTRL_4:
628 case RT5682_HP_CALIB_CTRL_5:
629 case RT5682_HP_CALIB_CTRL_6:
630 case RT5682_HP_CALIB_CTRL_7:
631 case RT5682_HP_CALIB_CTRL_9:
632 case RT5682_HP_CALIB_CTRL_10:
633 case RT5682_HP_CALIB_CTRL_11:
634 case RT5682_HP_CALIB_STA_1:
635 case RT5682_HP_CALIB_STA_2:
636 case RT5682_HP_CALIB_STA_3:
637 case RT5682_HP_CALIB_STA_4:
638 case RT5682_HP_CALIB_STA_5:
639 case RT5682_HP_CALIB_STA_6:
640 case RT5682_HP_CALIB_STA_7:
641 case RT5682_HP_CALIB_STA_8:
642 case RT5682_HP_CALIB_STA_9:
643 case RT5682_HP_CALIB_STA_10:
644 case RT5682_HP_CALIB_STA_11:
645 case RT5682_SAR_IL_CMD_1:
646 case RT5682_SAR_IL_CMD_2:
647 case RT5682_SAR_IL_CMD_3:
648 case RT5682_SAR_IL_CMD_4:
649 case RT5682_SAR_IL_CMD_5:
650 case RT5682_SAR_IL_CMD_6:
651 case RT5682_SAR_IL_CMD_7:
652 case RT5682_SAR_IL_CMD_8:
653 case RT5682_SAR_IL_CMD_9:
654 case RT5682_SAR_IL_CMD_10:
655 case RT5682_SAR_IL_CMD_11:
656 case RT5682_SAR_IL_CMD_12:
657 case RT5682_SAR_IL_CMD_13:
658 case RT5682_EFUSE_CTRL_1:
659 case RT5682_EFUSE_CTRL_2:
660 case RT5682_EFUSE_CTRL_3:
661 case RT5682_EFUSE_CTRL_4:
662 case RT5682_EFUSE_CTRL_5:
663 case RT5682_EFUSE_CTRL_6:
664 case RT5682_EFUSE_CTRL_7:
665 case RT5682_EFUSE_CTRL_8:
666 case RT5682_EFUSE_CTRL_9:
667 case RT5682_EFUSE_CTRL_10:
668 case RT5682_EFUSE_CTRL_11:
669 case RT5682_JD_TOP_VC_VTRL:
670 case RT5682_DRC1_CTRL_0:
671 case RT5682_DRC1_CTRL_1:
672 case RT5682_DRC1_CTRL_2:
673 case RT5682_DRC1_CTRL_3:
674 case RT5682_DRC1_CTRL_4:
675 case RT5682_DRC1_CTRL_5:
676 case RT5682_DRC1_CTRL_6:
677 case RT5682_DRC1_HARD_LMT_CTRL_1:
678 case RT5682_DRC1_HARD_LMT_CTRL_2:
679 case RT5682_DRC1_PRIV_1:
680 case RT5682_DRC1_PRIV_2:
681 case RT5682_DRC1_PRIV_3:
682 case RT5682_DRC1_PRIV_4:
683 case RT5682_DRC1_PRIV_5:
684 case RT5682_DRC1_PRIV_6:
685 case RT5682_DRC1_PRIV_7:
686 case RT5682_DRC1_PRIV_8:
687 case RT5682_EQ_AUTO_RCV_CTRL1:
688 case RT5682_EQ_AUTO_RCV_CTRL2:
689 case RT5682_EQ_AUTO_RCV_CTRL3:
690 case RT5682_EQ_AUTO_RCV_CTRL4:
691 case RT5682_EQ_AUTO_RCV_CTRL5:
692 case RT5682_EQ_AUTO_RCV_CTRL6:
693 case RT5682_EQ_AUTO_RCV_CTRL7:
694 case RT5682_EQ_AUTO_RCV_CTRL8:
695 case RT5682_EQ_AUTO_RCV_CTRL9:
696 case RT5682_EQ_AUTO_RCV_CTRL10:
697 case RT5682_EQ_AUTO_RCV_CTRL11:
698 case RT5682_EQ_AUTO_RCV_CTRL12:
699 case RT5682_EQ_AUTO_RCV_CTRL13:
700 case RT5682_ADC_L_EQ_LPF1_A1:
701 case RT5682_R_EQ_LPF1_A1:
702 case RT5682_L_EQ_LPF1_H0:
703 case RT5682_R_EQ_LPF1_H0:
704 case RT5682_L_EQ_BPF1_A1:
705 case RT5682_R_EQ_BPF1_A1:
706 case RT5682_L_EQ_BPF1_A2:
707 case RT5682_R_EQ_BPF1_A2:
708 case RT5682_L_EQ_BPF1_H0:
709 case RT5682_R_EQ_BPF1_H0:
710 case RT5682_L_EQ_BPF2_A1:
711 case RT5682_R_EQ_BPF2_A1:
712 case RT5682_L_EQ_BPF2_A2:
713 case RT5682_R_EQ_BPF2_A2:
714 case RT5682_L_EQ_BPF2_H0:
715 case RT5682_R_EQ_BPF2_H0:
716 case RT5682_L_EQ_BPF3_A1:
717 case RT5682_R_EQ_BPF3_A1:
718 case RT5682_L_EQ_BPF3_A2:
719 case RT5682_R_EQ_BPF3_A2:
720 case RT5682_L_EQ_BPF3_H0:
721 case RT5682_R_EQ_BPF3_H0:
722 case RT5682_L_EQ_BPF4_A1:
723 case RT5682_R_EQ_BPF4_A1:
724 case RT5682_L_EQ_BPF4_A2:
725 case RT5682_R_EQ_BPF4_A2:
726 case RT5682_L_EQ_BPF4_H0:
727 case RT5682_R_EQ_BPF4_H0:
728 case RT5682_L_EQ_HPF1_A1:
729 case RT5682_R_EQ_HPF1_A1:
730 case RT5682_L_EQ_HPF1_H0:
731 case RT5682_R_EQ_HPF1_H0:
732 case RT5682_L_EQ_PRE_VOL:
733 case RT5682_R_EQ_PRE_VOL:
734 case RT5682_L_EQ_POST_VOL:
735 case RT5682_R_EQ_POST_VOL:
736 case RT5682_I2C_MODE:
737 return true;
738 default:
739 return false;
740 }
741}
742EXPORT_SYMBOL_GPL(rt5682_readable_register);
743
744static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
745static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
746static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
747
748
749static const DECLARE_TLV_DB_RANGE(bst_tlv,
750 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
751 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
752 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
753 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
754 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
755 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
756 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
757);
758
759
760static const char * const rt5682_data_select[] = {
761 "L/R", "R/L", "L/L", "R/R"
762};
763
764static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
765 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
766
767static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
768 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
769
770static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
771 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
772
773static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
774 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
775
776static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
778
779static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
780 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
781
782static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
783 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
784
785static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
786 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
787
788static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
789 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
790
791static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
793
794static const char * const rt5682_dac_select[] = {
795 "IF1", "SOUND"
796};
797
798static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
799 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
800
801static const struct snd_kcontrol_new rt5682_dac_l_mux =
802 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
803
804static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
805 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
806
807static const struct snd_kcontrol_new rt5682_dac_r_mux =
808 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
809
810void rt5682_reset(struct rt5682_priv *rt5682)
811{
812 regmap_write(rt5682->regmap, RT5682_RESET, 0);
813 if (!rt5682->is_sdw)
814 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
815}
816EXPORT_SYMBOL_GPL(rt5682_reset);
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
833 unsigned int filter_mask, unsigned int clk_src)
834{
835 switch (clk_src) {
836 case RT5682_CLK_SEL_SYS:
837 case RT5682_CLK_SEL_I2S1_ASRC:
838 case RT5682_CLK_SEL_I2S2_ASRC:
839 break;
840
841 default:
842 return -EINVAL;
843 }
844
845 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
846 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
847 RT5682_FILTER_CLK_SEL_MASK,
848 clk_src << RT5682_FILTER_CLK_SEL_SFT);
849 }
850
851 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
852 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
853 RT5682_FILTER_CLK_SEL_MASK,
854 clk_src << RT5682_FILTER_CLK_SEL_SFT);
855 }
856
857 return 0;
858}
859EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
860
861static int rt5682_button_detect(struct snd_soc_component *component)
862{
863 int btn_type, val;
864
865 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
866 btn_type = val & 0xfff0;
867 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
868 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
869 snd_soc_component_update_bits(component,
870 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
871
872 return btn_type;
873}
874
875static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
876 bool enable)
877{
878 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
879
880 if (enable) {
881 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
882 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
883 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
884 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
885 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
886 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
887 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
888 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
889 if (rt5682->is_sdw)
890 snd_soc_component_update_bits(component,
891 RT5682_IRQ_CTRL_3,
892 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
893 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
894 else
895 snd_soc_component_update_bits(component,
896 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
897 RT5682_IL_IRQ_EN);
898 } else {
899 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
900 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
901 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
902 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
903 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
904 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
905 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
906 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
907 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
908 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
909 }
910}
911
912
913
914
915
916
917
918
919
920
921int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
922{
923 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
924 struct snd_soc_dapm_context *dapm = &component->dapm;
925 unsigned int val, count;
926
927 if (jack_insert) {
928 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
929 RT5682_PWR_VREF2 | RT5682_PWR_MB,
930 RT5682_PWR_VREF2 | RT5682_PWR_MB);
931 snd_soc_component_update_bits(component,
932 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
933 usleep_range(15000, 20000);
934 snd_soc_component_update_bits(component,
935 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
936 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
937 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
938 snd_soc_component_update_bits(component,
939 RT5682_HP_CHARGE_PUMP_1,
940 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
941 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
942 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
943
944 count = 0;
945 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
946 & RT5682_JACK_TYPE_MASK;
947 while (val == 0 && count < 50) {
948 usleep_range(10000, 15000);
949 val = snd_soc_component_read(component,
950 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
951 count++;
952 }
953
954 switch (val) {
955 case 0x1:
956 case 0x2:
957 rt5682->jack_type = SND_JACK_HEADSET;
958 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
959 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
960 rt5682_enable_push_button_irq(component, true);
961 break;
962 default:
963 rt5682->jack_type = SND_JACK_HEADPHONE;
964 break;
965 }
966
967 snd_soc_component_update_bits(component,
968 RT5682_HP_CHARGE_PUMP_1,
969 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
970 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
971 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
972 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
973 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
974 } else {
975 rt5682_enable_push_button_irq(component, false);
976 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
977 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
978 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
979 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
980 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
981 snd_soc_component_update_bits(component,
982 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
983 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
984 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
985 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
986 snd_soc_component_update_bits(component,
987 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
988 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
989 RT5682_PWR_CBJ, 0);
990 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
991 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
992 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
993 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
994 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
995
996 rt5682->jack_type = 0;
997 }
998
999 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1000 return rt5682->jack_type;
1001}
1002EXPORT_SYMBOL_GPL(rt5682_headset_detect);
1003
1004static int rt5682_set_jack_detect(struct snd_soc_component *component,
1005 struct snd_soc_jack *hs_jack, void *data)
1006{
1007 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1008
1009 rt5682->hs_jack = hs_jack;
1010
1011 if (!hs_jack) {
1012 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1013 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1014 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1015 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1016 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1017
1018 return 0;
1019 }
1020
1021 if (!rt5682->is_sdw) {
1022 switch (rt5682->pdata.jd_src) {
1023 case RT5682_JD1:
1024 snd_soc_component_update_bits(component,
1025 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1026 snd_soc_component_update_bits(component,
1027 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1028 RT5682_EXT_JD_SRC_MANUAL);
1029 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1030 0xd142);
1031 snd_soc_component_update_bits(component,
1032 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1033 RT5682_CBJ_IN_BUF_EN);
1034 snd_soc_component_update_bits(component,
1035 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1036 RT5682_SAR_POW_EN);
1037 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1038 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1039 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1040 RT5682_POW_IRQ | RT5682_POW_JDH |
1041 RT5682_POW_ANA, RT5682_POW_IRQ |
1042 RT5682_POW_JDH | RT5682_POW_ANA);
1043 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1044 RT5682_PWR_JDH, RT5682_PWR_JDH);
1045 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1046 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1047 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1050 rt5682->pdata.btndet_delay));
1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1053 rt5682->pdata.btndet_delay));
1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1056 rt5682->pdata.btndet_delay));
1057 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1058 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1059 rt5682->pdata.btndet_delay));
1060 mod_delayed_work(system_power_efficient_wq,
1061 &rt5682->jack_detect_work,
1062 msecs_to_jiffies(250));
1063 break;
1064
1065 case RT5682_JD_NULL:
1066 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1067 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1068 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1069 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1070 break;
1071
1072 default:
1073 dev_warn(component->dev, "Wrong JD source\n");
1074 break;
1075 }
1076 }
1077
1078 return 0;
1079}
1080
1081void rt5682_jack_detect_handler(struct work_struct *work)
1082{
1083 struct rt5682_priv *rt5682 =
1084 container_of(work, struct rt5682_priv, jack_detect_work.work);
1085 int val, btn_type;
1086
1087 while (!rt5682->component)
1088 usleep_range(10000, 15000);
1089
1090 while (!rt5682->component->card->instantiated)
1091 usleep_range(10000, 15000);
1092
1093 mutex_lock(&rt5682->calibrate_mutex);
1094
1095 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1096 & RT5682_JDH_RS_MASK;
1097 if (!val) {
1098
1099 if (rt5682->jack_type == 0) {
1100
1101 rt5682->jack_type =
1102 rt5682_headset_detect(rt5682->component, 1);
1103 rt5682->irq_work_delay_time = 0;
1104 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1105 SND_JACK_HEADSET) {
1106
1107 rt5682->jack_type = SND_JACK_HEADSET;
1108 btn_type = rt5682_button_detect(rt5682->component);
1109
1110
1111
1112
1113
1114
1115
1116 switch (btn_type) {
1117 case 0x8000:
1118 case 0x4000:
1119 case 0x2000:
1120 rt5682->jack_type |= SND_JACK_BTN_0;
1121 break;
1122 case 0x1000:
1123 case 0x0800:
1124 case 0x0400:
1125 rt5682->jack_type |= SND_JACK_BTN_1;
1126 break;
1127 case 0x0200:
1128 case 0x0100:
1129 case 0x0080:
1130 rt5682->jack_type |= SND_JACK_BTN_2;
1131 break;
1132 case 0x0040:
1133 case 0x0020:
1134 case 0x0010:
1135 rt5682->jack_type |= SND_JACK_BTN_3;
1136 break;
1137 case 0x0000:
1138 break;
1139 default:
1140 dev_err(rt5682->component->dev,
1141 "Unexpected button code 0x%04x\n",
1142 btn_type);
1143 break;
1144 }
1145 }
1146 } else {
1147
1148 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1149 rt5682->irq_work_delay_time = 50;
1150 }
1151
1152 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1153 SND_JACK_HEADSET |
1154 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1155 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1156
1157 if (!rt5682->is_sdw) {
1158 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1159 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1160 schedule_delayed_work(&rt5682->jd_check_work, 0);
1161 else
1162 cancel_delayed_work_sync(&rt5682->jd_check_work);
1163 }
1164
1165 mutex_unlock(&rt5682->calibrate_mutex);
1166}
1167EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1168
1169static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1170
1171 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1172 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1173
1174
1175 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1176 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1177
1178
1179 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1180 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1181 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1182 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1183
1184
1185 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1186 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1187 3, 0, adc_bst_tlv),
1188};
1189
1190static int rt5682_div_sel(struct rt5682_priv *rt5682,
1191 int target, const int div[], int size)
1192{
1193 int i;
1194
1195 if (rt5682->sysclk < target) {
1196 dev_err(rt5682->component->dev,
1197 "sysclk rate %d is too low\n", rt5682->sysclk);
1198 return 0;
1199 }
1200
1201 for (i = 0; i < size - 1; i++) {
1202 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1203 if (target * div[i] == rt5682->sysclk)
1204 return i;
1205 if (target * div[i + 1] > rt5682->sysclk) {
1206 dev_dbg(rt5682->component->dev,
1207 "can't find div for sysclk %d\n",
1208 rt5682->sysclk);
1209 return i;
1210 }
1211 }
1212
1213 if (target * div[i] < rt5682->sysclk)
1214 dev_err(rt5682->component->dev,
1215 "sysclk rate %d is too high\n", rt5682->sysclk);
1216
1217 return size - 1;
1218}
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
1232{
1233 struct snd_soc_component *component =
1234 snd_soc_dapm_to_component(w->dapm);
1235 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1236 int idx, dmic_clk_rate = 3072000;
1237 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1238
1239 if (rt5682->pdata.dmic_clk_rate)
1240 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1241
1242 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1243
1244 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1245 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1246
1247 return 0;
1248}
1249
1250static int set_filter_clk(struct snd_soc_dapm_widget *w,
1251 struct snd_kcontrol *kcontrol, int event)
1252{
1253 struct snd_soc_component *component =
1254 snd_soc_dapm_to_component(w->dapm);
1255 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1256 int ref, val, reg, idx;
1257 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1258 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1259
1260 if (rt5682->is_sdw)
1261 return 0;
1262
1263 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1264 RT5682_GP4_PIN_MASK;
1265 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1266 val == RT5682_GP4_PIN_ADCDAT2)
1267 ref = 256 * rt5682->lrck[RT5682_AIF2];
1268 else
1269 ref = 256 * rt5682->lrck[RT5682_AIF1];
1270
1271 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1272
1273 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1274 reg = RT5682_PLL_TRACK_3;
1275 else
1276 reg = RT5682_PLL_TRACK_2;
1277
1278 snd_soc_component_update_bits(component, reg,
1279 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1280
1281
1282 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1283 if (rt5682->sysclk <= 12288000 * div_o[idx])
1284 break;
1285 }
1286
1287 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1288 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1289 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1290
1291 return 0;
1292}
1293
1294static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1295 struct snd_soc_dapm_widget *sink)
1296{
1297 unsigned int val;
1298 struct snd_soc_component *component =
1299 snd_soc_dapm_to_component(w->dapm);
1300
1301 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1302 val &= RT5682_SCLK_SRC_MASK;
1303 if (val == RT5682_SCLK_SRC_PLL1)
1304 return 1;
1305 else
1306 return 0;
1307}
1308
1309static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1310 struct snd_soc_dapm_widget *sink)
1311{
1312 unsigned int val;
1313 struct snd_soc_component *component =
1314 snd_soc_dapm_to_component(w->dapm);
1315
1316 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1317 val &= RT5682_SCLK_SRC_MASK;
1318 if (val == RT5682_SCLK_SRC_PLL2)
1319 return 1;
1320 else
1321 return 0;
1322}
1323
1324static int is_using_asrc(struct snd_soc_dapm_widget *w,
1325 struct snd_soc_dapm_widget *sink)
1326{
1327 unsigned int reg, shift, val;
1328 struct snd_soc_component *component =
1329 snd_soc_dapm_to_component(w->dapm);
1330
1331 switch (w->shift) {
1332 case RT5682_ADC_STO1_ASRC_SFT:
1333 reg = RT5682_PLL_TRACK_3;
1334 shift = RT5682_FILTER_CLK_SEL_SFT;
1335 break;
1336 case RT5682_DAC_STO1_ASRC_SFT:
1337 reg = RT5682_PLL_TRACK_2;
1338 shift = RT5682_FILTER_CLK_SEL_SFT;
1339 break;
1340 default:
1341 return 0;
1342 }
1343
1344 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1345 switch (val) {
1346 case RT5682_CLK_SEL_I2S1_ASRC:
1347 case RT5682_CLK_SEL_I2S2_ASRC:
1348 return 1;
1349 default:
1350 return 0;
1351 }
1352}
1353
1354
1355static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1356 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1357 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1358 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1359 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1360};
1361
1362static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1363 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1364 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1365 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1366 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1367};
1368
1369static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1370 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1371 RT5682_M_ADCMIX_L_SFT, 1, 1),
1372 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1373 RT5682_M_DAC1_L_SFT, 1, 1),
1374};
1375
1376static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1377 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1378 RT5682_M_ADCMIX_R_SFT, 1, 1),
1379 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1380 RT5682_M_DAC1_R_SFT, 1, 1),
1381};
1382
1383static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1384 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1385 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1386 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1387 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1388};
1389
1390static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1391 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1392 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1393 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1394 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1395};
1396
1397
1398static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1399 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1400 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1401};
1402
1403
1404
1405static const char * const rt5682_sto1_adc1_src[] = {
1406 "DAC MIX", "ADC"
1407};
1408
1409static SOC_ENUM_SINGLE_DECL(
1410 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1411 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1412
1413static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1414 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1415
1416static SOC_ENUM_SINGLE_DECL(
1417 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1418 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1419
1420static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1421 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1422
1423
1424
1425static const char * const rt5682_sto1_adc_src[] = {
1426 "ADC1 L", "ADC1 R"
1427};
1428
1429static SOC_ENUM_SINGLE_DECL(
1430 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1431 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1432
1433static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1434 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1435
1436static SOC_ENUM_SINGLE_DECL(
1437 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1438 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1439
1440static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1441 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1442
1443
1444
1445static const char * const rt5682_sto1_adc2_src[] = {
1446 "DAC MIX", "DMIC"
1447};
1448
1449static SOC_ENUM_SINGLE_DECL(
1450 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1451 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1452
1453static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1454 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1455
1456static SOC_ENUM_SINGLE_DECL(
1457 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1458 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1459
1460static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1461 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1462
1463
1464static const unsigned int rt5682_if1_adc_slot_values[] = {
1465 0,
1466 2,
1467 4,
1468 6,
1469};
1470
1471static const char * const rt5682_if1_adc_slot_src[] = {
1472 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1473};
1474
1475static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1476 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1477 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1478
1479static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1480 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1481
1482
1483
1484static const char * const rt5682_alg_dac1_src[] = {
1485 "Stereo1 DAC Mixer", "DAC1"
1486};
1487
1488static SOC_ENUM_SINGLE_DECL(
1489 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1490 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1491
1492static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1493 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1494
1495static SOC_ENUM_SINGLE_DECL(
1496 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1497 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1498
1499static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1500 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1501
1502
1503static const struct snd_kcontrol_new hpol_switch =
1504 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1505 RT5682_L_MUTE_SFT, 1, 1);
1506static const struct snd_kcontrol_new hpor_switch =
1507 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1508 RT5682_R_MUTE_SFT, 1, 1);
1509
1510static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1511 struct snd_kcontrol *kcontrol, int event)
1512{
1513 struct snd_soc_component *component =
1514 snd_soc_dapm_to_component(w->dapm);
1515
1516 switch (event) {
1517 case SND_SOC_DAPM_PRE_PMU:
1518 snd_soc_component_write(component,
1519 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1520 snd_soc_component_write(component,
1521 RT5682_HP_CTRL_2, 0x6000);
1522 snd_soc_component_update_bits(component,
1523 RT5682_DEPOP_1, 0x60, 0x60);
1524 snd_soc_component_update_bits(component,
1525 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1526 break;
1527
1528 case SND_SOC_DAPM_POST_PMD:
1529 snd_soc_component_update_bits(component,
1530 RT5682_DEPOP_1, 0x60, 0x0);
1531 snd_soc_component_write(component,
1532 RT5682_HP_CTRL_2, 0x0000);
1533 snd_soc_component_update_bits(component,
1534 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1535 break;
1536 }
1537
1538 return 0;
1539}
1540
1541static int set_dmic_power(struct snd_soc_dapm_widget *w,
1542 struct snd_kcontrol *kcontrol, int event)
1543{
1544 struct snd_soc_component *component =
1545 snd_soc_dapm_to_component(w->dapm);
1546 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1547 unsigned int delay = 50, val;
1548
1549 if (rt5682->pdata.dmic_delay)
1550 delay = rt5682->pdata.dmic_delay;
1551
1552 switch (event) {
1553 case SND_SOC_DAPM_POST_PMU:
1554 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1555 val &= RT5682_SCLK_SRC_MASK;
1556 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1557 snd_soc_component_update_bits(component,
1558 RT5682_PWR_ANLG_1,
1559 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1560 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1561
1562
1563 msleep(delay);
1564 break;
1565
1566 case SND_SOC_DAPM_POST_PMD:
1567 if (!rt5682->jack_type) {
1568 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1569 snd_soc_component_update_bits(component,
1570 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1571 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1572 snd_soc_component_update_bits(component,
1573 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1574 }
1575 break;
1576 }
1577
1578 return 0;
1579}
1580
1581static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1582 struct snd_kcontrol *kcontrol, int event)
1583{
1584 struct snd_soc_component *component =
1585 snd_soc_dapm_to_component(w->dapm);
1586
1587 switch (event) {
1588 case SND_SOC_DAPM_PRE_PMU:
1589 switch (w->shift) {
1590 case RT5682_PWR_VREF1_BIT:
1591 snd_soc_component_update_bits(component,
1592 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1593 break;
1594
1595 case RT5682_PWR_VREF2_BIT:
1596 snd_soc_component_update_bits(component,
1597 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1598 break;
1599 }
1600 break;
1601
1602 case SND_SOC_DAPM_POST_PMU:
1603 usleep_range(15000, 20000);
1604 switch (w->shift) {
1605 case RT5682_PWR_VREF1_BIT:
1606 snd_soc_component_update_bits(component,
1607 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1608 RT5682_PWR_FV1);
1609 break;
1610
1611 case RT5682_PWR_VREF2_BIT:
1612 snd_soc_component_update_bits(component,
1613 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1614 RT5682_PWR_FV2);
1615 break;
1616 }
1617 break;
1618 }
1619
1620 return 0;
1621}
1622
1623static const unsigned int rt5682_adcdat_pin_values[] = {
1624 1,
1625 3,
1626};
1627
1628static const char * const rt5682_adcdat_pin_select[] = {
1629 "ADCDAT1",
1630 "ADCDAT2",
1631};
1632
1633static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1634 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1635 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1636
1637static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1638 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1639
1640static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1641 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1642 0, NULL, 0),
1643 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1644 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1646 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1648 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1649 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1650 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1651 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1652 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1653
1654
1655 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1656 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1657 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1658 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1660 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1661 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1662 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1663 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1664 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1665
1666
1667 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1668 0, NULL, 0),
1669 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1670 0, NULL, 0),
1671
1672
1673 SND_SOC_DAPM_INPUT("DMIC L1"),
1674 SND_SOC_DAPM_INPUT("DMIC R1"),
1675
1676 SND_SOC_DAPM_INPUT("IN1P"),
1677
1678 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1679 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1680 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1681 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1682 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1683
1684
1685 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1686 0, 0, NULL, 0),
1687
1688
1689 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1690 ARRAY_SIZE(rt5682_rec1_l_mix)),
1691 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1692 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1693
1694
1695 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1696 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1697
1698 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1699 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1700 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1701 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1702 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1703 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1704
1705
1706 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1707 &rt5682_sto1_adc1l_mux),
1708 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1709 &rt5682_sto1_adc1r_mux),
1710 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1711 &rt5682_sto1_adc2l_mux),
1712 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1713 &rt5682_sto1_adc2r_mux),
1714 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1715 &rt5682_sto1_adcl_mux),
1716 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1717 &rt5682_sto1_adcr_mux),
1718 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1719 &rt5682_if1_adc_slot_mux),
1720
1721
1722 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1723 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1724 SND_SOC_DAPM_PRE_PMU),
1725 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1726 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1727 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1728 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1729 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1730 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1731
1732
1733 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735
1736 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1737 0, NULL, 0),
1738 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1739 0, NULL, 0),
1740 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1742 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1743 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1744 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1745
1746
1747 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5682_if1_01_adc_swap_mux),
1749 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5682_if1_23_adc_swap_mux),
1751 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5682_if1_45_adc_swap_mux),
1753 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5682_if1_67_adc_swap_mux),
1755 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5682_if2_adc_swap_mux),
1757
1758 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5682_adcdat_pin_ctrl),
1760
1761 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1762 &rt5682_dac_l_mux),
1763 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1764 &rt5682_dac_r_mux),
1765
1766
1767 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1768 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1769 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1770 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1771 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1772 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1773 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1774
1775
1776
1777 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1778 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1779 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1780 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1781
1782
1783 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1784 &rt5682_alg_dac_l1_mux),
1785 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1786 &rt5682_alg_dac_r1_mux),
1787
1788
1789 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1790 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1791 SND_SOC_DAPM_PRE_PMU),
1792 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1793 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1794 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1795 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1796
1797
1798 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1799 RT5682_PWR_DAC_L1_BIT, 0),
1800 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1801 RT5682_PWR_DAC_R1_BIT, 0),
1802 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1803 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1804
1805
1806 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1807 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1808
1809 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1810 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1811 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1812 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1813 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1814 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1815 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1816 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1817
1818 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1819 &hpol_switch),
1820 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1821 &hpor_switch),
1822
1823
1824 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1825 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1826 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1827 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1828 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1829 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1830 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1831 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1832
1833
1834 SND_SOC_DAPM_OUTPUT("HPOL"),
1835 SND_SOC_DAPM_OUTPUT("HPOR"),
1836};
1837
1838static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1839
1840 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1841 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1842 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1843 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1844 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1845 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1846
1847
1848 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1849 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1850 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1851 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1852 {"ADC STO1 ASRC", NULL, "CLKDET"},
1853 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1854 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1855 {"DAC STO1 ASRC", NULL, "CLKDET"},
1856
1857
1858 {"MICBIAS1", NULL, "Vref1"},
1859 {"MICBIAS2", NULL, "Vref1"},
1860
1861 {"CLKDET SYS", NULL, "CLKDET"},
1862
1863 {"BST1 CBJ", NULL, "IN1P"},
1864
1865 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1866 {"RECMIX1L", NULL, "RECMIX1L Power"},
1867
1868 {"ADC1 L", NULL, "RECMIX1L"},
1869 {"ADC1 L", NULL, "ADC1 L Power"},
1870 {"ADC1 L", NULL, "ADC1 clock"},
1871
1872 {"DMIC L1", NULL, "DMIC CLK"},
1873 {"DMIC L1", NULL, "DMIC1 Power"},
1874 {"DMIC R1", NULL, "DMIC CLK"},
1875 {"DMIC R1", NULL, "DMIC1 Power"},
1876 {"DMIC CLK", NULL, "DMIC ASRC"},
1877
1878 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1879 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1880 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1881 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1882
1883 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1884 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1885 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1886 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1887
1888 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1889 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1890 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1891 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1892
1893 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1894 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1895 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1896
1897 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1898 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1899 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1900
1901 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1902 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1903
1904 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1905 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1906 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1907 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1908 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1909 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1911 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1912 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1913 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1914 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1915 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1916 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1917 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1918 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1919 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1920
1921 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1922 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1923 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1924 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1925 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1926 {"AIF1TX", NULL, "I2S1"},
1927 {"AIF1TX", NULL, "ADCDAT Mux"},
1928 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1929 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1930 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1931 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1932 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1933 {"AIF2TX", NULL, "ADCDAT Mux"},
1934
1935 {"SDWTX", NULL, "PLL2B"},
1936 {"SDWTX", NULL, "PLL2F"},
1937 {"SDWTX", NULL, "ADCDAT Mux"},
1938
1939 {"IF1 DAC1 L", NULL, "AIF1RX"},
1940 {"IF1 DAC1 L", NULL, "I2S1"},
1941 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1942 {"IF1 DAC1 R", NULL, "AIF1RX"},
1943 {"IF1 DAC1 R", NULL, "I2S1"},
1944 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1945
1946 {"SOUND DAC L", NULL, "SDWRX"},
1947 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1948 {"SOUND DAC L", NULL, "PLL2B"},
1949 {"SOUND DAC L", NULL, "PLL2F"},
1950 {"SOUND DAC R", NULL, "SDWRX"},
1951 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1952 {"SOUND DAC R", NULL, "PLL2B"},
1953 {"SOUND DAC R", NULL, "PLL2F"},
1954
1955 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1956 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1957 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1958 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1959
1960 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1961 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1962 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1963 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1964
1965 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1966 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1967
1968 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1969 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1970
1971 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1972 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1973 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1974 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1975
1976 {"DAC L1", NULL, "DAC L1 Source"},
1977 {"DAC R1", NULL, "DAC R1 Source"},
1978
1979 {"DAC L1", NULL, "DAC 1 Clock"},
1980 {"DAC R1", NULL, "DAC 1 Clock"},
1981
1982 {"HP Amp", NULL, "DAC L1"},
1983 {"HP Amp", NULL, "DAC R1"},
1984 {"HP Amp", NULL, "HP Amp L"},
1985 {"HP Amp", NULL, "HP Amp R"},
1986 {"HP Amp", NULL, "Capless"},
1987 {"HP Amp", NULL, "Charge Pump"},
1988 {"HP Amp", NULL, "CLKDET SYS"},
1989 {"HP Amp", NULL, "Vref1"},
1990 {"HPOL Playback", "Switch", "HP Amp"},
1991 {"HPOR Playback", "Switch", "HP Amp"},
1992 {"HPOL", NULL, "HPOL Playback"},
1993 {"HPOR", NULL, "HPOR Playback"},
1994};
1995
1996static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1997 unsigned int rx_mask, int slots, int slot_width)
1998{
1999 struct snd_soc_component *component = dai->component;
2000 unsigned int cl, val = 0;
2001
2002 if (tx_mask || rx_mask)
2003 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2004 RT5682_TDM_EN, RT5682_TDM_EN);
2005 else
2006 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2007 RT5682_TDM_EN, 0);
2008
2009 switch (slots) {
2010 case 4:
2011 val |= RT5682_TDM_TX_CH_4;
2012 val |= RT5682_TDM_RX_CH_4;
2013 break;
2014 case 6:
2015 val |= RT5682_TDM_TX_CH_6;
2016 val |= RT5682_TDM_RX_CH_6;
2017 break;
2018 case 8:
2019 val |= RT5682_TDM_TX_CH_8;
2020 val |= RT5682_TDM_RX_CH_8;
2021 break;
2022 case 2:
2023 break;
2024 default:
2025 return -EINVAL;
2026 }
2027
2028 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2029 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2030
2031 switch (slot_width) {
2032 case 8:
2033 if (tx_mask || rx_mask)
2034 return -EINVAL;
2035 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2036 break;
2037 case 16:
2038 val = RT5682_TDM_CL_16;
2039 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2040 break;
2041 case 20:
2042 val = RT5682_TDM_CL_20;
2043 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2044 break;
2045 case 24:
2046 val = RT5682_TDM_CL_24;
2047 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2048 break;
2049 case 32:
2050 val = RT5682_TDM_CL_32;
2051 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2052 break;
2053 default:
2054 return -EINVAL;
2055 }
2056
2057 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2058 RT5682_TDM_CL_MASK, val);
2059 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2060 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2061
2062 return 0;
2063}
2064
2065static int rt5682_hw_params(struct snd_pcm_substream *substream,
2066 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2067{
2068 struct snd_soc_component *component = dai->component;
2069 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2070 unsigned int len_1 = 0, len_2 = 0;
2071 int pre_div, frame_size;
2072
2073 rt5682->lrck[dai->id] = params_rate(params);
2074 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2075
2076 frame_size = snd_soc_params_to_frame_size(params);
2077 if (frame_size < 0) {
2078 dev_err(component->dev, "Unsupported frame size: %d\n",
2079 frame_size);
2080 return -EINVAL;
2081 }
2082
2083 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2084 rt5682->lrck[dai->id], pre_div, dai->id);
2085
2086 switch (params_width(params)) {
2087 case 16:
2088 break;
2089 case 20:
2090 len_1 |= RT5682_I2S1_DL_20;
2091 len_2 |= RT5682_I2S2_DL_20;
2092 break;
2093 case 24:
2094 len_1 |= RT5682_I2S1_DL_24;
2095 len_2 |= RT5682_I2S2_DL_24;
2096 break;
2097 case 32:
2098 len_1 |= RT5682_I2S1_DL_32;
2099 len_2 |= RT5682_I2S2_DL_24;
2100 break;
2101 case 8:
2102 len_1 |= RT5682_I2S2_DL_8;
2103 len_2 |= RT5682_I2S2_DL_8;
2104 break;
2105 default:
2106 return -EINVAL;
2107 }
2108
2109 switch (dai->id) {
2110 case RT5682_AIF1:
2111 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2112 RT5682_I2S1_DL_MASK, len_1);
2113 if (rt5682->master[RT5682_AIF1]) {
2114 snd_soc_component_update_bits(component,
2115 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2116 RT5682_I2S_CLK_SRC_MASK,
2117 pre_div << RT5682_I2S_M_DIV_SFT |
2118 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2119 }
2120 if (params_channels(params) == 1)
2121 snd_soc_component_update_bits(component,
2122 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2123 RT5682_I2S1_MONO_EN);
2124 else
2125 snd_soc_component_update_bits(component,
2126 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2127 RT5682_I2S1_MONO_DIS);
2128 break;
2129 case RT5682_AIF2:
2130 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2131 RT5682_I2S2_DL_MASK, len_2);
2132 if (rt5682->master[RT5682_AIF2]) {
2133 snd_soc_component_update_bits(component,
2134 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2135 pre_div << RT5682_I2S2_M_PD_SFT);
2136 }
2137 if (params_channels(params) == 1)
2138 snd_soc_component_update_bits(component,
2139 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2140 RT5682_I2S2_MONO_EN);
2141 else
2142 snd_soc_component_update_bits(component,
2143 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2144 RT5682_I2S2_MONO_DIS);
2145 break;
2146 default:
2147 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2148 return -EINVAL;
2149 }
2150
2151 return 0;
2152}
2153
2154static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2155{
2156 struct snd_soc_component *component = dai->component;
2157 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2158 unsigned int reg_val = 0, tdm_ctrl = 0;
2159
2160 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2161 case SND_SOC_DAIFMT_CBM_CFM:
2162 rt5682->master[dai->id] = 1;
2163 break;
2164 case SND_SOC_DAIFMT_CBS_CFS:
2165 rt5682->master[dai->id] = 0;
2166 break;
2167 default:
2168 return -EINVAL;
2169 }
2170
2171 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2172 case SND_SOC_DAIFMT_NB_NF:
2173 break;
2174 case SND_SOC_DAIFMT_IB_NF:
2175 reg_val |= RT5682_I2S_BP_INV;
2176 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2177 break;
2178 case SND_SOC_DAIFMT_NB_IF:
2179 if (dai->id == RT5682_AIF1)
2180 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2181 else
2182 return -EINVAL;
2183 break;
2184 case SND_SOC_DAIFMT_IB_IF:
2185 if (dai->id == RT5682_AIF1)
2186 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2187 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2188 else
2189 return -EINVAL;
2190 break;
2191 default:
2192 return -EINVAL;
2193 }
2194
2195 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2196 case SND_SOC_DAIFMT_I2S:
2197 break;
2198 case SND_SOC_DAIFMT_LEFT_J:
2199 reg_val |= RT5682_I2S_DF_LEFT;
2200 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2201 break;
2202 case SND_SOC_DAIFMT_DSP_A:
2203 reg_val |= RT5682_I2S_DF_PCM_A;
2204 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2205 break;
2206 case SND_SOC_DAIFMT_DSP_B:
2207 reg_val |= RT5682_I2S_DF_PCM_B;
2208 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2209 break;
2210 default:
2211 return -EINVAL;
2212 }
2213
2214 switch (dai->id) {
2215 case RT5682_AIF1:
2216 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2217 RT5682_I2S_DF_MASK, reg_val);
2218 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2219 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2220 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2221 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2222 tdm_ctrl | rt5682->master[dai->id]);
2223 break;
2224 case RT5682_AIF2:
2225 if (rt5682->master[dai->id] == 0)
2226 reg_val |= RT5682_I2S2_MS_S;
2227 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2228 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2229 RT5682_I2S_DF_MASK, reg_val);
2230 break;
2231 default:
2232 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2233 return -EINVAL;
2234 }
2235 return 0;
2236}
2237
2238static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2239 int clk_id, int source, unsigned int freq, int dir)
2240{
2241 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2242 unsigned int reg_val = 0, src = 0;
2243
2244 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2245 return 0;
2246
2247 switch (clk_id) {
2248 case RT5682_SCLK_S_MCLK:
2249 reg_val |= RT5682_SCLK_SRC_MCLK;
2250 src = RT5682_CLK_SRC_MCLK;
2251 break;
2252 case RT5682_SCLK_S_PLL1:
2253 reg_val |= RT5682_SCLK_SRC_PLL1;
2254 src = RT5682_CLK_SRC_PLL1;
2255 break;
2256 case RT5682_SCLK_S_PLL2:
2257 reg_val |= RT5682_SCLK_SRC_PLL2;
2258 src = RT5682_CLK_SRC_PLL2;
2259 break;
2260 case RT5682_SCLK_S_RCCLK:
2261 reg_val |= RT5682_SCLK_SRC_RCCLK;
2262 src = RT5682_CLK_SRC_RCCLK;
2263 break;
2264 default:
2265 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2266 return -EINVAL;
2267 }
2268 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2269 RT5682_SCLK_SRC_MASK, reg_val);
2270
2271 if (rt5682->master[RT5682_AIF2]) {
2272 snd_soc_component_update_bits(component,
2273 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2274 src << RT5682_I2S2_SRC_SFT);
2275 }
2276
2277 rt5682->sysclk = freq;
2278 rt5682->sysclk_src = clk_id;
2279
2280 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2281 freq, clk_id);
2282
2283 return 0;
2284}
2285
2286static int rt5682_set_component_pll(struct snd_soc_component *component,
2287 int pll_id, int source, unsigned int freq_in,
2288 unsigned int freq_out)
2289{
2290 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2291 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2292 unsigned int pll2_fout1, pll2_ps_val;
2293 int ret;
2294
2295 if (source == rt5682->pll_src[pll_id] &&
2296 freq_in == rt5682->pll_in[pll_id] &&
2297 freq_out == rt5682->pll_out[pll_id])
2298 return 0;
2299
2300 if (!freq_in || !freq_out) {
2301 dev_dbg(component->dev, "PLL disabled\n");
2302
2303 rt5682->pll_in[pll_id] = 0;
2304 rt5682->pll_out[pll_id] = 0;
2305 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2306 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2307 return 0;
2308 }
2309
2310 if (pll_id == RT5682_PLL2) {
2311 switch (source) {
2312 case RT5682_PLL2_S_MCLK:
2313 snd_soc_component_update_bits(component,
2314 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2315 RT5682_PLL2_SRC_MCLK);
2316 break;
2317 default:
2318 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2319 source);
2320 return -EINVAL;
2321 }
2322
2323
2324
2325
2326
2327 pll2_fout1 = 3840000;
2328 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2329 if (ret < 0) {
2330 dev_err(component->dev, "Unsupport input clock %d\n",
2331 freq_in);
2332 return ret;
2333 }
2334 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2335 freq_in, pll2_fout1,
2336 pll2f_code.m_bp,
2337 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2338 pll2f_code.n_code, pll2f_code.k_code);
2339
2340 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2341 if (ret < 0) {
2342 dev_err(component->dev, "Unsupport input clock %d\n",
2343 pll2_fout1);
2344 return ret;
2345 }
2346 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2347 pll2_fout1, freq_out,
2348 pll2b_code.m_bp,
2349 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2350 pll2b_code.n_code, pll2b_code.k_code);
2351
2352 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2353 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2354 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2355 pll2b_code.m_code);
2356 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2357 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2358 pll2b_code.n_code);
2359 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2360 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2361
2362 if (freq_out == 22579200)
2363 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2364 else
2365 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2366 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2367 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2368 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2369 pll2_ps_val |
2370 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2371 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2372 0xf);
2373 } else {
2374 switch (source) {
2375 case RT5682_PLL1_S_MCLK:
2376 snd_soc_component_update_bits(component,
2377 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2378 RT5682_PLL1_SRC_MCLK);
2379 break;
2380 case RT5682_PLL1_S_BCLK1:
2381 snd_soc_component_update_bits(component,
2382 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2383 RT5682_PLL1_SRC_BCLK1);
2384 break;
2385 default:
2386 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2387 source);
2388 return -EINVAL;
2389 }
2390
2391 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2392 if (ret < 0) {
2393 dev_err(component->dev, "Unsupport input clock %d\n",
2394 freq_in);
2395 return ret;
2396 }
2397
2398 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2399 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2400 pll_code.n_code, pll_code.k_code);
2401
2402 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2403 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2404 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2405 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2406 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2407 }
2408
2409 rt5682->pll_in[pll_id] = freq_in;
2410 rt5682->pll_out[pll_id] = freq_out;
2411 rt5682->pll_src[pll_id] = source;
2412
2413 return 0;
2414}
2415
2416static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2417{
2418 struct snd_soc_component *component = dai->component;
2419 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2420
2421 rt5682->bclk[dai->id] = ratio;
2422
2423 switch (ratio) {
2424 case 256:
2425 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2426 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2427 break;
2428 case 128:
2429 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2430 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2431 break;
2432 case 64:
2433 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2434 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2435 break;
2436 case 32:
2437 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2438 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2439 break;
2440 default:
2441 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2442 return -EINVAL;
2443 }
2444
2445 return 0;
2446}
2447
2448static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2449{
2450 struct snd_soc_component *component = dai->component;
2451 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2452
2453 rt5682->bclk[dai->id] = ratio;
2454
2455 switch (ratio) {
2456 case 64:
2457 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2458 RT5682_I2S2_BCLK_MS2_MASK,
2459 RT5682_I2S2_BCLK_MS2_64);
2460 break;
2461 case 32:
2462 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2463 RT5682_I2S2_BCLK_MS2_MASK,
2464 RT5682_I2S2_BCLK_MS2_32);
2465 break;
2466 default:
2467 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2468 return -EINVAL;
2469 }
2470
2471 return 0;
2472}
2473
2474static int rt5682_set_bias_level(struct snd_soc_component *component,
2475 enum snd_soc_bias_level level)
2476{
2477 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2478
2479 switch (level) {
2480 case SND_SOC_BIAS_PREPARE:
2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2482 RT5682_PWR_BG, RT5682_PWR_BG);
2483 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2484 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2485 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2486 break;
2487
2488 case SND_SOC_BIAS_STANDBY:
2489 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2490 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2491 break;
2492 case SND_SOC_BIAS_OFF:
2493 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2494 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2495 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2496 RT5682_PWR_BG, 0);
2497 break;
2498 case SND_SOC_BIAS_ON:
2499 break;
2500 }
2501
2502 return 0;
2503}
2504
2505#ifdef CONFIG_COMMON_CLK
2506#define CLK_PLL2_FIN 48000000
2507#define CLK_48 48000
2508#define CLK_44 44100
2509
2510static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2511{
2512 if (!rt5682->master[RT5682_AIF1]) {
2513 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2514 return false;
2515 }
2516 return true;
2517}
2518
2519static int rt5682_wclk_prepare(struct clk_hw *hw)
2520{
2521 struct rt5682_priv *rt5682 =
2522 container_of(hw, struct rt5682_priv,
2523 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2524 struct snd_soc_component *component = rt5682->component;
2525 struct snd_soc_dapm_context *dapm =
2526 snd_soc_component_get_dapm(component);
2527
2528 if (!rt5682_clk_check(rt5682))
2529 return -EINVAL;
2530
2531 snd_soc_dapm_mutex_lock(dapm);
2532
2533 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2534 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2535 RT5682_PWR_MB, RT5682_PWR_MB);
2536
2537 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2538 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2539 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2540 RT5682_PWR_VREF2);
2541 usleep_range(55000, 60000);
2542 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2543 RT5682_PWR_FV2, RT5682_PWR_FV2);
2544
2545 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2546 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2547 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2548 snd_soc_dapm_sync_unlocked(dapm);
2549
2550 snd_soc_dapm_mutex_unlock(dapm);
2551
2552 return 0;
2553}
2554
2555static void rt5682_wclk_unprepare(struct clk_hw *hw)
2556{
2557 struct rt5682_priv *rt5682 =
2558 container_of(hw, struct rt5682_priv,
2559 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2560 struct snd_soc_component *component = rt5682->component;
2561 struct snd_soc_dapm_context *dapm =
2562 snd_soc_component_get_dapm(component);
2563
2564 if (!rt5682_clk_check(rt5682))
2565 return;
2566
2567 snd_soc_dapm_mutex_lock(dapm);
2568
2569 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2570 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2571 if (!rt5682->jack_type)
2572 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2573 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2574 RT5682_PWR_MB, 0);
2575
2576 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2577 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2578 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2579 snd_soc_dapm_sync_unlocked(dapm);
2580
2581 snd_soc_dapm_mutex_unlock(dapm);
2582}
2583
2584static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2585 unsigned long parent_rate)
2586{
2587 struct rt5682_priv *rt5682 =
2588 container_of(hw, struct rt5682_priv,
2589 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2590 struct snd_soc_component *component = rt5682->component;
2591 const char * const clk_name = clk_hw_get_name(hw);
2592
2593 if (!rt5682_clk_check(rt5682))
2594 return 0;
2595
2596
2597
2598 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2599 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2600 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2601 __func__, clk_name, CLK_44, CLK_48);
2602 return 0;
2603 }
2604
2605 return rt5682->lrck[RT5682_AIF1];
2606}
2607
2608static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2609 unsigned long *parent_rate)
2610{
2611 struct rt5682_priv *rt5682 =
2612 container_of(hw, struct rt5682_priv,
2613 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2614 struct snd_soc_component *component = rt5682->component;
2615 const char * const clk_name = clk_hw_get_name(hw);
2616
2617 if (!rt5682_clk_check(rt5682))
2618 return -EINVAL;
2619
2620
2621
2622
2623 if (rate != CLK_48 && rate != CLK_44) {
2624 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2625 __func__, clk_name, CLK_44, CLK_48);
2626 rate = CLK_48;
2627 }
2628
2629 return rate;
2630}
2631
2632static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2633 unsigned long parent_rate)
2634{
2635 struct rt5682_priv *rt5682 =
2636 container_of(hw, struct rt5682_priv,
2637 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2638 struct snd_soc_component *component = rt5682->component;
2639 struct clk_hw *parent_hw;
2640 const char * const clk_name = clk_hw_get_name(hw);
2641 int pre_div;
2642 unsigned int clk_pll2_out;
2643
2644 if (!rt5682_clk_check(rt5682))
2645 return -EINVAL;
2646
2647
2648
2649
2650
2651
2652
2653
2654 parent_hw = clk_hw_get_parent(hw);
2655 if (!parent_hw)
2656 dev_warn(component->dev,
2657 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2658 CLK_PLL2_FIN);
2659
2660 if (parent_rate != CLK_PLL2_FIN)
2661 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2662 clk_name, CLK_PLL2_FIN);
2663
2664
2665
2666
2667
2668 clk_pll2_out = rate * 512;
2669 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2670 CLK_PLL2_FIN, clk_pll2_out);
2671
2672 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2673 clk_pll2_out, SND_SOC_CLOCK_IN);
2674
2675 rt5682->lrck[RT5682_AIF1] = rate;
2676
2677 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2678
2679 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2680 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2681 pre_div << RT5682_I2S_M_DIV_SFT |
2682 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2683
2684 return 0;
2685}
2686
2687static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2688 unsigned long parent_rate)
2689{
2690 struct rt5682_priv *rt5682 =
2691 container_of(hw, struct rt5682_priv,
2692 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2693 struct snd_soc_component *component = rt5682->component;
2694 unsigned int bclks_per_wclk;
2695
2696 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2697
2698 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2699 case RT5682_TDM_BCLK_MS1_256:
2700 return parent_rate * 256;
2701 case RT5682_TDM_BCLK_MS1_128:
2702 return parent_rate * 128;
2703 case RT5682_TDM_BCLK_MS1_64:
2704 return parent_rate * 64;
2705 case RT5682_TDM_BCLK_MS1_32:
2706 return parent_rate * 32;
2707 default:
2708 return 0;
2709 }
2710}
2711
2712static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2713 unsigned long parent_rate)
2714{
2715 unsigned long factor;
2716
2717 factor = rate / parent_rate;
2718 if (factor < 64)
2719 return 32;
2720 else if (factor < 128)
2721 return 64;
2722 else if (factor < 256)
2723 return 128;
2724 else
2725 return 256;
2726}
2727
2728static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2729 unsigned long *parent_rate)
2730{
2731 struct rt5682_priv *rt5682 =
2732 container_of(hw, struct rt5682_priv,
2733 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2734 unsigned long factor;
2735
2736 if (!*parent_rate || !rt5682_clk_check(rt5682))
2737 return -EINVAL;
2738
2739
2740
2741
2742
2743
2744
2745
2746 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2747
2748 return *parent_rate * factor;
2749}
2750
2751static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2752 unsigned long parent_rate)
2753{
2754 struct rt5682_priv *rt5682 =
2755 container_of(hw, struct rt5682_priv,
2756 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2757 struct snd_soc_component *component = rt5682->component;
2758 struct snd_soc_dai *dai;
2759 unsigned long factor;
2760
2761 if (!rt5682_clk_check(rt5682))
2762 return -EINVAL;
2763
2764 factor = rt5682_bclk_get_factor(rate, parent_rate);
2765
2766 for_each_component_dais(component, dai)
2767 if (dai->id == RT5682_AIF1)
2768 break;
2769 if (!dai) {
2770 dev_err(component->dev, "dai %d not found in component\n",
2771 RT5682_AIF1);
2772 return -ENODEV;
2773 }
2774
2775 return rt5682_set_bclk1_ratio(dai, factor);
2776}
2777
2778static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2779 [RT5682_DAI_WCLK_IDX] = {
2780 .prepare = rt5682_wclk_prepare,
2781 .unprepare = rt5682_wclk_unprepare,
2782 .recalc_rate = rt5682_wclk_recalc_rate,
2783 .round_rate = rt5682_wclk_round_rate,
2784 .set_rate = rt5682_wclk_set_rate,
2785 },
2786 [RT5682_DAI_BCLK_IDX] = {
2787 .recalc_rate = rt5682_bclk_recalc_rate,
2788 .round_rate = rt5682_bclk_round_rate,
2789 .set_rate = rt5682_bclk_set_rate,
2790 },
2791};
2792
2793static int rt5682_register_dai_clks(struct snd_soc_component *component)
2794{
2795 struct device *dev = component->dev;
2796 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2797 struct rt5682_platform_data *pdata = &rt5682->pdata;
2798 struct clk_hw *dai_clk_hw;
2799 int i, ret;
2800
2801 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2802 struct clk_init_data init = { };
2803
2804 dai_clk_hw = &rt5682->dai_clks_hw[i];
2805
2806 switch (i) {
2807 case RT5682_DAI_WCLK_IDX:
2808
2809 if (rt5682->mclk) {
2810 init.parent_data = &(struct clk_parent_data){
2811 .fw_name = "mclk",
2812 };
2813 init.num_parents = 1;
2814 }
2815 break;
2816 case RT5682_DAI_BCLK_IDX:
2817
2818 init.parent_hws = &(const struct clk_hw *){
2819 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]
2820 };
2821 init.num_parents = 1;
2822 break;
2823 default:
2824 dev_err(dev, "Invalid clock index\n");
2825 return -EINVAL;
2826 }
2827
2828 init.name = pdata->dai_clk_names[i];
2829 init.ops = &rt5682_dai_clk_ops[i];
2830 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2831 dai_clk_hw->init = &init;
2832
2833 ret = devm_clk_hw_register(dev, dai_clk_hw);
2834 if (ret) {
2835 dev_warn(dev, "Failed to register %s: %d\n",
2836 init.name, ret);
2837 return ret;
2838 }
2839
2840 if (dev->of_node) {
2841 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2842 dai_clk_hw);
2843 } else {
2844 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2845 init.name,
2846 dev_name(dev));
2847 if (ret)
2848 return ret;
2849 }
2850 }
2851
2852 return 0;
2853}
2854#endif
2855
2856static int rt5682_probe(struct snd_soc_component *component)
2857{
2858 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2859 struct sdw_slave *slave;
2860 unsigned long time;
2861 struct snd_soc_dapm_context *dapm = &component->dapm;
2862
2863#ifdef CONFIG_COMMON_CLK
2864 int ret;
2865#endif
2866 rt5682->component = component;
2867
2868 if (rt5682->is_sdw) {
2869 slave = rt5682->slave;
2870 time = wait_for_completion_timeout(
2871 &slave->initialization_complete,
2872 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2873 if (!time) {
2874 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2875 return -ETIMEDOUT;
2876 }
2877 } else {
2878#ifdef CONFIG_COMMON_CLK
2879
2880 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2881 if (IS_ERR(rt5682->mclk)) {
2882 if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2883 ret = PTR_ERR(rt5682->mclk);
2884 return ret;
2885 }
2886 rt5682->mclk = NULL;
2887 }
2888
2889
2890 ret = rt5682_register_dai_clks(component);
2891 if (ret)
2892 return ret;
2893
2894
2895 rt5682->lrck[RT5682_AIF1] = CLK_48;
2896#endif
2897 }
2898
2899 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2900 snd_soc_dapm_disable_pin(dapm, "Vref2");
2901 snd_soc_dapm_sync(dapm);
2902 return 0;
2903}
2904
2905static void rt5682_remove(struct snd_soc_component *component)
2906{
2907 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2908
2909 rt5682_reset(rt5682);
2910}
2911
2912#ifdef CONFIG_PM
2913static int rt5682_suspend(struct snd_soc_component *component)
2914{
2915 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2916 unsigned int val;
2917
2918 if (rt5682->is_sdw)
2919 return 0;
2920
2921 cancel_delayed_work_sync(&rt5682->jack_detect_work);
2922 cancel_delayed_work_sync(&rt5682->jd_check_work);
2923 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) {
2924 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2925 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2926 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
2927 val = snd_soc_component_read(component,
2928 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2929
2930 switch (val) {
2931 case 0x1:
2932 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2933 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2934 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2935 break;
2936 case 0x2:
2937 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2938 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2939 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2940 break;
2941 default:
2942 break;
2943 }
2944
2945
2946 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2947 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2948 RT5682_SAR_BUTDET_RST_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2949 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2950 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_BUTDET_RST_MASK,
2951 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV | RT5682_SAR_BUTDET_RST_NORMAL);
2952 }
2953
2954 regcache_cache_only(rt5682->regmap, true);
2955 regcache_mark_dirty(rt5682->regmap);
2956 return 0;
2957}
2958
2959static int rt5682_resume(struct snd_soc_component *component)
2960{
2961 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2962
2963 if (rt5682->is_sdw)
2964 return 0;
2965
2966 regcache_cache_only(rt5682->regmap, false);
2967 regcache_sync(rt5682->regmap);
2968
2969 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) {
2970 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2971 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
2972 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
2973 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2974 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2975 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
2976 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
2977 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
2978 }
2979
2980 mod_delayed_work(system_power_efficient_wq,
2981 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2982
2983 return 0;
2984}
2985#else
2986#define rt5682_suspend NULL
2987#define rt5682_resume NULL
2988#endif
2989
2990const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2991 .hw_params = rt5682_hw_params,
2992 .set_fmt = rt5682_set_dai_fmt,
2993 .set_tdm_slot = rt5682_set_tdm_slot,
2994 .set_bclk_ratio = rt5682_set_bclk1_ratio,
2995};
2996EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2997
2998const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2999 .hw_params = rt5682_hw_params,
3000 .set_fmt = rt5682_set_dai_fmt,
3001 .set_bclk_ratio = rt5682_set_bclk2_ratio,
3002};
3003EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3004
3005const struct snd_soc_component_driver rt5682_soc_component_dev = {
3006 .probe = rt5682_probe,
3007 .remove = rt5682_remove,
3008 .suspend = rt5682_suspend,
3009 .resume = rt5682_resume,
3010 .set_bias_level = rt5682_set_bias_level,
3011 .controls = rt5682_snd_controls,
3012 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3013 .dapm_widgets = rt5682_dapm_widgets,
3014 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3015 .dapm_routes = rt5682_dapm_routes,
3016 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3017 .set_sysclk = rt5682_set_component_sysclk,
3018 .set_pll = rt5682_set_component_pll,
3019 .set_jack = rt5682_set_jack_detect,
3020 .use_pmdown_time = 1,
3021 .endianness = 1,
3022 .non_legacy_dai_naming = 1,
3023};
3024EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3025
3026int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3027{
3028
3029 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3030 &rt5682->pdata.dmic1_data_pin);
3031 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3032 &rt5682->pdata.dmic1_clk_pin);
3033 device_property_read_u32(dev, "realtek,jd-src",
3034 &rt5682->pdata.jd_src);
3035 device_property_read_u32(dev, "realtek,btndet-delay",
3036 &rt5682->pdata.btndet_delay);
3037 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3038 &rt5682->pdata.dmic_clk_rate);
3039 device_property_read_u32(dev, "realtek,dmic-delay-ms",
3040 &rt5682->pdata.dmic_delay);
3041
3042 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3043 "realtek,ldo1-en-gpios", 0);
3044
3045 if (device_property_read_string_array(dev, "clock-output-names",
3046 rt5682->pdata.dai_clk_names,
3047 RT5682_DAI_NUM_CLKS) < 0)
3048 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3049 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3050 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3051
3052 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3053 "realtek,dmic-clk-driving-high");
3054
3055 return 0;
3056}
3057EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3058
3059void rt5682_calibrate(struct rt5682_priv *rt5682)
3060{
3061 int value, count;
3062
3063 mutex_lock(&rt5682->calibrate_mutex);
3064
3065 rt5682_reset(rt5682);
3066 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3067 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3068 usleep_range(15000, 20000);
3069 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3070 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3071 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3072 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3073 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3074 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3075 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3076 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3077 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3078 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3079 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3080 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3081 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3082 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3083 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3084
3085 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3086
3087 for (count = 0; count < 60; count++) {
3088 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3089 if (!(value & 0x8000))
3090 break;
3091
3092 usleep_range(10000, 10005);
3093 }
3094
3095 if (count >= 60)
3096 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3097
3098
3099 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3100 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3101 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3102 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3103 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3104 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3105 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3106 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3107
3108 mutex_unlock(&rt5682->calibrate_mutex);
3109}
3110EXPORT_SYMBOL_GPL(rt5682_calibrate);
3111
3112MODULE_DESCRIPTION("ASoC RT5682 driver");
3113MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3114MODULE_LICENSE("GPL v2");
3115
