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15#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/of_device.h>
25#include <linux/of_gpio.h>
26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/gpio/consumer.h>
29#include <linux/slab.h>
30#include <linux/workqueue.h>
31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
37#include <sound/tlv.h>
38
39#include <sound/sta32x.h>
40#include "sta32x.h"
41
42#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
43 SNDRV_PCM_RATE_44100 | \
44 SNDRV_PCM_RATE_48000 | \
45 SNDRV_PCM_RATE_88200 | \
46 SNDRV_PCM_RATE_96000 | \
47 SNDRV_PCM_RATE_176400 | \
48 SNDRV_PCM_RATE_192000)
49
50#define STA32X_FORMATS \
51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
52 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
53 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
54 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
56 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
57
58
59static const struct reg_default sta32x_regs[] = {
60 { 0x0, 0x63 },
61 { 0x1, 0x80 },
62 { 0x2, 0xc2 },
63 { 0x3, 0x40 },
64 { 0x4, 0xc2 },
65 { 0x5, 0x5c },
66 { 0x6, 0x10 },
67 { 0x7, 0xff },
68 { 0x8, 0x60 },
69 { 0x9, 0x60 },
70 { 0xa, 0x60 },
71 { 0xb, 0x80 },
72 { 0xc, 0x00 },
73 { 0xd, 0x00 },
74 { 0xe, 0x00 },
75 { 0xf, 0x40 },
76 { 0x10, 0x80 },
77 { 0x11, 0x77 },
78 { 0x12, 0x6a },
79 { 0x13, 0x69 },
80 { 0x14, 0x6a },
81 { 0x15, 0x69 },
82 { 0x16, 0x00 },
83 { 0x17, 0x00 },
84 { 0x18, 0x00 },
85 { 0x19, 0x00 },
86 { 0x1a, 0x00 },
87 { 0x1b, 0x00 },
88 { 0x1c, 0x00 },
89 { 0x1d, 0x00 },
90 { 0x1e, 0x00 },
91 { 0x1f, 0x00 },
92 { 0x20, 0x00 },
93 { 0x21, 0x00 },
94 { 0x22, 0x00 },
95 { 0x23, 0x00 },
96 { 0x24, 0x00 },
97 { 0x25, 0x00 },
98 { 0x26, 0x00 },
99 { 0x27, 0x2d },
100 { 0x28, 0xc0 },
101 { 0x2b, 0x00 },
102 { 0x2c, 0x0c },
103};
104
105static const struct regmap_range sta32x_write_regs_range[] = {
106 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
107};
108
109static const struct regmap_range sta32x_read_regs_range[] = {
110 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
111};
112
113static const struct regmap_range sta32x_volatile_regs_range[] = {
114 regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
115};
116
117static const struct regmap_access_table sta32x_write_regs = {
118 .yes_ranges = sta32x_write_regs_range,
119 .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
120};
121
122static const struct regmap_access_table sta32x_read_regs = {
123 .yes_ranges = sta32x_read_regs_range,
124 .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
125};
126
127static const struct regmap_access_table sta32x_volatile_regs = {
128 .yes_ranges = sta32x_volatile_regs_range,
129 .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
130};
131
132
133static const char *sta32x_supply_names[] = {
134 "Vdda",
135 "Vdd3",
136 "Vcc"
137};
138
139
140struct sta32x_priv {
141 struct regmap *regmap;
142 struct clk *xti_clk;
143 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
144 struct snd_soc_component *component;
145 struct sta32x_platform_data *pdata;
146
147 unsigned int mclk;
148 unsigned int format;
149
150 u32 coef_shadow[STA32X_COEF_COUNT];
151 struct delayed_work watchdog_work;
152 int shutdown;
153 struct gpio_desc *gpiod_nreset;
154 struct mutex coeff_lock;
155};
156
157static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
158static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
159static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
160
161static const char *sta32x_drc_ac[] = {
162 "Anti-Clipping", "Dynamic Range Compression" };
163static const char *sta32x_auto_eq_mode[] = {
164 "User", "Preset", "Loudness" };
165static const char *sta32x_auto_gc_mode[] = {
166 "User", "AC no clipping", "AC limited clipping (10%)",
167 "DRC nighttime listening mode" };
168static const char *sta32x_auto_xo_mode[] = {
169 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
170 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
171static const char *sta32x_preset_eq_mode[] = {
172 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
173 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
174 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
175 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
176 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
177 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
178static const char *sta32x_limiter_select[] = {
179 "Limiter Disabled", "Limiter #1", "Limiter #2" };
180static const char *sta32x_limiter_attack_rate[] = {
181 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
182 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
183 "0.0645", "0.0564", "0.0501", "0.0451" };
184static const char *sta32x_limiter_release_rate[] = {
185 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
186 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
187 "0.0134", "0.0117", "0.0110", "0.0104" };
188static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
189 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
190 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
191);
192
193static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
194 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
195 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
196 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
197 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
198 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
199);
200
201static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
202 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
203 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
204 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
205);
206
207static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
208 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
209 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
210 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
211 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
212 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
213);
214
215static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
216 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
217 sta32x_drc_ac);
218static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
219 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
220 sta32x_auto_eq_mode);
221static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
222 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
223 sta32x_auto_gc_mode);
224static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
225 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
226 sta32x_auto_xo_mode);
227static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
228 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
229 sta32x_preset_eq_mode);
230static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
231 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
232 sta32x_limiter_select);
233static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
234 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
235 sta32x_limiter_select);
236static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
237 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
238 sta32x_limiter_select);
239static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
240 STA32X_L1AR, STA32X_LxA_SHIFT,
241 sta32x_limiter_attack_rate);
242static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
243 STA32X_L2AR, STA32X_LxA_SHIFT,
244 sta32x_limiter_attack_rate);
245static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
246 STA32X_L1AR, STA32X_LxR_SHIFT,
247 sta32x_limiter_release_rate);
248static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
249 STA32X_L2AR, STA32X_LxR_SHIFT,
250 sta32x_limiter_release_rate);
251
252
253
254
255
256
257
258
259static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
260 struct snd_ctl_elem_info *uinfo)
261{
262 int numcoef = kcontrol->private_value >> 16;
263 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
264 uinfo->count = 3 * numcoef;
265 return 0;
266}
267
268static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
269 struct snd_ctl_elem_value *ucontrol)
270{
271 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
272 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
273 int numcoef = kcontrol->private_value >> 16;
274 int index = kcontrol->private_value & 0xffff;
275 unsigned int cfud, val;
276 int i, ret = 0;
277
278 mutex_lock(&sta32x->coeff_lock);
279
280
281 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
282 cfud &= 0xf0;
283
284
285
286
287 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
288
289 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
290 if (numcoef == 1) {
291 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
292 } else if (numcoef == 5) {
293 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
294 } else {
295 ret = -EINVAL;
296 goto exit_unlock;
297 }
298
299 for (i = 0; i < 3 * numcoef; i++) {
300 regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
301 ucontrol->value.bytes.data[i] = val;
302 }
303
304exit_unlock:
305 mutex_unlock(&sta32x->coeff_lock);
306
307 return ret;
308}
309
310static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
311 struct snd_ctl_elem_value *ucontrol)
312{
313 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
314 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
315 int numcoef = kcontrol->private_value >> 16;
316 int index = kcontrol->private_value & 0xffff;
317 unsigned int cfud;
318 int i;
319
320
321 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
322 cfud &= 0xf0;
323
324
325
326
327 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
328
329 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
330 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
331 sta32x->coef_shadow[index + i] =
332 (ucontrol->value.bytes.data[3 * i] << 16)
333 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
334 | (ucontrol->value.bytes.data[3 * i + 2]);
335 for (i = 0; i < 3 * numcoef; i++)
336 regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
337 ucontrol->value.bytes.data[i]);
338 if (numcoef == 1)
339 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
340 else if (numcoef == 5)
341 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
342 else
343 return -EINVAL;
344
345 return 0;
346}
347
348static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
349{
350 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
351 unsigned int cfud;
352 int i;
353
354
355 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
356 cfud &= 0xf0;
357
358 for (i = 0; i < STA32X_COEF_COUNT; i++) {
359 regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
360 regmap_write(sta32x->regmap, STA32X_B1CF1,
361 (sta32x->coef_shadow[i] >> 16) & 0xff);
362 regmap_write(sta32x->regmap, STA32X_B1CF2,
363 (sta32x->coef_shadow[i] >> 8) & 0xff);
364 regmap_write(sta32x->regmap, STA32X_B1CF3,
365 (sta32x->coef_shadow[i]) & 0xff);
366
367
368
369
370 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
371 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
372 }
373 return 0;
374}
375
376static int sta32x_cache_sync(struct snd_soc_component *component)
377{
378 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
379 unsigned int mute;
380 int rc;
381
382
383 regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
384 regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
385 sta32x_sync_coef_shadow(component);
386 rc = regcache_sync(sta32x->regmap);
387 regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
388 return rc;
389}
390
391
392static void sta32x_watchdog(struct work_struct *work)
393{
394 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
395 watchdog_work.work);
396 struct snd_soc_component *component = sta32x->component;
397 unsigned int confa, confa_cached;
398
399
400 confa_cached = snd_soc_component_read(component, STA32X_CONFA);
401 regcache_cache_bypass(sta32x->regmap, true);
402 confa = snd_soc_component_read(component, STA32X_CONFA);
403 regcache_cache_bypass(sta32x->regmap, false);
404 if (confa != confa_cached) {
405 regcache_mark_dirty(sta32x->regmap);
406 sta32x_cache_sync(component);
407 }
408
409 if (!sta32x->shutdown)
410 queue_delayed_work(system_power_efficient_wq,
411 &sta32x->watchdog_work,
412 round_jiffies_relative(HZ));
413}
414
415static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
416{
417 if (sta32x->pdata->needs_esd_watchdog) {
418 sta32x->shutdown = 0;
419 queue_delayed_work(system_power_efficient_wq,
420 &sta32x->watchdog_work,
421 round_jiffies_relative(HZ));
422 }
423}
424
425static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
426{
427 if (sta32x->pdata->needs_esd_watchdog) {
428 sta32x->shutdown = 1;
429 cancel_delayed_work_sync(&sta32x->watchdog_work);
430 }
431}
432
433#define SINGLE_COEF(xname, index) \
434{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
435 .info = sta32x_coefficient_info, \
436 .get = sta32x_coefficient_get,\
437 .put = sta32x_coefficient_put, \
438 .private_value = index | (1 << 16) }
439
440#define BIQUAD_COEFS(xname, index) \
441{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
442 .info = sta32x_coefficient_info, \
443 .get = sta32x_coefficient_get,\
444 .put = sta32x_coefficient_put, \
445 .private_value = index | (5 << 16) }
446
447static const struct snd_kcontrol_new sta32x_snd_controls[] = {
448SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
449SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
450SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
451SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
452SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
453SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
454SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
455SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
456SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
457SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
458SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
459SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
460SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
461SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
462SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
463SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
464SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
465SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
466SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
467SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
468SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
469SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
470SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
471SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
472SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
473SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
474SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
475SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
476SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
477SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
478SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
479SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
480SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
481SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
482
483
484
485
486SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
487 16, 0, sta32x_limiter_ac_attack_tlv),
488SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
489 16, 0, sta32x_limiter_ac_attack_tlv),
490SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
491 16, 0, sta32x_limiter_ac_release_tlv),
492SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
493 16, 0, sta32x_limiter_ac_release_tlv),
494SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
495 16, 0, sta32x_limiter_drc_attack_tlv),
496SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
497 16, 0, sta32x_limiter_drc_attack_tlv),
498SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
499 16, 0, sta32x_limiter_drc_release_tlv),
500SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
501 16, 0, sta32x_limiter_drc_release_tlv),
502
503BIQUAD_COEFS("Ch1 - Biquad 1", 0),
504BIQUAD_COEFS("Ch1 - Biquad 2", 5),
505BIQUAD_COEFS("Ch1 - Biquad 3", 10),
506BIQUAD_COEFS("Ch1 - Biquad 4", 15),
507BIQUAD_COEFS("Ch2 - Biquad 1", 20),
508BIQUAD_COEFS("Ch2 - Biquad 2", 25),
509BIQUAD_COEFS("Ch2 - Biquad 3", 30),
510BIQUAD_COEFS("Ch2 - Biquad 4", 35),
511BIQUAD_COEFS("High-pass", 40),
512BIQUAD_COEFS("Low-pass", 45),
513SINGLE_COEF("Ch1 - Prescale", 50),
514SINGLE_COEF("Ch2 - Prescale", 51),
515SINGLE_COEF("Ch1 - Postscale", 52),
516SINGLE_COEF("Ch2 - Postscale", 53),
517SINGLE_COEF("Ch3 - Postscale", 54),
518SINGLE_COEF("Thermal warning - Postscale", 55),
519SINGLE_COEF("Ch1 - Mix 1", 56),
520SINGLE_COEF("Ch1 - Mix 2", 57),
521SINGLE_COEF("Ch2 - Mix 1", 58),
522SINGLE_COEF("Ch2 - Mix 2", 59),
523SINGLE_COEF("Ch3 - Mix 1", 60),
524SINGLE_COEF("Ch3 - Mix 2", 61),
525};
526
527static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
528SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
529SND_SOC_DAPM_OUTPUT("LEFT"),
530SND_SOC_DAPM_OUTPUT("RIGHT"),
531SND_SOC_DAPM_OUTPUT("SUB"),
532};
533
534static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
535 { "LEFT", NULL, "DAC" },
536 { "RIGHT", NULL, "DAC" },
537 { "SUB", NULL, "DAC" },
538};
539
540
541static struct {
542 int fs;
543 int ir;
544} interpolation_ratios[] = {
545 { 32000, 0 },
546 { 44100, 0 },
547 { 48000, 0 },
548 { 88200, 1 },
549 { 96000, 1 },
550 { 176400, 2 },
551 { 192000, 2 },
552};
553
554
555static int mcs_ratio_table[3][7] = {
556 { 768, 512, 384, 256, 128, 576, 0 },
557 { 384, 256, 192, 128, 64, 0 },
558 { 384, 256, 192, 128, 64, 0 },
559};
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
581 int clk_id, unsigned int freq, int dir)
582{
583 struct snd_soc_component *component = codec_dai->component;
584 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
585
586 dev_dbg(component->dev, "mclk=%u\n", freq);
587 sta32x->mclk = freq;
588
589 return 0;
590}
591
592
593
594
595
596
597
598
599
600static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
601 unsigned int fmt)
602{
603 struct snd_soc_component *component = codec_dai->component;
604 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
605 u8 confb = 0;
606
607 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
608 case SND_SOC_DAIFMT_CBS_CFS:
609 break;
610 default:
611 return -EINVAL;
612 }
613
614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
615 case SND_SOC_DAIFMT_I2S:
616 case SND_SOC_DAIFMT_RIGHT_J:
617 case SND_SOC_DAIFMT_LEFT_J:
618 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
625 case SND_SOC_DAIFMT_NB_NF:
626 confb |= STA32X_CONFB_C2IM;
627 break;
628 case SND_SOC_DAIFMT_NB_IF:
629 confb |= STA32X_CONFB_C1IM;
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
636 STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
637}
638
639
640
641
642
643
644
645
646
647
648static int sta32x_hw_params(struct snd_pcm_substream *substream,
649 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai)
651{
652 struct snd_soc_component *component = dai->component;
653 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
654 int i, mcs = -EINVAL, ir = -EINVAL;
655 unsigned int confa, confb;
656 unsigned int rate, ratio;
657 int ret;
658
659 if (!sta32x->mclk) {
660 dev_err(component->dev,
661 "sta32x->mclk is unset. Unable to determine ratio\n");
662 return -EIO;
663 }
664
665 rate = params_rate(params);
666 ratio = sta32x->mclk / rate;
667 dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
668
669 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
670 if (interpolation_ratios[i].fs == rate) {
671 ir = interpolation_ratios[i].ir;
672 break;
673 }
674 }
675
676 if (ir < 0) {
677 dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
678 return -EINVAL;
679 }
680
681 for (i = 0; i < 6; i++) {
682 if (mcs_ratio_table[ir][i] == ratio) {
683 mcs = i;
684 break;
685 }
686 }
687
688 if (mcs < 0) {
689 dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
690 return -EINVAL;
691 }
692
693 confa = (ir << STA32X_CONFA_IR_SHIFT) |
694 (mcs << STA32X_CONFA_MCS_SHIFT);
695 confb = 0;
696
697 switch (params_width(params)) {
698 case 24:
699 dev_dbg(component->dev, "24bit\n");
700 fallthrough;
701 case 32:
702 dev_dbg(component->dev, "24bit or 32bit\n");
703 switch (sta32x->format) {
704 case SND_SOC_DAIFMT_I2S:
705 confb |= 0x0;
706 break;
707 case SND_SOC_DAIFMT_LEFT_J:
708 confb |= 0x1;
709 break;
710 case SND_SOC_DAIFMT_RIGHT_J:
711 confb |= 0x2;
712 break;
713 }
714
715 break;
716 case 20:
717 dev_dbg(component->dev, "20bit\n");
718 switch (sta32x->format) {
719 case SND_SOC_DAIFMT_I2S:
720 confb |= 0x4;
721 break;
722 case SND_SOC_DAIFMT_LEFT_J:
723 confb |= 0x5;
724 break;
725 case SND_SOC_DAIFMT_RIGHT_J:
726 confb |= 0x6;
727 break;
728 }
729
730 break;
731 case 18:
732 dev_dbg(component->dev, "18bit\n");
733 switch (sta32x->format) {
734 case SND_SOC_DAIFMT_I2S:
735 confb |= 0x8;
736 break;
737 case SND_SOC_DAIFMT_LEFT_J:
738 confb |= 0x9;
739 break;
740 case SND_SOC_DAIFMT_RIGHT_J:
741 confb |= 0xa;
742 break;
743 }
744
745 break;
746 case 16:
747 dev_dbg(component->dev, "16bit\n");
748 switch (sta32x->format) {
749 case SND_SOC_DAIFMT_I2S:
750 confb |= 0x0;
751 break;
752 case SND_SOC_DAIFMT_LEFT_J:
753 confb |= 0xd;
754 break;
755 case SND_SOC_DAIFMT_RIGHT_J:
756 confb |= 0xe;
757 break;
758 }
759
760 break;
761 default:
762 return -EINVAL;
763 }
764
765 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
766 STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
767 confa);
768 if (ret < 0)
769 return ret;
770
771 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
772 STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
773 confb);
774 if (ret < 0)
775 return ret;
776
777 return 0;
778}
779
780static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
781{
782 if (sta32x->gpiod_nreset) {
783 gpiod_set_value(sta32x->gpiod_nreset, 0);
784 mdelay(1);
785 gpiod_set_value(sta32x->gpiod_nreset, 1);
786 mdelay(1);
787 }
788
789 return 0;
790}
791
792
793
794
795
796
797
798
799
800
801static int sta32x_set_bias_level(struct snd_soc_component *component,
802 enum snd_soc_bias_level level)
803{
804 int ret;
805 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
806
807 dev_dbg(component->dev, "level = %d\n", level);
808 switch (level) {
809 case SND_SOC_BIAS_ON:
810 break;
811
812 case SND_SOC_BIAS_PREPARE:
813
814 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
815 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
816 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
817 break;
818
819 case SND_SOC_BIAS_STANDBY:
820 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
821 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
822 sta32x->supplies);
823 if (ret != 0) {
824 dev_err(component->dev,
825 "Failed to enable supplies: %d\n", ret);
826 return ret;
827 }
828
829 sta32x_startup_sequence(sta32x);
830 sta32x_cache_sync(component);
831 sta32x_watchdog_start(sta32x);
832 }
833
834
835 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
836 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
837 0);
838
839 break;
840
841 case SND_SOC_BIAS_OFF:
842
843 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
844 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
845 msleep(300);
846 sta32x_watchdog_stop(sta32x);
847
848 gpiod_set_value(sta32x->gpiod_nreset, 0);
849
850 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
851 sta32x->supplies);
852 break;
853 }
854 return 0;
855}
856
857static const struct snd_soc_dai_ops sta32x_dai_ops = {
858 .hw_params = sta32x_hw_params,
859 .set_sysclk = sta32x_set_dai_sysclk,
860 .set_fmt = sta32x_set_dai_fmt,
861};
862
863static struct snd_soc_dai_driver sta32x_dai = {
864 .name = "sta32x-hifi",
865 .playback = {
866 .stream_name = "Playback",
867 .channels_min = 2,
868 .channels_max = 2,
869 .rates = STA32X_RATES,
870 .formats = STA32X_FORMATS,
871 },
872 .ops = &sta32x_dai_ops,
873};
874
875static int sta32x_probe(struct snd_soc_component *component)
876{
877 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
878 struct sta32x_platform_data *pdata = sta32x->pdata;
879 int i, ret = 0, thermal = 0;
880
881 sta32x->component = component;
882
883 if (sta32x->xti_clk) {
884 ret = clk_prepare_enable(sta32x->xti_clk);
885 if (ret != 0) {
886 dev_err(component->dev,
887 "Failed to enable clock: %d\n", ret);
888 return ret;
889 }
890 }
891
892 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
893 sta32x->supplies);
894 if (ret != 0) {
895 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
896 goto err_clk_disable_unprepare;
897 }
898
899 ret = sta32x_startup_sequence(sta32x);
900 if (ret < 0) {
901 dev_err(component->dev, "Failed to startup device\n");
902 goto err_regulator_bulk_disable;
903 }
904
905
906 if (!pdata->thermal_warning_recovery)
907 thermal |= STA32X_CONFA_TWAB;
908 if (!pdata->thermal_warning_adjustment)
909 thermal |= STA32X_CONFA_TWRB;
910 if (!pdata->fault_detect_recovery)
911 thermal |= STA32X_CONFA_FDRB;
912 regmap_update_bits(sta32x->regmap, STA32X_CONFA,
913 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
914 STA32X_CONFA_FDRB,
915 thermal);
916
917
918 regmap_update_bits(sta32x->regmap, STA32X_CONFC,
919 STA32X_CONFC_CSZ_MASK,
920 pdata->drop_compensation_ns
921 << STA32X_CONFC_CSZ_SHIFT);
922
923
924 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
925 STA32X_CONFE_MPCV,
926 pdata->max_power_use_mpcc ?
927 STA32X_CONFE_MPCV : 0);
928 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
929 STA32X_CONFE_MPC,
930 pdata->max_power_correction ?
931 STA32X_CONFE_MPC : 0);
932 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
933 STA32X_CONFE_AME,
934 pdata->am_reduction_mode ?
935 STA32X_CONFE_AME : 0);
936 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
937 STA32X_CONFE_PWMS,
938 pdata->odd_pwm_speed_mode ?
939 STA32X_CONFE_PWMS : 0);
940
941
942 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
943 STA32X_CONFF_IDE,
944 pdata->invalid_input_detect_mute ?
945 STA32X_CONFF_IDE : 0);
946
947
948 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
949 STA32X_CONFF_OCFG_MASK,
950 pdata->output_conf
951 << STA32X_CONFF_OCFG_SHIFT);
952
953
954 regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
955 STA32X_CxCFG_OM_MASK,
956 pdata->ch1_output_mapping
957 << STA32X_CxCFG_OM_SHIFT);
958 regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
959 STA32X_CxCFG_OM_MASK,
960 pdata->ch2_output_mapping
961 << STA32X_CxCFG_OM_SHIFT);
962 regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
963 STA32X_CxCFG_OM_MASK,
964 pdata->ch3_output_mapping
965 << STA32X_CxCFG_OM_SHIFT);
966
967
968 for (i = 4; i <= 49; i += 5)
969 sta32x->coef_shadow[i] = 0x400000;
970 for (i = 50; i <= 54; i++)
971 sta32x->coef_shadow[i] = 0x7fffff;
972 sta32x->coef_shadow[55] = 0x5a9df7;
973 sta32x->coef_shadow[56] = 0x7fffff;
974 sta32x->coef_shadow[59] = 0x7fffff;
975 sta32x->coef_shadow[60] = 0x400000;
976 sta32x->coef_shadow[61] = 0x400000;
977
978 if (sta32x->pdata->needs_esd_watchdog)
979 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
980
981 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
982
983 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
984
985 return 0;
986
987err_regulator_bulk_disable:
988 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
989err_clk_disable_unprepare:
990 if (sta32x->xti_clk)
991 clk_disable_unprepare(sta32x->xti_clk);
992 return ret;
993}
994
995static void sta32x_remove(struct snd_soc_component *component)
996{
997 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
998
999 sta32x_watchdog_stop(sta32x);
1000 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
1001
1002 if (sta32x->xti_clk)
1003 clk_disable_unprepare(sta32x->xti_clk);
1004}
1005
1006static const struct snd_soc_component_driver sta32x_component = {
1007 .probe = sta32x_probe,
1008 .remove = sta32x_remove,
1009 .set_bias_level = sta32x_set_bias_level,
1010 .controls = sta32x_snd_controls,
1011 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
1012 .dapm_widgets = sta32x_dapm_widgets,
1013 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
1014 .dapm_routes = sta32x_dapm_routes,
1015 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
1016 .suspend_bias_off = 1,
1017 .idle_bias_on = 1,
1018 .use_pmdown_time = 1,
1019 .endianness = 1,
1020 .non_legacy_dai_naming = 1,
1021};
1022
1023static const struct regmap_config sta32x_regmap = {
1024 .reg_bits = 8,
1025 .val_bits = 8,
1026 .max_register = STA32X_FDRC2,
1027 .reg_defaults = sta32x_regs,
1028 .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
1029 .cache_type = REGCACHE_RBTREE,
1030 .wr_table = &sta32x_write_regs,
1031 .rd_table = &sta32x_read_regs,
1032 .volatile_table = &sta32x_volatile_regs,
1033};
1034
1035#ifdef CONFIG_OF
1036static const struct of_device_id st32x_dt_ids[] = {
1037 { .compatible = "st,sta32x", },
1038 { }
1039};
1040MODULE_DEVICE_TABLE(of, st32x_dt_ids);
1041
1042static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
1043{
1044 struct device_node *np = dev->of_node;
1045 struct sta32x_platform_data *pdata;
1046 u16 tmp;
1047
1048 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1049 if (!pdata)
1050 return -ENOMEM;
1051
1052 of_property_read_u8(np, "st,output-conf",
1053 &pdata->output_conf);
1054 of_property_read_u8(np, "st,ch1-output-mapping",
1055 &pdata->ch1_output_mapping);
1056 of_property_read_u8(np, "st,ch2-output-mapping",
1057 &pdata->ch2_output_mapping);
1058 of_property_read_u8(np, "st,ch3-output-mapping",
1059 &pdata->ch3_output_mapping);
1060
1061 if (of_get_property(np, "st,fault-detect-recovery", NULL))
1062 pdata->fault_detect_recovery = 1;
1063 if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1064 pdata->thermal_warning_recovery = 1;
1065 if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1066 pdata->thermal_warning_adjustment = 1;
1067 if (of_get_property(np, "st,needs_esd_watchdog", NULL))
1068 pdata->needs_esd_watchdog = 1;
1069
1070 tmp = 140;
1071 of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1072 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1073
1074
1075 if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1076 pdata->max_power_use_mpcc = 1;
1077
1078 if (of_get_property(np, "st,max-power-correction", NULL))
1079 pdata->max_power_correction = 1;
1080
1081 if (of_get_property(np, "st,am-reduction-mode", NULL))
1082 pdata->am_reduction_mode = 1;
1083
1084 if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1085 pdata->odd_pwm_speed_mode = 1;
1086
1087
1088 if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1089 pdata->invalid_input_detect_mute = 1;
1090
1091 sta32x->pdata = pdata;
1092
1093 return 0;
1094}
1095#endif
1096
1097static int sta32x_i2c_probe(struct i2c_client *i2c,
1098 const struct i2c_device_id *id)
1099{
1100 struct device *dev = &i2c->dev;
1101 struct sta32x_priv *sta32x;
1102 int ret, i;
1103
1104 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1105 GFP_KERNEL);
1106 if (!sta32x)
1107 return -ENOMEM;
1108
1109 mutex_init(&sta32x->coeff_lock);
1110 sta32x->pdata = dev_get_platdata(dev);
1111
1112#ifdef CONFIG_OF
1113 if (dev->of_node) {
1114 ret = sta32x_probe_dt(dev, sta32x);
1115 if (ret < 0)
1116 return ret;
1117 }
1118#endif
1119
1120
1121 sta32x->xti_clk = devm_clk_get(dev, "xti");
1122 if (IS_ERR(sta32x->xti_clk)) {
1123 ret = PTR_ERR(sta32x->xti_clk);
1124
1125 if (ret == -EPROBE_DEFER)
1126 return ret;
1127
1128 sta32x->xti_clk = NULL;
1129 }
1130
1131
1132 sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1133 GPIOD_OUT_LOW);
1134 if (IS_ERR(sta32x->gpiod_nreset))
1135 return PTR_ERR(sta32x->gpiod_nreset);
1136
1137
1138 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1139 sta32x->supplies[i].supply = sta32x_supply_names[i];
1140
1141 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1142 sta32x->supplies);
1143 if (ret != 0) {
1144 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1145 return ret;
1146 }
1147
1148 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1149 if (IS_ERR(sta32x->regmap)) {
1150 ret = PTR_ERR(sta32x->regmap);
1151 dev_err(dev, "Failed to init regmap: %d\n", ret);
1152 return ret;
1153 }
1154
1155 i2c_set_clientdata(i2c, sta32x);
1156
1157 ret = devm_snd_soc_register_component(dev, &sta32x_component,
1158 &sta32x_dai, 1);
1159 if (ret < 0)
1160 dev_err(dev, "Failed to register component (%d)\n", ret);
1161
1162 return ret;
1163}
1164
1165static const struct i2c_device_id sta32x_i2c_id[] = {
1166 { "sta326", 0 },
1167 { "sta328", 0 },
1168 { "sta329", 0 },
1169 { }
1170};
1171MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1172
1173static struct i2c_driver sta32x_i2c_driver = {
1174 .driver = {
1175 .name = "sta32x",
1176 .of_match_table = of_match_ptr(st32x_dt_ids),
1177 },
1178 .probe = sta32x_i2c_probe,
1179 .id_table = sta32x_i2c_id,
1180};
1181
1182module_i2c_driver(sta32x_i2c_driver);
1183
1184MODULE_DESCRIPTION("ASoC STA32X driver");
1185MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1186MODULE_LICENSE("GPL");
1187
