LXR linux/sound/soc/codecs/tlv320aic26.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Texas Instruments TLV320AIC26 low power audio CODEC
   4 * register definitions
   5 *
   6 * Copyright (C) 2008 Secret Lab Technologies Ltd.
   7 */
   8
   9#ifndef _TLV320AIC16_H_
  10#define _TLV320AIC16_H_
  11
  12/* AIC26 Registers */
  13#define AIC26_PAGE_ADDR(page, offset)   ((page << 11) | offset << 5)
  14
  15/* Page 0: Auxiliary data registers */
  16#define AIC26_REG_BAT1                  AIC26_PAGE_ADDR(0, 0x05)
  17#define AIC26_REG_BAT2                  AIC26_PAGE_ADDR(0, 0x06)
  18#define AIC26_REG_AUX                   AIC26_PAGE_ADDR(0, 0x07)
  19#define AIC26_REG_TEMP1                 AIC26_PAGE_ADDR(0, 0x09)
  20#define AIC26_REG_TEMP2                 AIC26_PAGE_ADDR(0, 0x0A)
  21
  22/* Page 1: Auxiliary control registers */
  23#define AIC26_REG_AUX_ADC               AIC26_PAGE_ADDR(1, 0x00)
  24#define AIC26_REG_STATUS                AIC26_PAGE_ADDR(1, 0x01)
  25#define AIC26_REG_REFERENCE             AIC26_PAGE_ADDR(1, 0x03)
  26#define AIC26_REG_RESET                 AIC26_PAGE_ADDR(1, 0x04)
  27
  28/* Page 2: Audio control registers */
  29#define AIC26_REG_AUDIO_CTRL1           AIC26_PAGE_ADDR(2, 0x00)
  30#define AIC26_REG_ADC_GAIN              AIC26_PAGE_ADDR(2, 0x01)
  31#define AIC26_REG_DAC_GAIN              AIC26_PAGE_ADDR(2, 0x02)
  32#define AIC26_REG_SIDETONE              AIC26_PAGE_ADDR(2, 0x03)
  33#define AIC26_REG_AUDIO_CTRL2           AIC26_PAGE_ADDR(2, 0x04)
  34#define AIC26_REG_POWER_CTRL            AIC26_PAGE_ADDR(2, 0x05)
  35#define AIC26_REG_AUDIO_CTRL3           AIC26_PAGE_ADDR(2, 0x06)
  36
  37#define AIC26_REG_FILTER_COEFF_L_N0     AIC26_PAGE_ADDR(2, 0x07)
  38#define AIC26_REG_FILTER_COEFF_L_N1     AIC26_PAGE_ADDR(2, 0x08)
  39#define AIC26_REG_FILTER_COEFF_L_N2     AIC26_PAGE_ADDR(2, 0x09)
  40#define AIC26_REG_FILTER_COEFF_L_N3     AIC26_PAGE_ADDR(2, 0x0A)
  41#define AIC26_REG_FILTER_COEFF_L_N4     AIC26_PAGE_ADDR(2, 0x0B)
  42#define AIC26_REG_FILTER_COEFF_L_N5     AIC26_PAGE_ADDR(2, 0x0C)
  43#define AIC26_REG_FILTER_COEFF_L_D1     AIC26_PAGE_ADDR(2, 0x0D)
  44#define AIC26_REG_FILTER_COEFF_L_D2     AIC26_PAGE_ADDR(2, 0x0E)
  45#define AIC26_REG_FILTER_COEFF_L_D4     AIC26_PAGE_ADDR(2, 0x0F)
  46#define AIC26_REG_FILTER_COEFF_L_D5     AIC26_PAGE_ADDR(2, 0x10)
  47#define AIC26_REG_FILTER_COEFF_R_N0     AIC26_PAGE_ADDR(2, 0x11)
  48#define AIC26_REG_FILTER_COEFF_R_N1     AIC26_PAGE_ADDR(2, 0x12)
  49#define AIC26_REG_FILTER_COEFF_R_N2     AIC26_PAGE_ADDR(2, 0x13)
  50#define AIC26_REG_FILTER_COEFF_R_N3     AIC26_PAGE_ADDR(2, 0x14)
  51#define AIC26_REG_FILTER_COEFF_R_N4     AIC26_PAGE_ADDR(2, 0x15)
  52#define AIC26_REG_FILTER_COEFF_R_N5     AIC26_PAGE_ADDR(2, 0x16)
  53#define AIC26_REG_FILTER_COEFF_R_D1     AIC26_PAGE_ADDR(2, 0x17)
  54#define AIC26_REG_FILTER_COEFF_R_D2     AIC26_PAGE_ADDR(2, 0x18)
  55#define AIC26_REG_FILTER_COEFF_R_D4     AIC26_PAGE_ADDR(2, 0x19)
  56#define AIC26_REG_FILTER_COEFF_R_D5     AIC26_PAGE_ADDR(2, 0x1A)
  57
  58#define AIC26_REG_PLL_PROG1             AIC26_PAGE_ADDR(2, 0x1B)
  59#define AIC26_REG_PLL_PROG2             AIC26_PAGE_ADDR(2, 0x1C)
  60#define AIC26_REG_AUDIO_CTRL4           AIC26_PAGE_ADDR(2, 0x1D)
  61#define AIC26_REG_AUDIO_CTRL5           AIC26_PAGE_ADDR(2, 0x1E)
  62
  63/* fsref dividers; used in register 'Audio Control 1' */
  64enum aic26_divisors {
  65        AIC26_DIV_1     = 0,
  66        AIC26_DIV_1_5   = 1,
  67        AIC26_DIV_2     = 2,
  68        AIC26_DIV_3     = 3,
  69        AIC26_DIV_4     = 4,
  70        AIC26_DIV_5     = 5,
  71        AIC26_DIV_5_5   = 6,
  72        AIC26_DIV_6     = 7,
  73};
  74
  75/* Digital data format */
  76enum aic26_datfm {
  77        AIC26_DATFM_I2S         = 0 << 8,
  78        AIC26_DATFM_DSP         = 1 << 8,
  79        AIC26_DATFM_RIGHTJ      = 2 << 8, /* right justified */
  80        AIC26_DATFM_LEFTJ       = 3 << 8, /* left justified */
  81};
  82
  83/* Sample word length in bits; used in register 'Audio Control 1' */
  84enum aic26_wlen {
  85        AIC26_WLEN_16   = 0 << 10,
  86        AIC26_WLEN_20   = 1 << 10,
  87        AIC26_WLEN_24   = 2 << 10,
  88        AIC26_WLEN_32   = 3 << 10,
  89};
  90
  91#endif /* _TLV320AIC16_H_ */
  92