linux/sound/soc/codecs/wm8994.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * wm8994.c  --  WM8994 ALSA SoC Audio driver
   4 *
   5 * Copyright 2009-12 Wolfson Microelectronics plc
   6 *
   7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8 */
   9
  10#include <linux/module.h>
  11#include <linux/moduleparam.h>
  12#include <linux/init.h>
  13#include <linux/delay.h>
  14#include <linux/pm.h>
  15#include <linux/gcd.h>
  16#include <linux/i2c.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm_runtime.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/slab.h>
  21#include <sound/core.h>
  22#include <sound/jack.h>
  23#include <sound/pcm.h>
  24#include <sound/pcm_params.h>
  25#include <sound/soc.h>
  26#include <sound/initval.h>
  27#include <sound/tlv.h>
  28#include <trace/events/asoc.h>
  29
  30#include <linux/mfd/wm8994/core.h>
  31#include <linux/mfd/wm8994/registers.h>
  32#include <linux/mfd/wm8994/pdata.h>
  33#include <linux/mfd/wm8994/gpio.h>
  34
  35#include "wm8994.h"
  36#include "wm_hubs.h"
  37
  38#define WM1811_JACKDET_MODE_NONE  0x0000
  39#define WM1811_JACKDET_MODE_JACK  0x0100
  40#define WM1811_JACKDET_MODE_MIC   0x0080
  41#define WM1811_JACKDET_MODE_AUDIO 0x0180
  42
  43#define WM8994_NUM_DRC 3
  44#define WM8994_NUM_EQ  3
  45
  46static struct {
  47        unsigned int reg;
  48        unsigned int mask;
  49} wm8994_vu_bits[] = {
  50        { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  51        { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  52        { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  53        { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  54        { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  55        { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  56        { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  57        { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  58        { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  59        { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  60
  61        { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  62        { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  63        { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  64        { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  65        { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  66        { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  67        { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  68        { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  69        { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  70        { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  71        { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  72        { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  73        { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  74        { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  75        { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  76        { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  77};
  78
  79static int wm8994_drc_base[] = {
  80        WM8994_AIF1_DRC1_1,
  81        WM8994_AIF1_DRC2_1,
  82        WM8994_AIF2_DRC_1,
  83};
  84
  85static int wm8994_retune_mobile_base[] = {
  86        WM8994_AIF1_DAC1_EQ_GAINS_1,
  87        WM8994_AIF1_DAC2_EQ_GAINS_1,
  88        WM8994_AIF2_EQ_GAINS_1,
  89};
  90
  91static const struct wm8958_micd_rate micdet_rates[] = {
  92        { 32768,       true,  1, 4 },
  93        { 32768,       false, 1, 1 },
  94        { 44100 * 256, true,  7, 10 },
  95        { 44100 * 256, false, 7, 10 },
  96};
  97
  98static const struct wm8958_micd_rate jackdet_rates[] = {
  99        { 32768,       true,  0, 1 },
 100        { 32768,       false, 0, 1 },
 101        { 44100 * 256, true,  10, 10 },
 102        { 44100 * 256, false, 7, 8 },
 103};
 104
 105static void wm8958_micd_set_rate(struct snd_soc_component *component)
 106{
 107        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 108        struct wm8994 *control = wm8994->wm8994;
 109        int best, i, sysclk, val;
 110        bool idle;
 111        const struct wm8958_micd_rate *rates;
 112        int num_rates;
 113
 114        idle = !wm8994->jack_mic;
 115
 116        sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1);
 117        if (sysclk & WM8994_SYSCLK_SRC)
 118                sysclk = wm8994->aifclk[1];
 119        else
 120                sysclk = wm8994->aifclk[0];
 121
 122        if (control->pdata.micd_rates) {
 123                rates = control->pdata.micd_rates;
 124                num_rates = control->pdata.num_micd_rates;
 125        } else if (wm8994->jackdet) {
 126                rates = jackdet_rates;
 127                num_rates = ARRAY_SIZE(jackdet_rates);
 128        } else {
 129                rates = micdet_rates;
 130                num_rates = ARRAY_SIZE(micdet_rates);
 131        }
 132
 133        best = 0;
 134        for (i = 0; i < num_rates; i++) {
 135                if (rates[i].idle != idle)
 136                        continue;
 137                if (abs(rates[i].sysclk - sysclk) <
 138                    abs(rates[best].sysclk - sysclk))
 139                        best = i;
 140                else if (rates[best].idle != idle)
 141                        best = i;
 142        }
 143
 144        val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 145                | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 146
 147        dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
 148                rates[best].start, rates[best].rate, sysclk,
 149                idle ? "idle" : "active");
 150
 151        snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
 152                            WM8958_MICD_BIAS_STARTTIME_MASK |
 153                            WM8958_MICD_RATE_MASK, val);
 154}
 155
 156static int configure_aif_clock(struct snd_soc_component *component, int aif)
 157{
 158        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 159        int rate;
 160        int reg1 = 0;
 161        int offset;
 162
 163        if (aif)
 164                offset = 4;
 165        else
 166                offset = 0;
 167
 168        switch (wm8994->sysclk[aif]) {
 169        case WM8994_SYSCLK_MCLK1:
 170                rate = wm8994->mclk[0];
 171                break;
 172
 173        case WM8994_SYSCLK_MCLK2:
 174                reg1 |= 0x8;
 175                rate = wm8994->mclk[1];
 176                break;
 177
 178        case WM8994_SYSCLK_FLL1:
 179                reg1 |= 0x10;
 180                rate = wm8994->fll[0].out;
 181                break;
 182
 183        case WM8994_SYSCLK_FLL2:
 184                reg1 |= 0x18;
 185                rate = wm8994->fll[1].out;
 186                break;
 187
 188        default:
 189                return -EINVAL;
 190        }
 191
 192        if (rate >= 13500000) {
 193                rate /= 2;
 194                reg1 |= WM8994_AIF1CLK_DIV;
 195
 196                dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
 197                        aif + 1, rate);
 198        }
 199
 200        wm8994->aifclk[aif] = rate;
 201
 202        snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
 203                            WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 204                            reg1);
 205
 206        return 0;
 207}
 208
 209static int configure_clock(struct snd_soc_component *component)
 210{
 211        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 212        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 213        int change, new;
 214
 215        /* Bring up the AIF clocks first */
 216        configure_aif_clock(component, 0);
 217        configure_aif_clock(component, 1);
 218
 219        /* Then switch CLK_SYS over to the higher of them; a change
 220         * can only happen as a result of a clocking change which can
 221         * only be made outside of DAPM so we can safely redo the
 222         * clocking.
 223         */
 224
 225        /* If they're equal it doesn't matter which is used */
 226        if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 227                wm8958_micd_set_rate(component);
 228                return 0;
 229        }
 230
 231        if (wm8994->aifclk[0] < wm8994->aifclk[1])
 232                new = WM8994_SYSCLK_SRC;
 233        else
 234                new = 0;
 235
 236        change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
 237                                     WM8994_SYSCLK_SRC, new);
 238        if (change)
 239                snd_soc_dapm_sync(dapm);
 240
 241        wm8958_micd_set_rate(component);
 242
 243        return 0;
 244}
 245
 246static int check_clk_sys(struct snd_soc_dapm_widget *source,
 247                         struct snd_soc_dapm_widget *sink)
 248{
 249        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
 250        int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
 251        const char *clk;
 252
 253        /* Check what we're currently using for CLK_SYS */
 254        if (reg & WM8994_SYSCLK_SRC)
 255                clk = "AIF2CLK";
 256        else
 257                clk = "AIF1CLK";
 258
 259        return strcmp(source->name, clk) == 0;
 260}
 261
 262static const char *sidetone_hpf_text[] = {
 263        "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 264};
 265
 266static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
 267                            WM8994_SIDETONE, 7, sidetone_hpf_text);
 268
 269static const char *adc_hpf_text[] = {
 270        "HiFi", "Voice 1", "Voice 2", "Voice 3"
 271};
 272
 273static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
 274                            WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
 275
 276static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
 277                            WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
 278
 279static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
 280                            WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
 281
 282static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 283static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 284static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 285static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 286static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 287static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 288static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 289
 290#define WM8994_DRC_SWITCH(xname, reg, shift) \
 291        SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
 292                snd_soc_get_volsw, wm8994_put_drc_sw)
 293
 294static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 295                             struct snd_ctl_elem_value *ucontrol)
 296{
 297        struct soc_mixer_control *mc =
 298                (struct soc_mixer_control *)kcontrol->private_value;
 299        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 300        int mask, ret;
 301
 302        /* Can't enable both ADC and DAC paths simultaneously */
 303        if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 304                mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 305                        WM8994_AIF1ADC1R_DRC_ENA_MASK;
 306        else
 307                mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 308
 309        ret = snd_soc_component_read32(component, mc->reg);
 310        if (ret < 0)
 311                return ret;
 312        if (ret & mask)
 313                return -EINVAL;
 314
 315        return snd_soc_put_volsw(kcontrol, ucontrol);
 316}
 317
 318static void wm8994_set_drc(struct snd_soc_component *component, int drc)
 319{
 320        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 321        struct wm8994 *control = wm8994->wm8994;
 322        struct wm8994_pdata *pdata = &control->pdata;
 323        int base = wm8994_drc_base[drc];
 324        int cfg = wm8994->drc_cfg[drc];
 325        int save, i;
 326
 327        /* Save any enables; the configuration should clear them. */
 328        save = snd_soc_component_read32(component, base);
 329        save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 330                WM8994_AIF1ADC1R_DRC_ENA;
 331
 332        for (i = 0; i < WM8994_DRC_REGS; i++)
 333                snd_soc_component_update_bits(component, base + i, 0xffff,
 334                                    pdata->drc_cfgs[cfg].regs[i]);
 335
 336        snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
 337                             WM8994_AIF1ADC1L_DRC_ENA |
 338                             WM8994_AIF1ADC1R_DRC_ENA, save);
 339}
 340
 341/* Icky as hell but saves code duplication */
 342static int wm8994_get_drc(const char *name)
 343{
 344        if (strcmp(name, "AIF1DRC1 Mode") == 0)
 345                return 0;
 346        if (strcmp(name, "AIF1DRC2 Mode") == 0)
 347                return 1;
 348        if (strcmp(name, "AIF2DRC Mode") == 0)
 349                return 2;
 350        return -EINVAL;
 351}
 352
 353static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 354                               struct snd_ctl_elem_value *ucontrol)
 355{
 356        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 357        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 358        struct wm8994 *control = wm8994->wm8994;
 359        struct wm8994_pdata *pdata = &control->pdata;
 360        int drc = wm8994_get_drc(kcontrol->id.name);
 361        int value = ucontrol->value.enumerated.item[0];
 362
 363        if (drc < 0)
 364                return drc;
 365
 366        if (value >= pdata->num_drc_cfgs)
 367                return -EINVAL;
 368
 369        wm8994->drc_cfg[drc] = value;
 370
 371        wm8994_set_drc(component, drc);
 372
 373        return 0;
 374}
 375
 376static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 377                               struct snd_ctl_elem_value *ucontrol)
 378{
 379        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 380        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 381        int drc = wm8994_get_drc(kcontrol->id.name);
 382
 383        if (drc < 0)
 384                return drc;
 385        ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 386
 387        return 0;
 388}
 389
 390static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
 391{
 392        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 393        struct wm8994 *control = wm8994->wm8994;
 394        struct wm8994_pdata *pdata = &control->pdata;
 395        int base = wm8994_retune_mobile_base[block];
 396        int iface, best, best_val, save, i, cfg;
 397
 398        if (!pdata || !wm8994->num_retune_mobile_texts)
 399                return;
 400
 401        switch (block) {
 402        case 0:
 403        case 1:
 404                iface = 0;
 405                break;
 406        case 2:
 407                iface = 1;
 408                break;
 409        default:
 410                return;
 411        }
 412
 413        /* Find the version of the currently selected configuration
 414         * with the nearest sample rate. */
 415        cfg = wm8994->retune_mobile_cfg[block];
 416        best = 0;
 417        best_val = INT_MAX;
 418        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 419                if (strcmp(pdata->retune_mobile_cfgs[i].name,
 420                           wm8994->retune_mobile_texts[cfg]) == 0 &&
 421                    abs(pdata->retune_mobile_cfgs[i].rate
 422                        - wm8994->dac_rates[iface]) < best_val) {
 423                        best = i;
 424                        best_val = abs(pdata->retune_mobile_cfgs[i].rate
 425                                       - wm8994->dac_rates[iface]);
 426                }
 427        }
 428
 429        dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 430                block,
 431                pdata->retune_mobile_cfgs[best].name,
 432                pdata->retune_mobile_cfgs[best].rate,
 433                wm8994->dac_rates[iface]);
 434
 435        /* The EQ will be disabled while reconfiguring it, remember the
 436         * current configuration.
 437         */
 438        save = snd_soc_component_read32(component, base);
 439        save &= WM8994_AIF1DAC1_EQ_ENA;
 440
 441        for (i = 0; i < WM8994_EQ_REGS; i++)
 442                snd_soc_component_update_bits(component, base + i, 0xffff,
 443                                pdata->retune_mobile_cfgs[best].regs[i]);
 444
 445        snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
 446}
 447
 448/* Icky as hell but saves code duplication */
 449static int wm8994_get_retune_mobile_block(const char *name)
 450{
 451        if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 452                return 0;
 453        if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 454                return 1;
 455        if (strcmp(name, "AIF2 EQ Mode") == 0)
 456                return 2;
 457        return -EINVAL;
 458}
 459
 460static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 461                                         struct snd_ctl_elem_value *ucontrol)
 462{
 463        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 464        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 465        struct wm8994 *control = wm8994->wm8994;
 466        struct wm8994_pdata *pdata = &control->pdata;
 467        int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 468        int value = ucontrol->value.enumerated.item[0];
 469
 470        if (block < 0)
 471                return block;
 472
 473        if (value >= pdata->num_retune_mobile_cfgs)
 474                return -EINVAL;
 475
 476        wm8994->retune_mobile_cfg[block] = value;
 477
 478        wm8994_set_retune_mobile(component, block);
 479
 480        return 0;
 481}
 482
 483static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 484                                         struct snd_ctl_elem_value *ucontrol)
 485{
 486        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 487        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 488        int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 489
 490        if (block < 0)
 491                return block;
 492
 493        ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 494
 495        return 0;
 496}
 497
 498static const char *aif_chan_src_text[] = {
 499        "Left", "Right"
 500};
 501
 502static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
 503                            WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
 504
 505static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
 506                            WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
 507
 508static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
 509                            WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
 510
 511static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
 512                            WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
 513
 514static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
 515                            WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
 516
 517static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
 518                            WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
 519
 520static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
 521                            WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
 522
 523static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
 524                            WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
 525
 526static const char *osr_text[] = {
 527        "Low Power", "High Performance",
 528};
 529
 530static SOC_ENUM_SINGLE_DECL(dac_osr,
 531                            WM8994_OVERSAMPLING, 0, osr_text);
 532
 533static SOC_ENUM_SINGLE_DECL(adc_osr,
 534                            WM8994_OVERSAMPLING, 1, osr_text);
 535
 536static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
 537SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 538                 WM8994_AIF1_ADC1_RIGHT_VOLUME,
 539                 1, 119, 0, digital_tlv),
 540SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 541                 WM8994_AIF2_ADC_RIGHT_VOLUME,
 542                 1, 119, 0, digital_tlv),
 543
 544SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 545SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 546SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 547SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 548
 549SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 550SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 551SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 552SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 553
 554SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 555                 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 556SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 557                 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 558
 559SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 560SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 561
 562SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 563SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 564
 565WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 566WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 567WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 568
 569WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 570WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 571WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 572
 573SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 574               5, 12, 0, st_tlv),
 575SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 576               0, 12, 0, st_tlv),
 577SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 578               5, 12, 0, st_tlv),
 579SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 580               0, 12, 0, st_tlv),
 581SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 582SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 583
 584SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 585SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 586
 587SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 588SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 589
 590SOC_ENUM("ADC OSR", adc_osr),
 591SOC_ENUM("DAC OSR", dac_osr),
 592
 593SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 594                 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 595SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 596             WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 597
 598SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 599                 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 600SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 601             WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 602
 603SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 604               6, 1, 1, wm_hubs_spkmix_tlv),
 605SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 606               2, 1, 1, wm_hubs_spkmix_tlv),
 607
 608SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 609               6, 1, 1, wm_hubs_spkmix_tlv),
 610SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 611               2, 1, 1, wm_hubs_spkmix_tlv),
 612
 613SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 614               10, 15, 0, wm8994_3d_tlv),
 615SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 616           8, 1, 0),
 617SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 618               10, 15, 0, wm8994_3d_tlv),
 619SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 620           8, 1, 0),
 621SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 622               10, 15, 0, wm8994_3d_tlv),
 623SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 624           8, 1, 0),
 625};
 626
 627/* Controls not available on WM1811 */
 628static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 629SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 630                 WM8994_AIF1_ADC2_RIGHT_VOLUME,
 631                 1, 119, 0, digital_tlv),
 632SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 633                 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 634
 635SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 636
 637WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 638WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 639WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 640
 641SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 642SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 643};
 644
 645static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 646SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 647               eq_tlv),
 648SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 649               eq_tlv),
 650SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 651               eq_tlv),
 652SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 653               eq_tlv),
 654SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 655               eq_tlv),
 656
 657SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 658               eq_tlv),
 659SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 660               eq_tlv),
 661SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 662               eq_tlv),
 663SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 664               eq_tlv),
 665SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 666               eq_tlv),
 667
 668SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 669               eq_tlv),
 670SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 671               eq_tlv),
 672SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 673               eq_tlv),
 674SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 675               eq_tlv),
 676SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 677               eq_tlv),
 678};
 679
 680static const struct snd_kcontrol_new wm8994_drc_controls[] = {
 681SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
 682                   WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 683                   WM8994_AIF1ADC1R_DRC_ENA),
 684SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
 685                   WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
 686                   WM8994_AIF1ADC2R_DRC_ENA),
 687SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
 688                   WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
 689                   WM8994_AIF2ADCR_DRC_ENA),
 690};
 691
 692static const char *wm8958_ng_text[] = {
 693        "30ms", "125ms", "250ms", "500ms",
 694};
 695
 696static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
 697                            WM8958_AIF1_DAC1_NOISE_GATE,
 698                            WM8958_AIF1DAC1_NG_THR_SHIFT,
 699                            wm8958_ng_text);
 700
 701static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
 702                            WM8958_AIF1_DAC2_NOISE_GATE,
 703                            WM8958_AIF1DAC2_NG_THR_SHIFT,
 704                            wm8958_ng_text);
 705
 706static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
 707                            WM8958_AIF2_DAC_NOISE_GATE,
 708                            WM8958_AIF2DAC_NG_THR_SHIFT,
 709                            wm8958_ng_text);
 710
 711static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 712SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 713
 714SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 715           WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 716SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 717SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 718               WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 719               7, 1, ng_tlv),
 720
 721SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 722           WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 723SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 724SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 725               WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 726               7, 1, ng_tlv),
 727
 728SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 729           WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 730SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 731SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 732               WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 733               7, 1, ng_tlv),
 734};
 735
 736static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 737SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 738               mixin_boost_tlv),
 739SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 740               mixin_boost_tlv),
 741};
 742
 743/* We run all mode setting through a function to enforce audio mode */
 744static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
 745{
 746        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 747
 748        if (!wm8994->jackdet || !wm8994->micdet[0].jack)
 749                return;
 750
 751        if (wm8994->active_refcount)
 752                mode = WM1811_JACKDET_MODE_AUDIO;
 753
 754        if (mode == wm8994->jackdet_mode)
 755                return;
 756
 757        wm8994->jackdet_mode = mode;
 758
 759        /* Always use audio mode to detect while the system is active */
 760        if (mode != WM1811_JACKDET_MODE_NONE)
 761                mode = WM1811_JACKDET_MODE_AUDIO;
 762
 763        snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 764                            WM1811_JACKDET_MODE_MASK, mode);
 765}
 766
 767static void active_reference(struct snd_soc_component *component)
 768{
 769        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 770
 771        mutex_lock(&wm8994->accdet_lock);
 772
 773        wm8994->active_refcount++;
 774
 775        dev_dbg(component->dev, "Active refcount incremented, now %d\n",
 776                wm8994->active_refcount);
 777
 778        /* If we're using jack detection go into audio mode */
 779        wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
 780
 781        mutex_unlock(&wm8994->accdet_lock);
 782}
 783
 784static void active_dereference(struct snd_soc_component *component)
 785{
 786        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 787        u16 mode;
 788
 789        mutex_lock(&wm8994->accdet_lock);
 790
 791        wm8994->active_refcount--;
 792
 793        dev_dbg(component->dev, "Active refcount decremented, now %d\n",
 794                wm8994->active_refcount);
 795
 796        if (wm8994->active_refcount == 0) {
 797                /* Go into appropriate detection only mode */
 798                if (wm8994->jack_mic || wm8994->mic_detecting)
 799                        mode = WM1811_JACKDET_MODE_MIC;
 800                else
 801                        mode = WM1811_JACKDET_MODE_JACK;
 802
 803                wm1811_jackdet_set_mode(component, mode);
 804        }
 805
 806        mutex_unlock(&wm8994->accdet_lock);
 807}
 808
 809static int clk_sys_event(struct snd_soc_dapm_widget *w,
 810                         struct snd_kcontrol *kcontrol, int event)
 811{
 812        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 813        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 814
 815        switch (event) {
 816        case SND_SOC_DAPM_PRE_PMU:
 817                return configure_clock(component);
 818
 819        case SND_SOC_DAPM_POST_PMU:
 820                /*
 821                 * JACKDET won't run until we start the clock and it
 822                 * only reports deltas, make sure we notify the state
 823                 * up the stack on startup.  Use a *very* generous
 824                 * timeout for paranoia, there's no urgency and we
 825                 * don't want false reports.
 826                 */
 827                if (wm8994->jackdet && !wm8994->clk_has_run) {
 828                        queue_delayed_work(system_power_efficient_wq,
 829                                           &wm8994->jackdet_bootstrap,
 830                                           msecs_to_jiffies(1000));
 831                        wm8994->clk_has_run = true;
 832                }
 833                break;
 834
 835        case SND_SOC_DAPM_POST_PMD:
 836                configure_clock(component);
 837                break;
 838        }
 839
 840        return 0;
 841}
 842
 843static void vmid_reference(struct snd_soc_component *component)
 844{
 845        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 846
 847        pm_runtime_get_sync(component->dev);
 848
 849        wm8994->vmid_refcount++;
 850
 851        dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
 852                wm8994->vmid_refcount);
 853
 854        if (wm8994->vmid_refcount == 1) {
 855                snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
 856                                    WM8994_LINEOUT1_DISCH |
 857                                    WM8994_LINEOUT2_DISCH, 0);
 858
 859                wm_hubs_vmid_ena(component);
 860
 861                switch (wm8994->vmid_mode) {
 862                default:
 863                        WARN_ON(NULL == "Invalid VMID mode");
 864                        /* fall through */
 865                case WM8994_VMID_NORMAL:
 866                        /* Startup bias, VMID ramp & buffer */
 867                        snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 868                                            WM8994_BIAS_SRC |
 869                                            WM8994_VMID_DISCH |
 870                                            WM8994_STARTUP_BIAS_ENA |
 871                                            WM8994_VMID_BUF_ENA |
 872                                            WM8994_VMID_RAMP_MASK,
 873                                            WM8994_BIAS_SRC |
 874                                            WM8994_STARTUP_BIAS_ENA |
 875                                            WM8994_VMID_BUF_ENA |
 876                                            (0x2 << WM8994_VMID_RAMP_SHIFT));
 877
 878                        /* Main bias enable, VMID=2x40k */
 879                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
 880                                            WM8994_BIAS_ENA |
 881                                            WM8994_VMID_SEL_MASK,
 882                                            WM8994_BIAS_ENA | 0x2);
 883
 884                        msleep(300);
 885
 886                        snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 887                                            WM8994_VMID_RAMP_MASK |
 888                                            WM8994_BIAS_SRC,
 889                                            0);
 890                        break;
 891
 892                case WM8994_VMID_FORCE:
 893                        /* Startup bias, slow VMID ramp & buffer */
 894                        snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 895                                            WM8994_BIAS_SRC |
 896                                            WM8994_VMID_DISCH |
 897                                            WM8994_STARTUP_BIAS_ENA |
 898                                            WM8994_VMID_BUF_ENA |
 899                                            WM8994_VMID_RAMP_MASK,
 900                                            WM8994_BIAS_SRC |
 901                                            WM8994_STARTUP_BIAS_ENA |
 902                                            WM8994_VMID_BUF_ENA |
 903                                            (0x2 << WM8994_VMID_RAMP_SHIFT));
 904
 905                        /* Main bias enable, VMID=2x40k */
 906                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
 907                                            WM8994_BIAS_ENA |
 908                                            WM8994_VMID_SEL_MASK,
 909                                            WM8994_BIAS_ENA | 0x2);
 910
 911                        msleep(400);
 912
 913                        snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 914                                            WM8994_VMID_RAMP_MASK |
 915                                            WM8994_BIAS_SRC,
 916                                            0);
 917                        break;
 918                }
 919        }
 920}
 921
 922static void vmid_dereference(struct snd_soc_component *component)
 923{
 924        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
 925
 926        wm8994->vmid_refcount--;
 927
 928        dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
 929                wm8994->vmid_refcount);
 930
 931        if (wm8994->vmid_refcount == 0) {
 932                if (wm8994->hubs.lineout1_se)
 933                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
 934                                            WM8994_LINEOUT1N_ENA |
 935                                            WM8994_LINEOUT1P_ENA,
 936                                            WM8994_LINEOUT1N_ENA |
 937                                            WM8994_LINEOUT1P_ENA);
 938
 939                if (wm8994->hubs.lineout2_se)
 940                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
 941                                            WM8994_LINEOUT2N_ENA |
 942                                            WM8994_LINEOUT2P_ENA,
 943                                            WM8994_LINEOUT2N_ENA |
 944                                            WM8994_LINEOUT2P_ENA);
 945
 946                /* Start discharging VMID */
 947                snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 948                                    WM8994_BIAS_SRC |
 949                                    WM8994_VMID_DISCH,
 950                                    WM8994_BIAS_SRC |
 951                                    WM8994_VMID_DISCH);
 952
 953                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
 954                                    WM8994_VMID_SEL_MASK, 0);
 955
 956                msleep(400);
 957
 958                /* Active discharge */
 959                snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
 960                                    WM8994_LINEOUT1_DISCH |
 961                                    WM8994_LINEOUT2_DISCH,
 962                                    WM8994_LINEOUT1_DISCH |
 963                                    WM8994_LINEOUT2_DISCH);
 964
 965                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
 966                                    WM8994_LINEOUT1N_ENA |
 967                                    WM8994_LINEOUT1P_ENA |
 968                                    WM8994_LINEOUT2N_ENA |
 969                                    WM8994_LINEOUT2P_ENA, 0);
 970
 971                /* Switch off startup biases */
 972                snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
 973                                    WM8994_BIAS_SRC |
 974                                    WM8994_STARTUP_BIAS_ENA |
 975                                    WM8994_VMID_BUF_ENA |
 976                                    WM8994_VMID_RAMP_MASK, 0);
 977
 978                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
 979                                    WM8994_VMID_SEL_MASK, 0);
 980        }
 981
 982        pm_runtime_put(component->dev);
 983}
 984
 985static int vmid_event(struct snd_soc_dapm_widget *w,
 986                      struct snd_kcontrol *kcontrol, int event)
 987{
 988        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 989
 990        switch (event) {
 991        case SND_SOC_DAPM_PRE_PMU:
 992                vmid_reference(component);
 993                break;
 994
 995        case SND_SOC_DAPM_POST_PMD:
 996                vmid_dereference(component);
 997                break;
 998        }
 999
1000        return 0;
1001}
1002
1003static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
1004{
1005        int source = 0;  /* GCC flow analysis can't track enable */
1006        int reg, reg_r;
1007
1008        /* We also need the same AIF source for L/R and only one path */
1009        reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
1010        switch (reg) {
1011        case WM8994_AIF2DACL_TO_DAC1L:
1012                dev_vdbg(component->dev, "Class W source AIF2DAC\n");
1013                source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014                break;
1015        case WM8994_AIF1DAC2L_TO_DAC1L:
1016                dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
1017                source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018                break;
1019        case WM8994_AIF1DAC1L_TO_DAC1L:
1020                dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
1021                source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1022                break;
1023        default:
1024                dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
1025                return false;
1026        }
1027
1028        reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1029        if (reg_r != reg) {
1030                dev_vdbg(component->dev, "Left and right DAC mixers different\n");
1031                return false;
1032        }
1033
1034        /* Set the source up */
1035        snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
1036                            WM8994_CP_DYN_SRC_SEL_MASK, source);
1037
1038        return true;
1039}
1040
1041static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1042                      struct snd_kcontrol *kcontrol, int event)
1043{
1044        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1045        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1046        struct wm8994 *control = wm8994->wm8994;
1047        int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1048        int i;
1049        int dac;
1050        int adc;
1051        int val;
1052
1053        switch (control->type) {
1054        case WM8994:
1055        case WM8958:
1056                mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1057                break;
1058        default:
1059                break;
1060        }
1061
1062        switch (event) {
1063        case SND_SOC_DAPM_PRE_PMU:
1064                /* Don't enable timeslot 2 if not in use */
1065                if (wm8994->channels[0] <= 2)
1066                        mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1067
1068                val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1);
1069                if ((val & WM8994_AIF1ADCL_SRC) &&
1070                    (val & WM8994_AIF1ADCR_SRC))
1071                        adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1072                else if (!(val & WM8994_AIF1ADCL_SRC) &&
1073                         !(val & WM8994_AIF1ADCR_SRC))
1074                        adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1075                else
1076                        adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1077                                WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1078
1079                val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2);
1080                if ((val & WM8994_AIF1DACL_SRC) &&
1081                    (val & WM8994_AIF1DACR_SRC))
1082                        dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1083                else if (!(val & WM8994_AIF1DACL_SRC) &&
1084                         !(val & WM8994_AIF1DACR_SRC))
1085                        dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1086                else
1087                        dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1088                                WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1089
1090                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1091                                    mask, adc);
1092                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1093                                    mask, dac);
1094                snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1095                                    WM8994_AIF1DSPCLK_ENA |
1096                                    WM8994_SYSDSPCLK_ENA,
1097                                    WM8994_AIF1DSPCLK_ENA |
1098                                    WM8994_SYSDSPCLK_ENA);
1099                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
1100                                    WM8994_AIF1ADC1R_ENA |
1101                                    WM8994_AIF1ADC1L_ENA |
1102                                    WM8994_AIF1ADC2R_ENA |
1103                                    WM8994_AIF1ADC2L_ENA);
1104                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
1105                                    WM8994_AIF1DAC1R_ENA |
1106                                    WM8994_AIF1DAC1L_ENA |
1107                                    WM8994_AIF1DAC2R_ENA |
1108                                    WM8994_AIF1DAC2L_ENA);
1109                break;
1110
1111        case SND_SOC_DAPM_POST_PMU:
1112                for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1113                        snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1114                                      snd_soc_component_read32(component,
1115                                                   wm8994_vu_bits[i].reg));
1116                break;
1117
1118        case SND_SOC_DAPM_PRE_PMD:
1119        case SND_SOC_DAPM_POST_PMD:
1120                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1121                                    mask, 0);
1122                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1123                                    mask, 0);
1124
1125                val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1126                if (val & WM8994_AIF2DSPCLK_ENA)
1127                        val = WM8994_SYSDSPCLK_ENA;
1128                else
1129                        val = 0;
1130                snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1131                                    WM8994_SYSDSPCLK_ENA |
1132                                    WM8994_AIF1DSPCLK_ENA, val);
1133                break;
1134        }
1135
1136        return 0;
1137}
1138
1139static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1140                      struct snd_kcontrol *kcontrol, int event)
1141{
1142        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1143        int i;
1144        int dac;
1145        int adc;
1146        int val;
1147
1148        switch (event) {
1149        case SND_SOC_DAPM_PRE_PMU:
1150                val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1);
1151                if ((val & WM8994_AIF2ADCL_SRC) &&
1152                    (val & WM8994_AIF2ADCR_SRC))
1153                        adc = WM8994_AIF2ADCR_ENA;
1154                else if (!(val & WM8994_AIF2ADCL_SRC) &&
1155                         !(val & WM8994_AIF2ADCR_SRC))
1156                        adc = WM8994_AIF2ADCL_ENA;
1157                else
1158                        adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1159
1160
1161                val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2);
1162                if ((val & WM8994_AIF2DACL_SRC) &&
1163                    (val & WM8994_AIF2DACR_SRC))
1164                        dac = WM8994_AIF2DACR_ENA;
1165                else if (!(val & WM8994_AIF2DACL_SRC) &&
1166                         !(val & WM8994_AIF2DACR_SRC))
1167                        dac = WM8994_AIF2DACL_ENA;
1168                else
1169                        dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1170
1171                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1172                                    WM8994_AIF2ADCL_ENA |
1173                                    WM8994_AIF2ADCR_ENA, adc);
1174                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1175                                    WM8994_AIF2DACL_ENA |
1176                                    WM8994_AIF2DACR_ENA, dac);
1177                snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1178                                    WM8994_AIF2DSPCLK_ENA |
1179                                    WM8994_SYSDSPCLK_ENA,
1180                                    WM8994_AIF2DSPCLK_ENA |
1181                                    WM8994_SYSDSPCLK_ENA);
1182                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1183                                    WM8994_AIF2ADCL_ENA |
1184                                    WM8994_AIF2ADCR_ENA,
1185                                    WM8994_AIF2ADCL_ENA |
1186                                    WM8994_AIF2ADCR_ENA);
1187                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1188                                    WM8994_AIF2DACL_ENA |
1189                                    WM8994_AIF2DACR_ENA,
1190                                    WM8994_AIF2DACL_ENA |
1191                                    WM8994_AIF2DACR_ENA);
1192                break;
1193
1194        case SND_SOC_DAPM_POST_PMU:
1195                for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1196                        snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1197                                      snd_soc_component_read32(component,
1198                                                   wm8994_vu_bits[i].reg));
1199                break;
1200
1201        case SND_SOC_DAPM_PRE_PMD:
1202        case SND_SOC_DAPM_POST_PMD:
1203                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1204                                    WM8994_AIF2DACL_ENA |
1205                                    WM8994_AIF2DACR_ENA, 0);
1206                snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1207                                    WM8994_AIF2ADCL_ENA |
1208                                    WM8994_AIF2ADCR_ENA, 0);
1209
1210                val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1211                if (val & WM8994_AIF1DSPCLK_ENA)
1212                        val = WM8994_SYSDSPCLK_ENA;
1213                else
1214                        val = 0;
1215                snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1216                                    WM8994_SYSDSPCLK_ENA |
1217                                    WM8994_AIF2DSPCLK_ENA, val);
1218                break;
1219        }
1220
1221        return 0;
1222}
1223
1224static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1225                           struct snd_kcontrol *kcontrol, int event)
1226{
1227        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1228        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1229
1230        switch (event) {
1231        case SND_SOC_DAPM_PRE_PMU:
1232                wm8994->aif1clk_enable = 1;
1233                break;
1234        case SND_SOC_DAPM_POST_PMD:
1235                wm8994->aif1clk_disable = 1;
1236                break;
1237        }
1238
1239        return 0;
1240}
1241
1242static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1243                           struct snd_kcontrol *kcontrol, int event)
1244{
1245        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1246        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1247
1248        switch (event) {
1249        case SND_SOC_DAPM_PRE_PMU:
1250                wm8994->aif2clk_enable = 1;
1251                break;
1252        case SND_SOC_DAPM_POST_PMD:
1253                wm8994->aif2clk_disable = 1;
1254                break;
1255        }
1256
1257        return 0;
1258}
1259
1260static int late_enable_ev(struct snd_soc_dapm_widget *w,
1261                          struct snd_kcontrol *kcontrol, int event)
1262{
1263        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1264        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1265
1266        switch (event) {
1267        case SND_SOC_DAPM_PRE_PMU:
1268                if (wm8994->aif1clk_enable) {
1269                        aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1270                        snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1271                                            WM8994_AIF1CLK_ENA_MASK,
1272                                            WM8994_AIF1CLK_ENA);
1273                        aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1274                        wm8994->aif1clk_enable = 0;
1275                }
1276                if (wm8994->aif2clk_enable) {
1277                        aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1278                        snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1279                                            WM8994_AIF2CLK_ENA_MASK,
1280                                            WM8994_AIF2CLK_ENA);
1281                        aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1282                        wm8994->aif2clk_enable = 0;
1283                }
1284                break;
1285        }
1286
1287        /* We may also have postponed startup of DSP, handle that. */
1288        wm8958_aif_ev(w, kcontrol, event);
1289
1290        return 0;
1291}
1292
1293static int late_disable_ev(struct snd_soc_dapm_widget *w,
1294                           struct snd_kcontrol *kcontrol, int event)
1295{
1296        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1297        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1298
1299        switch (event) {
1300        case SND_SOC_DAPM_POST_PMD:
1301                if (wm8994->aif1clk_disable) {
1302                        aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1303                        snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1304                                            WM8994_AIF1CLK_ENA_MASK, 0);
1305                        aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1306                        wm8994->aif1clk_disable = 0;
1307                }
1308                if (wm8994->aif2clk_disable) {
1309                        aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1310                        snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1311                                            WM8994_AIF2CLK_ENA_MASK, 0);
1312                        aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1313                        wm8994->aif2clk_disable = 0;
1314                }
1315                break;
1316        }
1317
1318        return 0;
1319}
1320
1321static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1322                      struct snd_kcontrol *kcontrol, int event)
1323{
1324        late_enable_ev(w, kcontrol, event);
1325        return 0;
1326}
1327
1328static int micbias_ev(struct snd_soc_dapm_widget *w,
1329                      struct snd_kcontrol *kcontrol, int event)
1330{
1331        late_enable_ev(w, kcontrol, event);
1332        return 0;
1333}
1334
1335static int dac_ev(struct snd_soc_dapm_widget *w,
1336                  struct snd_kcontrol *kcontrol, int event)
1337{
1338        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1339        unsigned int mask = 1 << w->shift;
1340
1341        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1342                            mask, mask);
1343        return 0;
1344}
1345
1346static const char *adc_mux_text[] = {
1347        "ADC",
1348        "DMIC",
1349};
1350
1351static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1352
1353static const struct snd_kcontrol_new adcl_mux =
1354        SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1355
1356static const struct snd_kcontrol_new adcr_mux =
1357        SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1358
1359static const struct snd_kcontrol_new left_speaker_mixer[] = {
1360SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1361SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1362SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1363SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1364SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1365};
1366
1367static const struct snd_kcontrol_new right_speaker_mixer[] = {
1368SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1369SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1370SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1371SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1372SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1373};
1374
1375/* Debugging; dump chip status after DAPM transitions */
1376static int post_ev(struct snd_soc_dapm_widget *w,
1377            struct snd_kcontrol *kcontrol, int event)
1378{
1379        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1380        dev_dbg(component->dev, "SRC status: %x\n",
1381                snd_soc_component_read32(component,
1382                             WM8994_RATE_STATUS));
1383        return 0;
1384}
1385
1386static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1387SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1388                1, 1, 0),
1389SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1390                0, 1, 0),
1391};
1392
1393static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1394SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1395                1, 1, 0),
1396SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1397                0, 1, 0),
1398};
1399
1400static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1401SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1402                1, 1, 0),
1403SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1404                0, 1, 0),
1405};
1406
1407static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1408SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1409                1, 1, 0),
1410SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1411                0, 1, 0),
1412};
1413
1414static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1415SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416                5, 1, 0),
1417SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418                4, 1, 0),
1419SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420                2, 1, 0),
1421SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1422                1, 1, 0),
1423SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1424                0, 1, 0),
1425};
1426
1427static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1428SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429                5, 1, 0),
1430SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431                4, 1, 0),
1432SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433                2, 1, 0),
1434SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1435                1, 1, 0),
1436SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1437                0, 1, 0),
1438};
1439
1440#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1441        SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1442                snd_soc_dapm_get_volsw, wm8994_put_class_w)
1443
1444static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1445                              struct snd_ctl_elem_value *ucontrol)
1446{
1447        struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
1448        int ret;
1449
1450        ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1451
1452        wm_hubs_update_class_w(component);
1453
1454        return ret;
1455}
1456
1457static const struct snd_kcontrol_new dac1l_mix[] = {
1458WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459                      5, 1, 0),
1460WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461                      4, 1, 0),
1462WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463                      2, 1, 0),
1464WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1465                      1, 1, 0),
1466WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1467                      0, 1, 0),
1468};
1469
1470static const struct snd_kcontrol_new dac1r_mix[] = {
1471WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472                      5, 1, 0),
1473WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474                      4, 1, 0),
1475WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476                      2, 1, 0),
1477WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1478                      1, 1, 0),
1479WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1480                      0, 1, 0),
1481};
1482
1483static const char *sidetone_text[] = {
1484        "ADC/DMIC1", "DMIC2",
1485};
1486
1487static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1488                            WM8994_SIDETONE, 0, sidetone_text);
1489
1490static const struct snd_kcontrol_new sidetone1_mux =
1491        SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1492
1493static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1494                            WM8994_SIDETONE, 1, sidetone_text);
1495
1496static const struct snd_kcontrol_new sidetone2_mux =
1497        SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1498
1499static const char *aif1dac_text[] = {
1500        "AIF1DACDAT", "AIF3DACDAT",
1501};
1502
1503static const char *loopback_text[] = {
1504        "None", "ADCDAT",
1505};
1506
1507static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1508                            WM8994_AIF1_CONTROL_2,
1509                            WM8994_AIF1_LOOPBACK_SHIFT,
1510                            loopback_text);
1511
1512static const struct snd_kcontrol_new aif1_loopback =
1513        SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1514
1515static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1516                            WM8994_AIF2_CONTROL_2,
1517                            WM8994_AIF2_LOOPBACK_SHIFT,
1518                            loopback_text);
1519
1520static const struct snd_kcontrol_new aif2_loopback =
1521        SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1522
1523static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1524                            WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1525
1526static const struct snd_kcontrol_new aif1dac_mux =
1527        SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1528
1529static const char *aif2dac_text[] = {
1530        "AIF2DACDAT", "AIF3DACDAT",
1531};
1532
1533static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1534                            WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1535
1536static const struct snd_kcontrol_new aif2dac_mux =
1537        SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1538
1539static const char *aif2adc_text[] = {
1540        "AIF2ADCDAT", "AIF3DACDAT",
1541};
1542
1543static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1544                            WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1545
1546static const struct snd_kcontrol_new aif2adc_mux =
1547        SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1548
1549static const char *aif3adc_text[] = {
1550        "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1551};
1552
1553static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1554                            WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1555
1556static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1557        SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1558
1559static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1560                            WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1561
1562static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1563        SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1564
1565static const char *mono_pcm_out_text[] = {
1566        "None", "AIF2ADCL", "AIF2ADCR",
1567};
1568
1569static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1570                            WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1571
1572static const struct snd_kcontrol_new mono_pcm_out_mux =
1573        SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1574
1575static const char *aif2dac_src_text[] = {
1576        "AIF2", "AIF3",
1577};
1578
1579/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1580static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1581                            WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1582
1583static const struct snd_kcontrol_new aif2dacl_src_mux =
1584        SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1585
1586static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1587                            WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1588
1589static const struct snd_kcontrol_new aif2dacr_src_mux =
1590        SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1591
1592static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1593SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1594        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1595SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1596        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1597
1598SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1599        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1601        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1602SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1603        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1605        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1606SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1607        late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1608
1609SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1610                     left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1611                     late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1612SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1613                     right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1614                     late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1615SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1616                   late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1617SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1618                   late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1619
1620SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1621};
1622
1623static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1624SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1625                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1626                    SND_SOC_DAPM_PRE_PMD),
1627SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1628                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1629                    SND_SOC_DAPM_PRE_PMD),
1630SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1631SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1632                   left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1633SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1634                   right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1635SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1636SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1637};
1638
1639static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1640SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1641        dac_ev, SND_SOC_DAPM_PRE_PMU),
1642SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1643        dac_ev, SND_SOC_DAPM_PRE_PMU),
1644SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1645        dac_ev, SND_SOC_DAPM_PRE_PMU),
1646SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1647        dac_ev, SND_SOC_DAPM_PRE_PMU),
1648};
1649
1650static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1651SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1652SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1653SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1654SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1655};
1656
1657static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1658SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1659                        adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1660SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1661                        adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1662};
1663
1664static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1665SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1666SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1667};
1668
1669static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1670SND_SOC_DAPM_INPUT("DMIC1DAT"),
1671SND_SOC_DAPM_INPUT("DMIC2DAT"),
1672SND_SOC_DAPM_INPUT("Clock"),
1673
1674SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1675                      SND_SOC_DAPM_PRE_PMU),
1676SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1677                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1678
1679SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1680                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1681                    SND_SOC_DAPM_PRE_PMD),
1682
1683SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1684SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1685SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1686
1687SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1688                     0, SND_SOC_NOPM, 9, 0),
1689SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1690                     0, SND_SOC_NOPM, 8, 0),
1691SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1692                      SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1693                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1694SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1695                      SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1696                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1697
1698SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1699                     0, SND_SOC_NOPM, 11, 0),
1700SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1701                     0, SND_SOC_NOPM, 10, 0),
1702SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1703                      SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1704                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1705SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1706                      SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1707                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1708
1709SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1710                   aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1711SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1712                   aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1713
1714SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1715                   aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1716SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1717                   aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1718
1719SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1720                   aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1721SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1722                   aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1723
1724SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1725SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1726
1727SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1728                   dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1729SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1730                   dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1731
1732SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1733                     SND_SOC_NOPM, 13, 0),
1734SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1735                     SND_SOC_NOPM, 12, 0),
1736SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1737                      SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1738                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1739SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1740                      SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1741                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1742
1743SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1744SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1745SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1746SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1747
1748SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1749SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1750SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1751
1752SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1753SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1754
1755SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1756
1757SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1758SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1759SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1760SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1761
1762/* Power is done with the muxes since the ADC power also controls the
1763 * downsampling chain, the chip will automatically manage the analogue
1764 * specific portions.
1765 */
1766SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1767SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1768
1769SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1770SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1771
1772SND_SOC_DAPM_POST("Debug log", post_ev),
1773};
1774
1775static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1776SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1777};
1778
1779static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1780SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1781SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1782SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1783SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1784SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1785};
1786
1787static const struct snd_soc_dapm_route intercon[] = {
1788        { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1789        { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1790
1791        { "DSP1CLK", NULL, "CLK_SYS" },
1792        { "DSP2CLK", NULL, "CLK_SYS" },
1793        { "DSPINTCLK", NULL, "CLK_SYS" },
1794
1795        { "AIF1ADC1L", NULL, "AIF1CLK" },
1796        { "AIF1ADC1L", NULL, "DSP1CLK" },
1797        { "AIF1ADC1R", NULL, "AIF1CLK" },
1798        { "AIF1ADC1R", NULL, "DSP1CLK" },
1799        { "AIF1ADC1R", NULL, "DSPINTCLK" },
1800
1801        { "AIF1DAC1L", NULL, "AIF1CLK" },
1802        { "AIF1DAC1L", NULL, "DSP1CLK" },
1803        { "AIF1DAC1R", NULL, "AIF1CLK" },
1804        { "AIF1DAC1R", NULL, "DSP1CLK" },
1805        { "AIF1DAC1R", NULL, "DSPINTCLK" },
1806
1807        { "AIF1ADC2L", NULL, "AIF1CLK" },
1808        { "AIF1ADC2L", NULL, "DSP1CLK" },
1809        { "AIF1ADC2R", NULL, "AIF1CLK" },
1810        { "AIF1ADC2R", NULL, "DSP1CLK" },
1811        { "AIF1ADC2R", NULL, "DSPINTCLK" },
1812
1813        { "AIF1DAC2L", NULL, "AIF1CLK" },
1814        { "AIF1DAC2L", NULL, "DSP1CLK" },
1815        { "AIF1DAC2R", NULL, "AIF1CLK" },
1816        { "AIF1DAC2R", NULL, "DSP1CLK" },
1817        { "AIF1DAC2R", NULL, "DSPINTCLK" },
1818
1819        { "AIF2ADCL", NULL, "AIF2CLK" },
1820        { "AIF2ADCL", NULL, "DSP2CLK" },
1821        { "AIF2ADCR", NULL, "AIF2CLK" },
1822        { "AIF2ADCR", NULL, "DSP2CLK" },
1823        { "AIF2ADCR", NULL, "DSPINTCLK" },
1824
1825        { "AIF2DACL", NULL, "AIF2CLK" },
1826        { "AIF2DACL", NULL, "DSP2CLK" },
1827        { "AIF2DACR", NULL, "AIF2CLK" },
1828        { "AIF2DACR", NULL, "DSP2CLK" },
1829        { "AIF2DACR", NULL, "DSPINTCLK" },
1830
1831        { "DMIC1L", NULL, "DMIC1DAT" },
1832        { "DMIC1L", NULL, "CLK_SYS" },
1833        { "DMIC1R", NULL, "DMIC1DAT" },
1834        { "DMIC1R", NULL, "CLK_SYS" },
1835        { "DMIC2L", NULL, "DMIC2DAT" },
1836        { "DMIC2L", NULL, "CLK_SYS" },
1837        { "DMIC2R", NULL, "DMIC2DAT" },
1838        { "DMIC2R", NULL, "CLK_SYS" },
1839
1840        { "ADCL", NULL, "AIF1CLK" },
1841        { "ADCL", NULL, "DSP1CLK" },
1842        { "ADCL", NULL, "DSPINTCLK" },
1843
1844        { "ADCR", NULL, "AIF1CLK" },
1845        { "ADCR", NULL, "DSP1CLK" },
1846        { "ADCR", NULL, "DSPINTCLK" },
1847
1848        { "ADCL Mux", "ADC", "ADCL" },
1849        { "ADCL Mux", "DMIC", "DMIC1L" },
1850        { "ADCR Mux", "ADC", "ADCR" },
1851        { "ADCR Mux", "DMIC", "DMIC1R" },
1852
1853        { "DAC1L", NULL, "AIF1CLK" },
1854        { "DAC1L", NULL, "DSP1CLK" },
1855        { "DAC1L", NULL, "DSPINTCLK" },
1856
1857        { "DAC1R", NULL, "AIF1CLK" },
1858        { "DAC1R", NULL, "DSP1CLK" },
1859        { "DAC1R", NULL, "DSPINTCLK" },
1860
1861        { "DAC2L", NULL, "AIF2CLK" },
1862        { "DAC2L", NULL, "DSP2CLK" },
1863        { "DAC2L", NULL, "DSPINTCLK" },
1864
1865        { "DAC2R", NULL, "AIF2DACR" },
1866        { "DAC2R", NULL, "AIF2CLK" },
1867        { "DAC2R", NULL, "DSP2CLK" },
1868        { "DAC2R", NULL, "DSPINTCLK" },
1869
1870        { "TOCLK", NULL, "CLK_SYS" },
1871
1872        { "AIF1DACDAT", NULL, "AIF1 Playback" },
1873        { "AIF2DACDAT", NULL, "AIF2 Playback" },
1874        { "AIF3DACDAT", NULL, "AIF3 Playback" },
1875
1876        { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1877        { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1878        { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1879
1880        /* AIF1 outputs */
1881        { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1882        { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1883        { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884
1885        { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1886        { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1887        { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1888
1889        { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1890        { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1891        { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1892
1893        { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1894        { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1895        { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1896
1897        /* Pin level routing for AIF3 */
1898        { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1899        { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1900        { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1901        { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1902
1903        { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1904        { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1905        { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1906        { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1907        { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1908        { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1909        { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1910
1911        /* DAC1 inputs */
1912        { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1913        { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1914        { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1915        { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1916        { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1917
1918        { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1919        { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1920        { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1921        { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1922        { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1923
1924        /* DAC2/AIF2 outputs  */
1925        { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1926        { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1927        { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1928        { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1929        { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1930        { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1931
1932        { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1933        { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1934        { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1935        { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1936        { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1937        { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1938
1939        { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1940        { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1941        { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1942        { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1943
1944        { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1945
1946        /* AIF3 output */
1947        { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
1948        { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
1949        { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
1950        { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
1951        { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1952        { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1953        { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
1954        { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
1955
1956        { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
1957
1958        /* Loopback */
1959        { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1960        { "AIF1 Loopback", "None", "AIF1DACDAT" },
1961        { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1962        { "AIF2 Loopback", "None", "AIF2DACDAT" },
1963
1964        /* Sidetone */
1965        { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1966        { "Left Sidetone", "DMIC2", "DMIC2L" },
1967        { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1968        { "Right Sidetone", "DMIC2", "DMIC2R" },
1969
1970        /* Output stages */
1971        { "Left Output Mixer", "DAC Switch", "DAC1L" },
1972        { "Right Output Mixer", "DAC Switch", "DAC1R" },
1973
1974        { "SPKL", "DAC1 Switch", "DAC1L" },
1975        { "SPKL", "DAC2 Switch", "DAC2L" },
1976
1977        { "SPKR", "DAC1 Switch", "DAC1R" },
1978        { "SPKR", "DAC2 Switch", "DAC2R" },
1979
1980        { "Left Headphone Mux", "DAC", "DAC1L" },
1981        { "Right Headphone Mux", "DAC", "DAC1R" },
1982};
1983
1984static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1985        { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1986        { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1987        { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1988        { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1989        { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1990        { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1991        { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1992        { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1993};
1994
1995static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1996        { "DAC1L", NULL, "DAC1L Mixer" },
1997        { "DAC1R", NULL, "DAC1R Mixer" },
1998        { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1999        { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2000};
2001
2002static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2003        { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2004        { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2005        { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2006        { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2007        { "MICBIAS1", NULL, "CLK_SYS" },
2008        { "MICBIAS1", NULL, "MICBIAS Supply" },
2009        { "MICBIAS2", NULL, "CLK_SYS" },
2010        { "MICBIAS2", NULL, "MICBIAS Supply" },
2011};
2012
2013static const struct snd_soc_dapm_route wm8994_intercon[] = {
2014        { "AIF2DACL", NULL, "AIF2DAC Mux" },
2015        { "AIF2DACR", NULL, "AIF2DAC Mux" },
2016        { "MICBIAS1", NULL, "VMID" },
2017        { "MICBIAS2", NULL, "VMID" },
2018};
2019
2020static const struct snd_soc_dapm_route wm8958_intercon[] = {
2021        { "AIF2DACL", NULL, "AIF2DACL Mux" },
2022        { "AIF2DACR", NULL, "AIF2DACR Mux" },
2023
2024        { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2025        { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2026        { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2027        { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2028
2029        { "AIF3DACDAT", NULL, "AIF3" },
2030        { "AIF3ADCDAT", NULL, "AIF3" },
2031
2032        { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2033        { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2034
2035        { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2036};
2037
2038/* The size in bits of the FLL divide multiplied by 10
2039 * to allow rounding later */
2040#define FIXED_FLL_SIZE ((1 << 16) * 10)
2041
2042struct fll_div {
2043        u16 outdiv;
2044        u16 n;
2045        u16 k;
2046        u16 lambda;
2047        u16 clk_ref_div;
2048        u16 fll_fratio;
2049};
2050
2051static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2052                                 int freq_in, int freq_out)
2053{
2054        u64 Kpart;
2055        unsigned int K, Ndiv, Nmod, gcd_fll;
2056
2057        pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2058
2059        /* Scale the input frequency down to <= 13.5MHz */
2060        fll->clk_ref_div = 0;
2061        while (freq_in > 13500000) {
2062                fll->clk_ref_div++;
2063                freq_in /= 2;
2064
2065                if (fll->clk_ref_div > 3)
2066                        return -EINVAL;
2067        }
2068        pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2069
2070        /* Scale the output to give 90MHz<=Fvco<=100MHz */
2071        fll->outdiv = 3;
2072        while (freq_out * (fll->outdiv + 1) < 90000000) {
2073                fll->outdiv++;
2074                if (fll->outdiv > 63)
2075                        return -EINVAL;
2076        }
2077        freq_out *= fll->outdiv + 1;
2078        pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2079
2080        if (freq_in > 1000000) {
2081                fll->fll_fratio = 0;
2082        } else if (freq_in > 256000) {
2083                fll->fll_fratio = 1;
2084                freq_in *= 2;
2085        } else if (freq_in > 128000) {
2086                fll->fll_fratio = 2;
2087                freq_in *= 4;
2088        } else if (freq_in > 64000) {
2089                fll->fll_fratio = 3;
2090                freq_in *= 8;
2091        } else {
2092                fll->fll_fratio = 4;
2093                freq_in *= 16;
2094        }
2095        pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2096
2097        /* Now, calculate N.K */
2098        Ndiv = freq_out / freq_in;
2099
2100        fll->n = Ndiv;
2101        Nmod = freq_out % freq_in;
2102        pr_debug("Nmod=%d\n", Nmod);
2103
2104        switch (control->type) {
2105        case WM8994:
2106                /* Calculate fractional part - scale up so we can round. */
2107                Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2108
2109                do_div(Kpart, freq_in);
2110
2111                K = Kpart & 0xFFFFFFFF;
2112
2113                if ((K % 10) >= 5)
2114                        K += 5;
2115
2116                /* Move down to proper range now rounding is done */
2117                fll->k = K / 10;
2118                fll->lambda = 0;
2119
2120                pr_debug("N=%x K=%x\n", fll->n, fll->k);
2121                break;
2122
2123        default:
2124                gcd_fll = gcd(freq_out, freq_in);
2125
2126                fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2127                fll->lambda = freq_in / gcd_fll;
2128                
2129        }
2130
2131        return 0;
2132}
2133
2134static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
2135                          unsigned int freq_in, unsigned int freq_out)
2136{
2137        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2138        struct wm8994 *control = wm8994->wm8994;
2139        int reg_offset, ret;
2140        struct fll_div fll;
2141        u16 reg, clk1, aif_reg, aif_src;
2142        unsigned long timeout;
2143        bool was_enabled;
2144
2145        switch (id) {
2146        case WM8994_FLL1:
2147                reg_offset = 0;
2148                id = 0;
2149                aif_src = 0x10;
2150                break;
2151        case WM8994_FLL2:
2152                reg_offset = 0x20;
2153                id = 1;
2154                aif_src = 0x18;
2155                break;
2156        default:
2157                return -EINVAL;
2158        }
2159
2160        reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2161        was_enabled = reg & WM8994_FLL1_ENA;
2162
2163        switch (src) {
2164        case 0:
2165                /* Allow no source specification when stopping */
2166                if (freq_out)
2167                        return -EINVAL;
2168                src = wm8994->fll[id].src;
2169                break;
2170        case WM8994_FLL_SRC_MCLK1:
2171        case WM8994_FLL_SRC_MCLK2:
2172        case WM8994_FLL_SRC_LRCLK:
2173        case WM8994_FLL_SRC_BCLK:
2174                break;
2175        case WM8994_FLL_SRC_INTERNAL:
2176                freq_in = 12000000;
2177                freq_out = 12000000;
2178                break;
2179        default:
2180                return -EINVAL;
2181        }
2182
2183        /* Are we changing anything? */
2184        if (wm8994->fll[id].src == src &&
2185            wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2186                return 0;
2187
2188        /* If we're stopping the FLL redo the old config - no
2189         * registers will actually be written but we avoid GCC flow
2190         * analysis bugs spewing warnings.
2191         */
2192        if (freq_out)
2193                ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2194        else
2195                ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2196                                            wm8994->fll[id].out);
2197        if (ret < 0)
2198                return ret;
2199
2200        /* Make sure that we're not providing SYSCLK right now */
2201        clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1);
2202        if (clk1 & WM8994_SYSCLK_SRC)
2203                aif_reg = WM8994_AIF2_CLOCKING_1;
2204        else
2205                aif_reg = WM8994_AIF1_CLOCKING_1;
2206        reg = snd_soc_component_read32(component, aif_reg);
2207
2208        if ((reg & WM8994_AIF1CLK_ENA) &&
2209            (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2210                dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
2211                        id + 1);
2212                return -EBUSY;
2213        }
2214
2215        /* We always need to disable the FLL while reconfiguring */
2216        snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2217                            WM8994_FLL1_ENA, 0);
2218
2219        if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2220            freq_in == freq_out && freq_out) {
2221                dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
2222                snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2223                                    WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2224                goto out;
2225        }
2226
2227        reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2228                (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2229        snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
2230                            WM8994_FLL1_OUTDIV_MASK |
2231                            WM8994_FLL1_FRATIO_MASK, reg);
2232
2233        snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
2234                            WM8994_FLL1_K_MASK, fll.k);
2235
2236        snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
2237                            WM8994_FLL1_N_MASK,
2238                            fll.n << WM8994_FLL1_N_SHIFT);
2239
2240        if (fll.lambda) {
2241                snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
2242                                    WM8958_FLL1_LAMBDA_MASK,
2243                                    fll.lambda);
2244                snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2245                                    WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2246        } else {
2247                snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2248                                    WM8958_FLL1_EFS_ENA, 0);
2249        }
2250
2251        snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2252                            WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2253                            WM8994_FLL1_REFCLK_DIV_MASK |
2254                            WM8994_FLL1_REFCLK_SRC_MASK,
2255                            ((src == WM8994_FLL_SRC_INTERNAL)
2256                             << WM8994_FLL1_FRC_NCO_SHIFT) |
2257                            (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2258                            (src - 1));
2259
2260        /* Clear any pending completion from a previous failure */
2261        try_wait_for_completion(&wm8994->fll_locked[id]);
2262
2263        /* Enable (with fractional mode if required) */
2264        if (freq_out) {
2265                /* Enable VMID if we need it */
2266                if (!was_enabled) {
2267                        active_reference(component);
2268
2269                        switch (control->type) {
2270                        case WM8994:
2271                                vmid_reference(component);
2272                                break;
2273                        case WM8958:
2274                                if (control->revision < 1)
2275                                        vmid_reference(component);
2276                                break;
2277                        default:
2278                                break;
2279                        }
2280                }
2281
2282                reg = WM8994_FLL1_ENA;
2283
2284                if (fll.k)
2285                        reg |= WM8994_FLL1_FRAC;
2286                if (src == WM8994_FLL_SRC_INTERNAL)
2287                        reg |= WM8994_FLL1_OSC_ENA;
2288
2289                snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2290                                    WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2291                                    WM8994_FLL1_FRAC, reg);
2292
2293                if (wm8994->fll_locked_irq) {
2294                        timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2295                                                              msecs_to_jiffies(10));
2296                        if (timeout == 0)
2297                                dev_warn(component->dev,
2298                                         "Timed out waiting for FLL lock\n");
2299                } else {
2300                        msleep(5);
2301                }
2302        } else {
2303                if (was_enabled) {
2304                        switch (control->type) {
2305                        case WM8994:
2306                                vmid_dereference(component);
2307                                break;
2308                        case WM8958:
2309                                if (control->revision < 1)
2310                                        vmid_dereference(component);
2311                                break;
2312                        default:
2313                                break;
2314                        }
2315
2316                        active_dereference(component);
2317                }
2318        }
2319
2320out:
2321        wm8994->fll[id].in = freq_in;
2322        wm8994->fll[id].out = freq_out;
2323        wm8994->fll[id].src = src;
2324
2325        configure_clock(component);
2326
2327        /*
2328         * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2329         * for detection.
2330         */
2331        if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2332                dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2333
2334                wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2335                        & WM8994_AIF1CLK_RATE_MASK;
2336                wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2337                        & WM8994_AIF1CLK_RATE_MASK;
2338
2339                snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2340                                    WM8994_AIF1CLK_RATE_MASK, 0x1);
2341                snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2342                                    WM8994_AIF2CLK_RATE_MASK, 0x1);
2343        } else if (wm8994->aifdiv[0]) {
2344                snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2345                                    WM8994_AIF1CLK_RATE_MASK,
2346                                    wm8994->aifdiv[0]);
2347                snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2348                                    WM8994_AIF2CLK_RATE_MASK,
2349                                    wm8994->aifdiv[1]);
2350
2351                wm8994->aifdiv[0] = 0;
2352                wm8994->aifdiv[1] = 0;
2353        }
2354
2355        return 0;
2356}
2357
2358static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2359{
2360        struct completion *completion = data;
2361
2362        complete(completion);
2363
2364        return IRQ_HANDLED;
2365}
2366
2367static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2368
2369static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2370                          unsigned int freq_in, unsigned int freq_out)
2371{
2372        return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
2373}
2374
2375static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2376                int clk_id, unsigned int freq, int dir)
2377{
2378        struct snd_soc_component *component = dai->component;
2379        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2380        int i;
2381
2382        switch (dai->id) {
2383        case 1:
2384        case 2:
2385                break;
2386
2387        default:
2388                /* AIF3 shares clocking with AIF1/2 */
2389                return -EINVAL;
2390        }
2391
2392        switch (clk_id) {
2393        case WM8994_SYSCLK_MCLK1:
2394                wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2395                wm8994->mclk[0] = freq;
2396                dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2397                        dai->id, freq);
2398                break;
2399
2400        case WM8994_SYSCLK_MCLK2:
2401                /* TODO: Set GPIO AF */
2402                wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2403                wm8994->mclk[1] = freq;
2404                dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2405                        dai->id, freq);
2406                break;
2407
2408        case WM8994_SYSCLK_FLL1:
2409                wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2410                dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2411                break;
2412
2413        case WM8994_SYSCLK_FLL2:
2414                wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2415                dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2416                break;
2417
2418        case WM8994_SYSCLK_OPCLK:
2419                /* Special case - a division (times 10) is given and
2420                 * no effect on main clocking.
2421                 */
2422                if (freq) {
2423                        for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2424                                if (opclk_divs[i] == freq)
2425                                        break;
2426                        if (i == ARRAY_SIZE(opclk_divs))
2427                                return -EINVAL;
2428                        snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
2429                                            WM8994_OPCLK_DIV_MASK, i);
2430                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2431                                            WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2432                } else {
2433                        snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2434                                            WM8994_OPCLK_ENA, 0);
2435                }
2436                break;
2437
2438        default:
2439                return -EINVAL;
2440        }
2441
2442        configure_clock(component);
2443
2444        /*
2445         * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2446         * for detection.
2447         */
2448        if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2449                dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2450
2451                wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2452                        & WM8994_AIF1CLK_RATE_MASK;
2453                wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2454                        & WM8994_AIF1CLK_RATE_MASK;
2455
2456                snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2457                                    WM8994_AIF1CLK_RATE_MASK, 0x1);
2458                snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2459                                    WM8994_AIF2CLK_RATE_MASK, 0x1);
2460        } else if (wm8994->aifdiv[0]) {
2461                snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2462                                    WM8994_AIF1CLK_RATE_MASK,
2463                                    wm8994->aifdiv[0]);
2464                snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2465                                    WM8994_AIF2CLK_RATE_MASK,
2466                                    wm8994->aifdiv[1]);
2467
2468                wm8994->aifdiv[0] = 0;
2469                wm8994->aifdiv[1] = 0;
2470        }
2471
2472        return 0;
2473}
2474
2475static int wm8994_set_bias_level(struct snd_soc_component *component,
2476                                 enum snd_soc_bias_level level)
2477{
2478        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2479        struct wm8994 *control = wm8994->wm8994;
2480
2481        wm_hubs_set_bias_level(component, level);
2482
2483        switch (level) {
2484        case SND_SOC_BIAS_ON:
2485                break;
2486
2487        case SND_SOC_BIAS_PREPARE:
2488                /* MICBIAS into regulating mode */
2489                switch (control->type) {
2490                case WM8958:
2491                case WM1811:
2492                        snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2493                                            WM8958_MICB1_MODE, 0);
2494                        snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2495                                            WM8958_MICB2_MODE, 0);
2496                        break;
2497                default:
2498                        break;
2499                }
2500
2501                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2502                        active_reference(component);
2503                break;
2504
2505        case SND_SOC_BIAS_STANDBY:
2506                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2507                        switch (control->type) {
2508                        case WM8958:
2509                                if (control->revision == 0) {
2510                                        /* Optimise performance for rev A */
2511                                        snd_soc_component_update_bits(component,
2512                                                            WM8958_CHARGE_PUMP_2,
2513                                                            WM8958_CP_DISCH,
2514                                                            WM8958_CP_DISCH);
2515                                }
2516                                break;
2517
2518                        default:
2519                                break;
2520                        }
2521
2522                        /* Discharge LINEOUT1 & 2 */
2523                        snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
2524                                            WM8994_LINEOUT1_DISCH |
2525                                            WM8994_LINEOUT2_DISCH,
2526                                            WM8994_LINEOUT1_DISCH |
2527                                            WM8994_LINEOUT2_DISCH);
2528                }
2529
2530                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
2531                        active_dereference(component);
2532
2533                /* MICBIAS into bypass mode on newer devices */
2534                switch (control->type) {
2535                case WM8958:
2536                case WM1811:
2537                        snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2538                                            WM8958_MICB1_MODE,
2539                                            WM8958_MICB1_MODE);
2540                        snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2541                                            WM8958_MICB2_MODE,
2542                                            WM8958_MICB2_MODE);
2543                        break;
2544                default:
2545                        break;
2546                }
2547                break;
2548
2549        case SND_SOC_BIAS_OFF:
2550                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2551                        wm8994->cur_fw = NULL;
2552                break;
2553        }
2554
2555        return 0;
2556}
2557
2558int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
2559{
2560        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2561        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2562
2563        switch (mode) {
2564        case WM8994_VMID_NORMAL:
2565                snd_soc_dapm_mutex_lock(dapm);
2566
2567                if (wm8994->hubs.lineout1_se) {
2568                        snd_soc_dapm_disable_pin_unlocked(dapm,
2569                                                          "LINEOUT1N Driver");
2570                        snd_soc_dapm_disable_pin_unlocked(dapm,
2571                                                          "LINEOUT1P Driver");
2572                }
2573                if (wm8994->hubs.lineout2_se) {
2574                        snd_soc_dapm_disable_pin_unlocked(dapm,
2575                                                          "LINEOUT2N Driver");
2576                        snd_soc_dapm_disable_pin_unlocked(dapm,
2577                                                          "LINEOUT2P Driver");
2578                }
2579
2580                /* Do the sync with the old mode to allow it to clean up */
2581                snd_soc_dapm_sync_unlocked(dapm);
2582                wm8994->vmid_mode = mode;
2583
2584                snd_soc_dapm_mutex_unlock(dapm);
2585                break;
2586
2587        case WM8994_VMID_FORCE:
2588                snd_soc_dapm_mutex_lock(dapm);
2589
2590                if (wm8994->hubs.lineout1_se) {
2591                        snd_soc_dapm_force_enable_pin_unlocked(dapm,
2592                                                               "LINEOUT1N Driver");
2593                        snd_soc_dapm_force_enable_pin_unlocked(dapm,
2594                                                               "LINEOUT1P Driver");
2595                }
2596                if (wm8994->hubs.lineout2_se) {
2597                        snd_soc_dapm_force_enable_pin_unlocked(dapm,
2598                                                               "LINEOUT2N Driver");
2599                        snd_soc_dapm_force_enable_pin_unlocked(dapm,
2600                                                               "LINEOUT2P Driver");
2601                }
2602
2603                wm8994->vmid_mode = mode;
2604                snd_soc_dapm_sync_unlocked(dapm);
2605
2606                snd_soc_dapm_mutex_unlock(dapm);
2607                break;
2608
2609        default:
2610                return -EINVAL;
2611        }
2612
2613        return 0;
2614}
2615
2616static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2617{
2618        struct snd_soc_component *component = dai->component;
2619        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2620        struct wm8994 *control = wm8994->wm8994;
2621        int ms_reg;
2622        int aif1_reg;
2623        int dac_reg;
2624        int adc_reg;
2625        int ms = 0;
2626        int aif1 = 0;
2627        int lrclk = 0;
2628
2629        switch (dai->id) {
2630        case 1:
2631                ms_reg = WM8994_AIF1_MASTER_SLAVE;
2632                aif1_reg = WM8994_AIF1_CONTROL_1;
2633                dac_reg = WM8994_AIF1DAC_LRCLK;
2634                adc_reg = WM8994_AIF1ADC_LRCLK;
2635                break;
2636        case 2:
2637                ms_reg = WM8994_AIF2_MASTER_SLAVE;
2638                aif1_reg = WM8994_AIF2_CONTROL_1;
2639                dac_reg = WM8994_AIF1DAC_LRCLK;
2640                adc_reg = WM8994_AIF1ADC_LRCLK;
2641                break;
2642        default:
2643                return -EINVAL;
2644        }
2645
2646        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2647        case SND_SOC_DAIFMT_CBS_CFS:
2648                break;
2649        case SND_SOC_DAIFMT_CBM_CFM:
2650                ms = WM8994_AIF1_MSTR;
2651                break;
2652        default:
2653                return -EINVAL;
2654        }
2655
2656        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2657        case SND_SOC_DAIFMT_DSP_B:
2658                aif1 |= WM8994_AIF1_LRCLK_INV;
2659                lrclk |= WM8958_AIF1_LRCLK_INV;
2660                /* fall through */
2661        case SND_SOC_DAIFMT_DSP_A:
2662                aif1 |= 0x18;
2663                break;
2664        case SND_SOC_DAIFMT_I2S:
2665                aif1 |= 0x10;
2666                break;
2667        case SND_SOC_DAIFMT_RIGHT_J:
2668                break;
2669        case SND_SOC_DAIFMT_LEFT_J:
2670                aif1 |= 0x8;
2671                break;
2672        default:
2673                return -EINVAL;
2674        }
2675
2676        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2677        case SND_SOC_DAIFMT_DSP_A:
2678        case SND_SOC_DAIFMT_DSP_B:
2679                /* frame inversion not valid for DSP modes */
2680                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2681                case SND_SOC_DAIFMT_NB_NF:
2682                        break;
2683                case SND_SOC_DAIFMT_IB_NF:
2684                        aif1 |= WM8994_AIF1_BCLK_INV;
2685                        break;
2686                default:
2687                        return -EINVAL;
2688                }
2689                break;
2690
2691        case SND_SOC_DAIFMT_I2S:
2692        case SND_SOC_DAIFMT_RIGHT_J:
2693        case SND_SOC_DAIFMT_LEFT_J:
2694                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2695                case SND_SOC_DAIFMT_NB_NF:
2696                        break;
2697                case SND_SOC_DAIFMT_IB_IF:
2698                        aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2699                        lrclk |= WM8958_AIF1_LRCLK_INV;
2700                        break;
2701                case SND_SOC_DAIFMT_IB_NF:
2702                        aif1 |= WM8994_AIF1_BCLK_INV;
2703                        break;
2704                case SND_SOC_DAIFMT_NB_IF:
2705                        aif1 |= WM8994_AIF1_LRCLK_INV;
2706                        lrclk |= WM8958_AIF1_LRCLK_INV;
2707                        break;
2708                default:
2709                        return -EINVAL;
2710                }
2711                break;
2712        default:
2713                return -EINVAL;
2714        }
2715
2716        /* The AIF2 format configuration needs to be mirrored to AIF3
2717         * on WM8958 if it's in use so just do it all the time. */
2718        switch (control->type) {
2719        case WM1811:
2720        case WM8958:
2721                if (dai->id == 2)
2722                        snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
2723                                            WM8994_AIF1_LRCLK_INV |
2724                                            WM8958_AIF3_FMT_MASK, aif1);
2725                break;
2726
2727        default:
2728                break;
2729        }
2730
2731        snd_soc_component_update_bits(component, aif1_reg,
2732                            WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2733                            WM8994_AIF1_FMT_MASK,
2734                            aif1);
2735        snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
2736                            ms);
2737        snd_soc_component_update_bits(component, dac_reg,
2738                            WM8958_AIF1_LRCLK_INV, lrclk);
2739        snd_soc_component_update_bits(component, adc_reg,
2740                            WM8958_AIF1_LRCLK_INV, lrclk);
2741
2742        return 0;
2743}
2744
2745static struct {
2746        int val, rate;
2747} srs[] = {
2748        { 0,   8000 },
2749        { 1,  11025 },
2750        { 2,  12000 },
2751        { 3,  16000 },
2752        { 4,  22050 },
2753        { 5,  24000 },
2754        { 6,  32000 },
2755        { 7,  44100 },
2756        { 8,  48000 },
2757        { 9,  88200 },
2758        { 10, 96000 },
2759};
2760
2761static int fs_ratios[] = {
2762        64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2763};
2764
2765static int bclk_divs[] = {
2766        10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2767        640, 880, 960, 1280, 1760, 1920
2768};
2769
2770static int wm8994_hw_params(struct snd_pcm_substream *substream,
2771                            struct snd_pcm_hw_params *params,
2772                            struct snd_soc_dai *dai)
2773{
2774        struct snd_soc_component *component = dai->component;
2775        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2776        struct wm8994 *control = wm8994->wm8994;
2777        struct wm8994_pdata *pdata = &control->pdata;
2778        int aif1_reg;
2779        int aif2_reg;
2780        int bclk_reg;
2781        int lrclk_reg;
2782        int rate_reg;
2783        int aif1 = 0;
2784        int aif2 = 0;
2785        int bclk = 0;
2786        int lrclk = 0;
2787        int rate_val = 0;
2788        int id = dai->id - 1;
2789
2790        int i, cur_val, best_val, bclk_rate, best;
2791
2792        switch (dai->id) {
2793        case 1:
2794                aif1_reg = WM8994_AIF1_CONTROL_1;
2795                aif2_reg = WM8994_AIF1_CONTROL_2;
2796                bclk_reg = WM8994_AIF1_BCLK;
2797                rate_reg = WM8994_AIF1_RATE;
2798                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2799                    wm8994->lrclk_shared[0]) {
2800                        lrclk_reg = WM8994_AIF1DAC_LRCLK;
2801                } else {
2802                        lrclk_reg = WM8994_AIF1ADC_LRCLK;
2803                        dev_dbg(component->dev, "AIF1 using split LRCLK\n");
2804                }
2805                break;
2806        case 2:
2807                aif1_reg = WM8994_AIF2_CONTROL_1;
2808                aif2_reg = WM8994_AIF2_CONTROL_2;
2809                bclk_reg = WM8994_AIF2_BCLK;
2810                rate_reg = WM8994_AIF2_RATE;
2811                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2812                    wm8994->lrclk_shared[1]) {
2813                        lrclk_reg = WM8994_AIF2DAC_LRCLK;
2814                } else {
2815                        lrclk_reg = WM8994_AIF2ADC_LRCLK;
2816                        dev_dbg(component->dev, "AIF2 using split LRCLK\n");
2817                }
2818                break;
2819        default:
2820                return -EINVAL;
2821        }
2822
2823        bclk_rate = params_rate(params);
2824        switch (params_width(params)) {
2825        case 16:
2826                bclk_rate *= 16;
2827                break;
2828        case 20:
2829                bclk_rate *= 20;
2830                aif1 |= 0x20;
2831                break;
2832        case 24:
2833                bclk_rate *= 24;
2834                aif1 |= 0x40;
2835                break;
2836        case 32:
2837                bclk_rate *= 32;
2838                aif1 |= 0x60;
2839                break;
2840        default:
2841                return -EINVAL;
2842        }
2843
2844        wm8994->channels[id] = params_channels(params);
2845        if (pdata->max_channels_clocked[id] &&
2846            wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2847                dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2848                        pdata->max_channels_clocked[id], wm8994->channels[id]);
2849                wm8994->channels[id] = pdata->max_channels_clocked[id];
2850        }
2851
2852        switch (wm8994->channels[id]) {
2853        case 1:
2854        case 2:
2855                bclk_rate *= 2;
2856                break;
2857        default:
2858                bclk_rate *= 4;
2859                break;
2860        }
2861
2862        /* Try to find an appropriate sample rate; look for an exact match. */
2863        for (i = 0; i < ARRAY_SIZE(srs); i++)
2864                if (srs[i].rate == params_rate(params))
2865                        break;
2866        if (i == ARRAY_SIZE(srs))
2867                return -EINVAL;
2868        rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2869
2870        dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2871        dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2872                dai->id, wm8994->aifclk[id], bclk_rate);
2873
2874        if (wm8994->channels[id] == 1 &&
2875            (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18)
2876                aif2 |= WM8994_AIF1_MONO;
2877
2878        if (wm8994->aifclk[id] == 0) {
2879                dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2880                return -EINVAL;
2881        }
2882
2883        /* AIFCLK/fs ratio; look for a close match in either direction */
2884        best = 0;
2885        best_val = abs((fs_ratios[0] * params_rate(params))
2886                       - wm8994->aifclk[id]);
2887        for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2888                cur_val = abs((fs_ratios[i] * params_rate(params))
2889                              - wm8994->aifclk[id]);
2890                if (cur_val >= best_val)
2891                        continue;
2892                best = i;
2893                best_val = cur_val;
2894        }
2895        dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2896                dai->id, fs_ratios[best]);
2897        rate_val |= best;
2898
2899        /* We may not get quite the right frequency if using
2900         * approximate clocks so look for the closest match that is
2901         * higher than the target (we need to ensure that there enough
2902         * BCLKs to clock out the samples).
2903         */
2904        best = 0;
2905        for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2906                cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2907                if (cur_val < 0) /* BCLK table is sorted */
2908                        break;
2909                best = i;
2910        }
2911        bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2912        dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2913                bclk_divs[best], bclk_rate);
2914        bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2915
2916        lrclk = bclk_rate / params_rate(params);
2917        if (!lrclk) {
2918                dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2919                        bclk_rate);
2920                return -EINVAL;
2921        }
2922        dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2923                lrclk, bclk_rate / lrclk);
2924
2925        snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2926        snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
2927        snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2928        snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2929                            lrclk);
2930        snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
2931                            WM8994_AIF1CLK_RATE_MASK, rate_val);
2932
2933        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2934                switch (dai->id) {
2935                case 1:
2936                        wm8994->dac_rates[0] = params_rate(params);
2937                        wm8994_set_retune_mobile(component, 0);
2938                        wm8994_set_retune_mobile(component, 1);
2939                        break;
2940                case 2:
2941                        wm8994->dac_rates[1] = params_rate(params);
2942                        wm8994_set_retune_mobile(component, 2);
2943                        break;
2944                }
2945        }
2946
2947        return 0;
2948}
2949
2950static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2951                                 struct snd_pcm_hw_params *params,
2952                                 struct snd_soc_dai *dai)
2953{
2954        struct snd_soc_component *component = dai->component;
2955        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2956        struct wm8994 *control = wm8994->wm8994;
2957        int aif1_reg;
2958        int aif1 = 0;
2959
2960        switch (dai->id) {
2961        case 3:
2962                switch (control->type) {
2963                case WM1811:
2964                case WM8958:
2965                        aif1_reg = WM8958_AIF3_CONTROL_1;
2966                        break;
2967                default:
2968                        return 0;
2969                }
2970                break;
2971        default:
2972                return 0;
2973        }
2974
2975        switch (params_width(params)) {
2976        case 16:
2977                break;
2978        case 20:
2979                aif1 |= 0x20;
2980                break;
2981        case 24:
2982                aif1 |= 0x40;
2983                break;
2984        case 32:
2985                aif1 |= 0x60;
2986                break;
2987        default:
2988                return -EINVAL;
2989        }
2990
2991        return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2992}
2993
2994static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2995{
2996        struct snd_soc_component *component = codec_dai->component;
2997        int mute_reg;
2998        int reg;
2999
3000        switch (codec_dai->id) {
3001        case 1:
3002                mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3003                break;
3004        case 2:
3005                mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3006                break;
3007        default:
3008                return -EINVAL;
3009        }
3010
3011        if (mute)
3012                reg = WM8994_AIF1DAC1_MUTE;
3013        else
3014                reg = 0;
3015
3016        snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3017
3018        return 0;
3019}
3020
3021static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3022{
3023        struct snd_soc_component *component = codec_dai->component;
3024        int reg, val, mask;
3025
3026        switch (codec_dai->id) {
3027        case 1:
3028                reg = WM8994_AIF1_MASTER_SLAVE;
3029                mask = WM8994_AIF1_TRI;
3030                break;
3031        case 2:
3032                reg = WM8994_AIF2_MASTER_SLAVE;
3033                mask = WM8994_AIF2_TRI;
3034                break;
3035        default:
3036                return -EINVAL;
3037        }
3038
3039        if (tristate)
3040                val = mask;
3041        else
3042                val = 0;
3043
3044        return snd_soc_component_update_bits(component, reg, mask, val);
3045}
3046
3047static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3048{
3049        struct snd_soc_component *component = dai->component;
3050
3051        /* Disable the pulls on the AIF if we're using it to save power. */
3052        snd_soc_component_update_bits(component, WM8994_GPIO_3,
3053                            WM8994_GPN_PU | WM8994_GPN_PD, 0);
3054        snd_soc_component_update_bits(component, WM8994_GPIO_4,
3055                            WM8994_GPN_PU | WM8994_GPN_PD, 0);
3056        snd_soc_component_update_bits(component, WM8994_GPIO_5,
3057                            WM8994_GPN_PU | WM8994_GPN_PD, 0);
3058
3059        return 0;
3060}
3061
3062#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3063
3064#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3065                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3066
3067static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3068        .set_sysclk     = wm8994_set_dai_sysclk,
3069        .set_fmt        = wm8994_set_dai_fmt,
3070        .hw_params      = wm8994_hw_params,
3071        .digital_mute   = wm8994_aif_mute,
3072        .set_pll        = wm8994_set_fll,
3073        .set_tristate   = wm8994_set_tristate,
3074};
3075
3076static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3077        .set_sysclk     = wm8994_set_dai_sysclk,
3078        .set_fmt        = wm8994_set_dai_fmt,
3079        .hw_params      = wm8994_hw_params,
3080        .digital_mute   = wm8994_aif_mute,
3081        .set_pll        = wm8994_set_fll,
3082        .set_tristate   = wm8994_set_tristate,
3083};
3084
3085static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3086        .hw_params      = wm8994_aif3_hw_params,
3087};
3088
3089static struct snd_soc_dai_driver wm8994_dai[] = {
3090        {
3091                .name = "wm8994-aif1",
3092                .id = 1,
3093                .playback = {
3094                        .stream_name = "AIF1 Playback",
3095                        .channels_min = 1,
3096                        .channels_max = 2,
3097                        .rates = WM8994_RATES,
3098                        .formats = WM8994_FORMATS,
3099                        .sig_bits = 24,
3100                },
3101                .capture = {
3102                        .stream_name = "AIF1 Capture",
3103                        .channels_min = 1,
3104                        .channels_max = 2,
3105                        .rates = WM8994_RATES,
3106                        .formats = WM8994_FORMATS,
3107                        .sig_bits = 24,
3108                 },
3109                .ops = &wm8994_aif1_dai_ops,
3110        },
3111        {
3112                .name = "wm8994-aif2",
3113                .id = 2,
3114                .playback = {
3115                        .stream_name = "AIF2 Playback",
3116                        .channels_min = 1,
3117                        .channels_max = 2,
3118                        .rates = WM8994_RATES,
3119                        .formats = WM8994_FORMATS,
3120                        .sig_bits = 24,
3121                },
3122                .capture = {
3123                        .stream_name = "AIF2 Capture",
3124                        .channels_min = 1,
3125                        .channels_max = 2,
3126                        .rates = WM8994_RATES,
3127                        .formats = WM8994_FORMATS,
3128                        .sig_bits = 24,
3129                },
3130                .probe = wm8994_aif2_probe,
3131                .ops = &wm8994_aif2_dai_ops,
3132        },
3133        {
3134                .name = "wm8994-aif3",
3135                .id = 3,
3136                .playback = {
3137                        .stream_name = "AIF3 Playback",
3138                        .channels_min = 1,
3139                        .channels_max = 2,
3140                        .rates = WM8994_RATES,
3141                        .formats = WM8994_FORMATS,
3142                        .sig_bits = 24,
3143                },
3144                .capture = {
3145                        .stream_name = "AIF3 Capture",
3146                        .channels_min = 1,
3147                        .channels_max = 2,
3148                        .rates = WM8994_RATES,
3149                        .formats = WM8994_FORMATS,
3150                        .sig_bits = 24,
3151                 },
3152                .ops = &wm8994_aif3_dai_ops,
3153        }
3154};
3155
3156#ifdef CONFIG_PM
3157static int wm8994_component_suspend(struct snd_soc_component *component)
3158{
3159        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3160        int i, ret;
3161
3162        for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3163                memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3164                       sizeof(struct wm8994_fll_config));
3165                ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
3166                if (ret < 0)
3167                        dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
3168                                 i + 1, ret);
3169        }
3170
3171        snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3172
3173        return 0;
3174}
3175
3176static int wm8994_component_resume(struct snd_soc_component *component)
3177{
3178        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3179        int i, ret;
3180
3181        for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3182                if (!wm8994->fll_suspend[i].out)
3183                        continue;
3184
3185                ret = _wm8994_set_fll(component, i + 1,
3186                                     wm8994->fll_suspend[i].src,
3187                                     wm8994->fll_suspend[i].in,
3188                                     wm8994->fll_suspend[i].out);
3189                if (ret < 0)
3190                        dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
3191                                 i + 1, ret);
3192        }
3193
3194        return 0;
3195}
3196#else
3197#define wm8994_component_suspend NULL
3198#define wm8994_component_resume NULL
3199#endif
3200
3201static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3202{
3203        struct snd_soc_component *component = wm8994->hubs.component;
3204        struct wm8994 *control = wm8994->wm8994;
3205        struct wm8994_pdata *pdata = &control->pdata;
3206        struct snd_kcontrol_new controls[] = {
3207                SOC_ENUM_EXT("AIF1.1 EQ Mode",
3208                             wm8994->retune_mobile_enum,
3209                             wm8994_get_retune_mobile_enum,
3210                             wm8994_put_retune_mobile_enum),
3211                SOC_ENUM_EXT("AIF1.2 EQ Mode",
3212                             wm8994->retune_mobile_enum,
3213                             wm8994_get_retune_mobile_enum,
3214                             wm8994_put_retune_mobile_enum),
3215                SOC_ENUM_EXT("AIF2 EQ Mode",
3216                             wm8994->retune_mobile_enum,
3217                             wm8994_get_retune_mobile_enum,
3218                             wm8994_put_retune_mobile_enum),
3219        };
3220        int ret, i, j;
3221        const char **t;
3222
3223        /* We need an array of texts for the enum API but the number
3224         * of texts is likely to be less than the number of
3225         * configurations due to the sample rate dependency of the
3226         * configurations. */
3227        wm8994->num_retune_mobile_texts = 0;
3228        wm8994->retune_mobile_texts = NULL;
3229        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3230                for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3231                        if (strcmp(pdata->retune_mobile_cfgs[i].name,
3232                                   wm8994->retune_mobile_texts[j]) == 0)
3233                                break;
3234                }
3235
3236                if (j != wm8994->num_retune_mobile_texts)
3237                        continue;
3238
3239                /* Expand the array... */
3240                t = krealloc(wm8994->retune_mobile_texts,
3241                             sizeof(char *) *
3242                             (wm8994->num_retune_mobile_texts + 1),
3243                             GFP_KERNEL);
3244                if (t == NULL)
3245                        continue;
3246
3247                /* ...store the new entry... */
3248                t[wm8994->num_retune_mobile_texts] =
3249                        pdata->retune_mobile_cfgs[i].name;
3250
3251                /* ...and remember the new version. */
3252                wm8994->num_retune_mobile_texts++;
3253                wm8994->retune_mobile_texts = t;
3254        }
3255
3256        dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
3257                wm8994->num_retune_mobile_texts);
3258
3259        wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3260        wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3261
3262        ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3263                                   ARRAY_SIZE(controls));
3264        if (ret != 0)
3265                dev_err(wm8994->hubs.component->dev,
3266                        "Failed to add ReTune Mobile controls: %d\n", ret);
3267}
3268
3269static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3270{
3271        struct snd_soc_component *component = wm8994->hubs.component;
3272        struct wm8994 *control = wm8994->wm8994;
3273        struct wm8994_pdata *pdata = &control->pdata;
3274        int ret, i;
3275
3276        if (!pdata)
3277                return;
3278
3279        wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
3280                                      pdata->lineout2_diff,
3281                                      pdata->lineout1fb,
3282                                      pdata->lineout2fb,
3283                                      pdata->jd_scthr,
3284                                      pdata->jd_thr,
3285                                      pdata->micb1_delay,
3286                                      pdata->micb2_delay,
3287                                      pdata->micbias1_lvl,
3288                                      pdata->micbias2_lvl);
3289
3290        dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3291
3292        if (pdata->num_drc_cfgs) {
3293                struct snd_kcontrol_new controls[] = {
3294                        SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3295                                     wm8994_get_drc_enum, wm8994_put_drc_enum),
3296                        SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3297                                     wm8994_get_drc_enum, wm8994_put_drc_enum),
3298                        SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3299                                     wm8994_get_drc_enum, wm8994_put_drc_enum),
3300                };
3301
3302                /* We need an array of texts for the enum API */
3303                wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
3304                            pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
3305                if (!wm8994->drc_texts)
3306                        return;
3307
3308                for (i = 0; i < pdata->num_drc_cfgs; i++)
3309                        wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3310
3311                wm8994->drc_enum.items = pdata->num_drc_cfgs;
3312                wm8994->drc_enum.texts = wm8994->drc_texts;
3313
3314                ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3315                                           ARRAY_SIZE(controls));
3316                for (i = 0; i < WM8994_NUM_DRC; i++)
3317                        wm8994_set_drc(component, i);
3318        } else {
3319                ret = snd_soc_add_component_controls(wm8994->hubs.component,
3320                                                 wm8994_drc_controls,
3321                                                 ARRAY_SIZE(wm8994_drc_controls));
3322        }
3323
3324        if (ret != 0)
3325                dev_err(wm8994->hubs.component->dev,
3326                        "Failed to add DRC mode controls: %d\n", ret);
3327
3328
3329        dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
3330                pdata->num_retune_mobile_cfgs);
3331
3332        if (pdata->num_retune_mobile_cfgs)
3333                wm8994_handle_retune_mobile_pdata(wm8994);
3334        else
3335                snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
3336                                     ARRAY_SIZE(wm8994_eq_controls));
3337
3338        for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3339                if (pdata->micbias[i]) {
3340                        snd_soc_component_write(component, WM8958_MICBIAS1 + i,
3341                                pdata->micbias[i] & 0xffff);
3342                }
3343        }
3344}
3345
3346/**
3347 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3348 *
3349 * @component:   WM8994 component
3350 * @jack:    jack to report detection events on
3351 * @micbias: microphone bias to detect on
3352 *
3353 * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3354 * being used to bring out signals to the processor then only platform
3355 * data configuration is needed for WM8994 and processor GPIOs should
3356 * be configured using snd_soc_jack_add_gpios() instead.
3357 *
3358 * Configuration of detection levels is available via the micbias1_lvl
3359 * and micbias2_lvl platform data members.
3360 */
3361int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3362                      int micbias)
3363{
3364        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3365        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3366        struct wm8994_micdet *micdet;
3367        struct wm8994 *control = wm8994->wm8994;
3368        int reg, ret;
3369
3370        if (control->type != WM8994) {
3371                dev_warn(component->dev, "Not a WM8994\n");
3372                return -EINVAL;
3373        }
3374
3375        switch (micbias) {
3376        case 1:
3377                micdet = &wm8994->micdet[0];
3378                if (jack)
3379                        ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3380                else
3381                        ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3382                break;
3383        case 2:
3384                micdet = &wm8994->micdet[1];
3385                if (jack)
3386                        ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3387                else
3388                        ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3389                break;
3390        default:
3391                dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
3392                return -EINVAL;
3393        }
3394
3395        if (ret != 0)
3396                dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
3397                         micbias, ret);
3398
3399        dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
3400                micbias, jack);
3401
3402        /* Store the configuration */
3403        micdet->jack = jack;
3404        micdet->detecting = true;
3405
3406        /* If either of the jacks is set up then enable detection */
3407        if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3408                reg = WM8994_MICD_ENA;
3409        else
3410                reg = 0;
3411
3412        snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3413
3414        /* enable MICDET and MICSHRT deboune */
3415        snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
3416                            WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3417                            WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3418                            WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3419
3420        snd_soc_dapm_sync(dapm);
3421
3422        return 0;
3423}
3424EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3425
3426static void wm8994_mic_work(struct work_struct *work)
3427{
3428        struct wm8994_priv *priv = container_of(work,
3429                                                struct wm8994_priv,
3430                                                mic_work.work);
3431        struct regmap *regmap = priv->wm8994->regmap;
3432        struct device *dev = priv->wm8994->dev;
3433        unsigned int reg;
3434        int ret;
3435        int report;
3436
3437        pm_runtime_get_sync(dev);
3438
3439        ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3440        if (ret < 0) {
3441                dev_err(dev, "Failed to read microphone status: %d\n",
3442                        ret);
3443                pm_runtime_put(dev);
3444                return;
3445        }
3446
3447        dev_dbg(dev, "Microphone status: %x\n", reg);
3448
3449        report = 0;
3450        if (reg & WM8994_MIC1_DET_STS) {
3451                if (priv->micdet[0].detecting)
3452                        report = SND_JACK_HEADSET;
3453        }
3454        if (reg & WM8994_MIC1_SHRT_STS) {
3455                if (priv->micdet[0].detecting)
3456                        report = SND_JACK_HEADPHONE;
3457                else
3458                        report |= SND_JACK_BTN_0;
3459        }
3460        if (report)
3461                priv->micdet[0].detecting = false;
3462        else
3463                priv->micdet[0].detecting = true;
3464
3465        snd_soc_jack_report(priv->micdet[0].jack, report,
3466                            SND_JACK_HEADSET | SND_JACK_BTN_0);
3467
3468        report = 0;
3469        if (reg & WM8994_MIC2_DET_STS) {
3470                if (priv->micdet[1].detecting)
3471                        report = SND_JACK_HEADSET;
3472        }
3473        if (reg & WM8994_MIC2_SHRT_STS) {
3474                if (priv->micdet[1].detecting)
3475                        report = SND_JACK_HEADPHONE;
3476                else
3477                        report |= SND_JACK_BTN_0;
3478        }
3479        if (report)
3480                priv->micdet[1].detecting = false;
3481        else
3482                priv->micdet[1].detecting = true;
3483
3484        snd_soc_jack_report(priv->micdet[1].jack, report,
3485                            SND_JACK_HEADSET | SND_JACK_BTN_0);
3486
3487        pm_runtime_put(dev);
3488}
3489
3490static irqreturn_t wm8994_mic_irq(int irq, void *data)
3491{
3492        struct wm8994_priv *priv = data;
3493        struct snd_soc_component *component = priv->hubs.component;
3494
3495#ifndef CONFIG_SND_SOC_WM8994_MODULE
3496        trace_snd_soc_jack_irq(dev_name(component->dev));
3497#endif
3498
3499        pm_wakeup_event(component->dev, 300);
3500
3501        queue_delayed_work(system_power_efficient_wq,
3502                           &priv->mic_work, msecs_to_jiffies(250));
3503
3504        return IRQ_HANDLED;
3505}
3506
3507/* Should be called with accdet_lock held */
3508static void wm1811_micd_stop(struct snd_soc_component *component)
3509{
3510        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3511        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3512
3513        if (!wm8994->jackdet)
3514                return;
3515
3516        snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3517
3518        wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3519
3520        if (wm8994->wm8994->pdata.jd_ext_cap)
3521                snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3522}
3523
3524static void wm8958_button_det(struct snd_soc_component *component, u16 status)
3525{
3526        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3527        int report;
3528
3529        report = 0;
3530        if (status & 0x4)
3531                report |= SND_JACK_BTN_0;
3532
3533        if (status & 0x8)
3534                report |= SND_JACK_BTN_1;
3535
3536        if (status & 0x10)
3537                report |= SND_JACK_BTN_2;
3538
3539        if (status & 0x20)
3540                report |= SND_JACK_BTN_3;
3541
3542        if (status & 0x40)
3543                report |= SND_JACK_BTN_4;
3544
3545        if (status & 0x80)
3546                report |= SND_JACK_BTN_5;
3547
3548        snd_soc_jack_report(wm8994->micdet[0].jack, report,
3549                            wm8994->btn_mask);
3550}
3551
3552static void wm8958_open_circuit_work(struct work_struct *work)
3553{
3554        struct wm8994_priv *wm8994 = container_of(work,
3555                                                  struct wm8994_priv,
3556                                                  open_circuit_work.work);
3557        struct device *dev = wm8994->wm8994->dev;
3558
3559        mutex_lock(&wm8994->accdet_lock);
3560
3561        wm1811_micd_stop(wm8994->hubs.component);
3562
3563        dev_dbg(dev, "Reporting open circuit\n");
3564
3565        wm8994->jack_mic = false;
3566        wm8994->mic_detecting = true;
3567
3568        wm8958_micd_set_rate(wm8994->hubs.component);
3569
3570        snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3571                            wm8994->btn_mask |
3572                            SND_JACK_HEADSET);
3573
3574        mutex_unlock(&wm8994->accdet_lock);
3575}
3576
3577static void wm8958_mic_id(void *data, u16 status)
3578{
3579        struct snd_soc_component *component = data;
3580        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3581
3582        /* Either nothing present or just starting detection */
3583        if (!(status & WM8958_MICD_STS)) {
3584                /* If nothing present then clear our statuses */
3585                dev_dbg(component->dev, "Detected open circuit\n");
3586
3587                queue_delayed_work(system_power_efficient_wq,
3588                                   &wm8994->open_circuit_work,
3589                                   msecs_to_jiffies(2500));
3590                return;
3591        }
3592
3593        /* If the measurement is showing a high impedence we've got a
3594         * microphone.
3595         */
3596        if (status & 0x600) {
3597                dev_dbg(component->dev, "Detected microphone\n");
3598
3599                wm8994->mic_detecting = false;
3600                wm8994->jack_mic = true;
3601
3602                wm8958_micd_set_rate(component);
3603
3604                snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3605                                    SND_JACK_HEADSET);
3606        }
3607
3608
3609        if (status & 0xfc) {
3610                dev_dbg(component->dev, "Detected headphone\n");
3611                wm8994->mic_detecting = false;
3612
3613                wm8958_micd_set_rate(component);
3614
3615                /* If we have jackdet that will detect removal */
3616                wm1811_micd_stop(component);
3617
3618                snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3619                                    SND_JACK_HEADSET);
3620        }
3621}
3622
3623/* Deferred mic detection to allow for extra settling time */
3624static void wm1811_mic_work(struct work_struct *work)
3625{
3626        struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3627                                                  mic_work.work);
3628        struct wm8994 *control = wm8994->wm8994;
3629        struct snd_soc_component *component = wm8994->hubs.component;
3630        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3631
3632        pm_runtime_get_sync(component->dev);
3633
3634        /* If required for an external cap force MICBIAS on */
3635        if (control->pdata.jd_ext_cap) {
3636                snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
3637                snd_soc_dapm_sync(dapm);
3638        }
3639
3640        mutex_lock(&wm8994->accdet_lock);
3641
3642        dev_dbg(component->dev, "Starting mic detection\n");
3643
3644        /* Use a user-supplied callback if we have one */
3645        if (wm8994->micd_cb) {
3646                wm8994->micd_cb(wm8994->micd_cb_data);
3647        } else {
3648                /*
3649                 * Start off measument of microphone impedence to find out
3650                 * what's actually there.
3651                 */
3652                wm8994->mic_detecting = true;
3653                wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
3654
3655                snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3656                                    WM8958_MICD_ENA, WM8958_MICD_ENA);
3657        }
3658
3659        mutex_unlock(&wm8994->accdet_lock);
3660
3661        pm_runtime_put(component->dev);
3662}
3663
3664static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3665{
3666        struct wm8994_priv *wm8994 = data;
3667        struct wm8994 *control = wm8994->wm8994;
3668        struct snd_soc_component *component = wm8994->hubs.component;
3669        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3670        int reg, delay;
3671        bool present;
3672
3673        pm_runtime_get_sync(component->dev);
3674
3675        cancel_delayed_work_sync(&wm8994->mic_complete_work);
3676
3677        mutex_lock(&wm8994->accdet_lock);
3678
3679        reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3680        if (reg < 0) {
3681                dev_err(component->dev, "Failed to read jack status: %d\n", reg);
3682                mutex_unlock(&wm8994->accdet_lock);
3683                pm_runtime_put(component->dev);
3684                return IRQ_NONE;
3685        }
3686
3687        dev_dbg(component->dev, "JACKDET %x\n", reg);
3688
3689        present = reg & WM1811_JACKDET_LVL;
3690
3691        if (present) {
3692                dev_dbg(component->dev, "Jack detected\n");
3693
3694                wm8958_micd_set_rate(component);
3695
3696                snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3697                                    WM8958_MICB2_DISCH, 0);
3698
3699                /* Disable debounce while inserted */
3700                snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3701                                    WM1811_JACKDET_DB, 0);
3702
3703                delay = control->pdata.micdet_delay;
3704                queue_delayed_work(system_power_efficient_wq,
3705                                   &wm8994->mic_work,
3706                                   msecs_to_jiffies(delay));
3707        } else {
3708                dev_dbg(component->dev, "Jack not detected\n");
3709
3710                cancel_delayed_work_sync(&wm8994->mic_work);
3711
3712                snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3713                                    WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3714
3715                /* Enable debounce while removed */
3716                snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3717                                    WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3718
3719                wm8994->mic_detecting = false;
3720                wm8994->jack_mic = false;
3721                snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3722                                    WM8958_MICD_ENA, 0);
3723                wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3724        }
3725
3726        mutex_unlock(&wm8994->accdet_lock);
3727
3728        /* Turn off MICBIAS if it was on for an external cap */
3729        if (control->pdata.jd_ext_cap && !present)
3730                snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3731
3732        if (present)
3733                snd_soc_jack_report(wm8994->micdet[0].jack,
3734                                    SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3735        else
3736                snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3737                                    SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3738                                    wm8994->btn_mask);
3739
3740        /* Since we only report deltas force an update, ensures we
3741         * avoid bootstrapping issues with the core. */
3742        snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3743
3744        pm_runtime_put(component->dev);
3745        return IRQ_HANDLED;
3746}
3747
3748static void wm1811_jackdet_bootstrap(struct work_struct *work)
3749{
3750        struct wm8994_priv *wm8994 = container_of(work,
3751                                                struct wm8994_priv,
3752                                                jackdet_bootstrap.work);
3753        wm1811_jackdet_irq(0, wm8994);
3754}
3755
3756/**
3757 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3758 *
3759 * @component:   WM8958 component
3760 * @jack:    jack to report detection events on
3761 *
3762 * Enable microphone detection functionality for the WM8958.  By
3763 * default simple detection which supports the detection of up to 6
3764 * buttons plus video and microphone functionality is supported.
3765 *
3766 * The WM8958 has an advanced jack detection facility which is able to
3767 * support complex accessory detection, especially when used in
3768 * conjunction with external circuitry.  In order to provide maximum
3769 * flexiblity a callback is provided which allows a completely custom
3770 * detection algorithm.
3771 */
3772int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3773                      wm1811_micdet_cb det_cb, void *det_cb_data,
3774                      wm1811_mic_id_cb id_cb, void *id_cb_data)
3775{
3776        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3777        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3778        struct wm8994 *control = wm8994->wm8994;
3779        u16 micd_lvl_sel;
3780
3781        switch (control->type) {
3782        case WM1811:
3783        case WM8958:
3784                break;
3785        default:
3786                return -EINVAL;
3787        }
3788
3789        if (jack) {
3790                snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
3791                snd_soc_dapm_sync(dapm);
3792
3793                wm8994->micdet[0].jack = jack;
3794
3795                if (det_cb) {
3796                        wm8994->micd_cb = det_cb;
3797                        wm8994->micd_cb_data = det_cb_data;
3798                } else {
3799                        wm8994->mic_detecting = true;
3800                        wm8994->jack_mic = false;
3801                }
3802
3803                if (id_cb) {
3804                        wm8994->mic_id_cb = id_cb;
3805                        wm8994->mic_id_cb_data = id_cb_data;
3806                } else {
3807                        wm8994->mic_id_cb = wm8958_mic_id;
3808                        wm8994->mic_id_cb_data = component;
3809                }
3810
3811                wm8958_micd_set_rate(component);
3812
3813                /* Detect microphones and short circuits by default */
3814                if (control->pdata.micd_lvl_sel)
3815                        micd_lvl_sel = control->pdata.micd_lvl_sel;
3816                else
3817                        micd_lvl_sel = 0x41;
3818
3819                wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3820                        SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3821                        SND_JACK_BTN_4 | SND_JACK_BTN_5;
3822
3823                snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
3824                                    WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3825
3826                WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
3827
3828                /*
3829                 * If we can use jack detection start off with that,
3830                 * otherwise jump straight to microphone detection.
3831                 */
3832                if (wm8994->jackdet) {
3833                        /* Disable debounce for the initial detect */
3834                        snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3835                                            WM1811_JACKDET_DB, 0);
3836
3837                        snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3838                                            WM8958_MICB2_DISCH,
3839                                            WM8958_MICB2_DISCH);
3840                        snd_soc_component_update_bits(component, WM8994_LDO_1,
3841                                            WM8994_LDO1_DISCH, 0);
3842                        wm1811_jackdet_set_mode(component,
3843                                                WM1811_JACKDET_MODE_JACK);
3844                } else {
3845                        snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3846                                            WM8958_MICD_ENA, WM8958_MICD_ENA);
3847                }
3848
3849        } else {
3850                snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3851                                    WM8958_MICD_ENA, 0);
3852                wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
3853                snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
3854                snd_soc_dapm_sync(dapm);
3855        }
3856
3857        return 0;
3858}
3859EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3860
3861static void wm8958_mic_work(struct work_struct *work)
3862{
3863        struct wm8994_priv *wm8994 = container_of(work,
3864                                                  struct wm8994_priv,
3865                                                  mic_complete_work.work);
3866        struct snd_soc_component *component = wm8994->hubs.component;
3867
3868        pm_runtime_get_sync(component->dev);
3869
3870        mutex_lock(&wm8994->accdet_lock);
3871
3872        wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3873
3874        mutex_unlock(&wm8994->accdet_lock);
3875
3876        pm_runtime_put(component->dev);
3877}
3878
3879static irqreturn_t wm8958_mic_irq(int irq, void *data)
3880{
3881        struct wm8994_priv *wm8994 = data;
3882        struct snd_soc_component *component = wm8994->hubs.component;
3883        int reg, count, ret, id_delay;
3884
3885        /*
3886         * Jack detection may have detected a removal simulataneously
3887         * with an update of the MICDET status; if so it will have
3888         * stopped detection and we can ignore this interrupt.
3889         */
3890        if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3891                return IRQ_HANDLED;
3892
3893        cancel_delayed_work_sync(&wm8994->mic_complete_work);
3894        cancel_delayed_work_sync(&wm8994->open_circuit_work);
3895
3896        pm_runtime_get_sync(component->dev);
3897
3898        /* We may occasionally read a detection without an impedence
3899         * range being provided - if that happens loop again.
3900         */
3901        count = 10;
3902        do {
3903                reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3);
3904                if (reg < 0) {
3905                        dev_err(component->dev,
3906                                "Failed to read mic detect status: %d\n",
3907                                reg);
3908                        pm_runtime_put(component->dev);
3909                        return IRQ_NONE;
3910                }
3911
3912                if (!(reg & WM8958_MICD_VALID)) {
3913                        dev_dbg(component->dev, "Mic detect data not valid\n");
3914                        goto out;
3915                }
3916
3917                if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3918                        break;
3919
3920                msleep(1);
3921        } while (count--);
3922
3923        if (count == 0)
3924                dev_warn(component->dev, "No impedance range reported for jack\n");
3925
3926#ifndef CONFIG_SND_SOC_WM8994_MODULE
3927        trace_snd_soc_jack_irq(dev_name(component->dev));
3928#endif
3929
3930        /* Avoid a transient report when the accessory is being removed */
3931        if (wm8994->jackdet) {
3932                ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3933                if (ret < 0) {
3934                        dev_err(component->dev, "Failed to read jack status: %d\n",
3935                                ret);
3936                } else if (!(ret & WM1811_JACKDET_LVL)) {
3937                        dev_dbg(component->dev, "Ignoring removed jack\n");
3938                        goto out;
3939                }
3940        } else if (!(reg & WM8958_MICD_STS)) {
3941                snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3942                                    SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3943                                    wm8994->btn_mask);
3944                wm8994->mic_detecting = true;
3945                goto out;
3946        }
3947
3948        wm8994->mic_status = reg;
3949        id_delay = wm8994->wm8994->pdata.mic_id_delay;
3950
3951        if (wm8994->mic_detecting)
3952                queue_delayed_work(system_power_efficient_wq,
3953                                   &wm8994->mic_complete_work,
3954                                   msecs_to_jiffies(id_delay));
3955        else
3956                wm8958_button_det(component, reg);
3957
3958out:
3959        pm_runtime_put(component->dev);
3960        return IRQ_HANDLED;
3961}
3962
3963static irqreturn_t wm8994_fifo_error(int irq, void *data)
3964{
3965        struct snd_soc_component *component = data;
3966
3967        dev_err(component->dev, "FIFO error\n");
3968
3969        return IRQ_HANDLED;
3970}
3971
3972static irqreturn_t wm8994_temp_warn(int irq, void *data)
3973{
3974        struct snd_soc_component *component = data;
3975
3976        dev_err(component->dev, "Thermal warning\n");
3977
3978        return IRQ_HANDLED;
3979}
3980
3981static irqreturn_t wm8994_temp_shut(int irq, void *data)
3982{
3983        struct snd_soc_component *component = data;
3984
3985        dev_crit(component->dev, "Thermal shutdown\n");
3986
3987        return IRQ_HANDLED;
3988}
3989
3990static int wm8994_component_probe(struct snd_soc_component *component)
3991{
3992        struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3993        struct wm8994 *control = dev_get_drvdata(component->dev->parent);
3994        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3995        unsigned int reg;
3996        int ret, i;
3997
3998        snd_soc_component_init_regmap(component, control->regmap);
3999
4000        wm8994->hubs.component = component;
4001
4002        mutex_init(&wm8994->accdet_lock);
4003        INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4004                          wm1811_jackdet_bootstrap);
4005        INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4006                          wm8958_open_circuit_work);
4007
4008        switch (control->type) {
4009        case WM8994:
4010                INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4011                break;
4012        case WM1811:
4013                INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4014                break;
4015        default:
4016                break;
4017        }
4018
4019        INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4020
4021        for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4022                init_completion(&wm8994->fll_locked[i]);
4023
4024        wm8994->micdet_irq = control->pdata.micdet_irq;
4025
4026        /* By default use idle_bias_off, will override for WM8994 */
4027        dapm->idle_bias_off = 1;
4028
4029        /* Set revision-specific configuration */
4030        switch (control->type) {
4031        case WM8994:
4032                /* Single ended line outputs should have VMID on. */
4033                if (!control->pdata.lineout1_diff ||
4034                    !control->pdata.lineout2_diff)
4035                        dapm->idle_bias_off = 0;
4036
4037                switch (control->revision) {
4038                case 2:
4039                case 3:
4040                        wm8994->hubs.dcs_codes_l = -5;
4041                        wm8994->hubs.dcs_codes_r = -5;
4042                        wm8994->hubs.hp_startup_mode = 1;
4043                        wm8994->hubs.dcs_readback_mode = 1;
4044                        wm8994->hubs.series_startup = 1;
4045                        break;
4046                default:
4047                        wm8994->hubs.dcs_readback_mode = 2;
4048                        break;
4049                }
4050                break;
4051
4052        case WM8958:
4053                wm8994->hubs.dcs_readback_mode = 1;
4054                wm8994->hubs.hp_startup_mode = 1;
4055
4056                switch (control->revision) {
4057                case 0:
4058                        break;
4059                default:
4060                        wm8994->fll_byp = true;
4061                        break;
4062                }
4063                break;
4064
4065        case WM1811:
4066                wm8994->hubs.dcs_readback_mode = 2;
4067                wm8994->hubs.no_series_update = 1;
4068                wm8994->hubs.hp_startup_mode = 1;
4069                wm8994->hubs.no_cache_dac_hp_direct = true;
4070                wm8994->fll_byp = true;
4071
4072                wm8994->hubs.dcs_codes_l = -9;
4073                wm8994->hubs.dcs_codes_r = -7;
4074
4075                snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
4076                                    WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4077                break;
4078
4079        default:
4080                break;
4081        }
4082
4083        wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4084                           wm8994_fifo_error, "FIFO error", component);
4085        wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4086                           wm8994_temp_warn, "Thermal warning", component);
4087        wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4088                           wm8994_temp_shut, "Thermal shutdown", component);
4089
4090        switch (control->type) {
4091        case WM8994:
4092                if (wm8994->micdet_irq)
4093                        ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4094                                                   wm8994_mic_irq,
4095                                                   IRQF_TRIGGER_RISING |
4096                                                   IRQF_ONESHOT,
4097                                                   "Mic1 detect",
4098                                                   wm8994);
4099                 else
4100                        ret = wm8994_request_irq(wm8994->wm8994,
4101                                        WM8994_IRQ_MIC1_DET,
4102                                        wm8994_mic_irq, "Mic 1 detect",
4103                                        wm8994);
4104
4105                if (ret != 0)
4106                        dev_warn(component->dev,
4107                                 "Failed to request Mic1 detect IRQ: %d\n",
4108                                 ret);
4109
4110
4111                ret = wm8994_request_irq(wm8994->wm8994,
4112                                         WM8994_IRQ_MIC1_SHRT,
4113                                         wm8994_mic_irq, "Mic 1 short",
4114                                         wm8994);
4115                if (ret != 0)
4116                        dev_warn(component->dev,
4117                                 "Failed to request Mic1 short IRQ: %d\n",
4118                                 ret);
4119
4120                ret = wm8994_request_irq(wm8994->wm8994,
4121                                         WM8994_IRQ_MIC2_DET,
4122                                         wm8994_mic_irq, "Mic 2 detect",
4123                                         wm8994);
4124                if (ret != 0)
4125                        dev_warn(component->dev,
4126                                 "Failed to request Mic2 detect IRQ: %d\n",
4127                                 ret);
4128
4129                ret = wm8994_request_irq(wm8994->wm8994,
4130                                         WM8994_IRQ_MIC2_SHRT,
4131                                         wm8994_mic_irq, "Mic 2 short",
4132                                         wm8994);
4133                if (ret != 0)
4134                        dev_warn(component->dev,
4135                                 "Failed to request Mic2 short IRQ: %d\n",
4136                                 ret);
4137                break;
4138
4139        case WM8958:
4140        case WM1811:
4141                if (wm8994->micdet_irq) {
4142                        ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4143                                                   wm8958_mic_irq,
4144                                                   IRQF_TRIGGER_RISING |
4145                                                   IRQF_ONESHOT,
4146                                                   "Mic detect",
4147                                                   wm8994);
4148                        if (ret != 0)
4149                                dev_warn(component->dev,
4150                                         "Failed to request Mic detect IRQ: %d\n",
4151                                         ret);
4152                } else {
4153                        wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4154                                           wm8958_mic_irq, "Mic detect",
4155                                           wm8994);
4156                }
4157        }
4158
4159        switch (control->type) {
4160        case WM1811:
4161                if (control->cust_id > 1 || control->revision > 1) {
4162                        ret = wm8994_request_irq(wm8994->wm8994,
4163                                                 WM8994_IRQ_GPIO(6),
4164                                                 wm1811_jackdet_irq, "JACKDET",
4165                                                 wm8994);
4166                        if (ret == 0)
4167                                wm8994->jackdet = true;
4168                }
4169                break;
4170        default:
4171                break;
4172        }
4173
4174        wm8994->fll_locked_irq = true;
4175        for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4176                ret = wm8994_request_irq(wm8994->wm8994,
4177                                         WM8994_IRQ_FLL1_LOCK + i,
4178                                         wm8994_fll_locked_irq, "FLL lock",
4179                                         &wm8994->fll_locked[i]);
4180                if (ret != 0)
4181                        wm8994->fll_locked_irq = false;
4182        }
4183
4184        /* Make sure we can read from the GPIOs if they're inputs */
4185        pm_runtime_get_sync(component->dev);
4186
4187        /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
4188         * configured on init - if a system wants to do this dynamically
4189         * at runtime we can deal with that then.
4190         */
4191        ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4192        if (ret < 0) {
4193                dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
4194                goto err_irq;
4195        }
4196        if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4197                wm8994->lrclk_shared[0] = 1;
4198                wm8994_dai[0].symmetric_rates = 1;
4199        } else {
4200                wm8994->lrclk_shared[0] = 0;
4201        }
4202
4203        ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4204        if (ret < 0) {
4205                dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
4206                goto err_irq;
4207        }
4208        if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4209                wm8994->lrclk_shared[1] = 1;
4210                wm8994_dai[1].symmetric_rates = 1;
4211        } else {
4212                wm8994->lrclk_shared[1] = 0;
4213        }
4214
4215        pm_runtime_put(component->dev);
4216
4217        /* Latch volume update bits */
4218        for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4219                snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
4220                                    wm8994_vu_bits[i].mask,
4221                                    wm8994_vu_bits[i].mask);
4222
4223        /* Set the low bit of the 3D stereo depth so TLV matches */
4224        snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
4225                            1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4226                            1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4227        snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
4228                            1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4229                            1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4230        snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
4231                            1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4232                            1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4233
4234        /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4235         * use this; it only affects behaviour on idle TDM clock
4236         * cycles. */
4237        switch (control->type) {
4238        case WM8994:
4239        case WM8958:
4240                snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
4241                                    WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4242                break;
4243        default:
4244                break;
4245        }
4246
4247        /* Put MICBIAS into bypass mode by default on newer devices */
4248        switch (control->type) {
4249        case WM8958:
4250        case WM1811:
4251                snd_soc_component_update_bits(component, WM8958_MICBIAS1,
4252                                    WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4253                snd_soc_component_update_bits(component, WM8958_MICBIAS2,
4254                                    WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4255                break;
4256        default:
4257                break;
4258        }
4259
4260        wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4261        wm_hubs_update_class_w(component);
4262
4263        wm8994_handle_pdata(wm8994);
4264
4265        wm_hubs_add_analogue_controls(component);
4266        snd_soc_add_component_controls(component, wm8994_common_snd_controls,
4267                                       ARRAY_SIZE(wm8994_common_snd_controls));
4268        snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4269                                  ARRAY_SIZE(wm8994_dapm_widgets));
4270
4271        switch (control->type) {
4272        case WM8994:
4273                snd_soc_add_component_controls(component, wm8994_snd_controls,
4274                                               ARRAY_SIZE(wm8994_snd_controls));
4275                snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4276                                          ARRAY_SIZE(wm8994_specific_dapm_widgets));
4277                if (control->revision < 4) {
4278                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4279                                                  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4280                        snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4281                                                  ARRAY_SIZE(wm8994_adc_revd_widgets));
4282                        snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4283                                                  ARRAY_SIZE(wm8994_dac_revd_widgets));
4284                } else {
4285                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4286                                                  ARRAY_SIZE(wm8994_lateclk_widgets));
4287                        snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4288                                                  ARRAY_SIZE(wm8994_adc_widgets));
4289                        snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4290                                                  ARRAY_SIZE(wm8994_dac_widgets));
4291                }
4292                break;
4293        case WM8958:
4294                snd_soc_add_component_controls(component, wm8994_snd_controls,
4295                                               ARRAY_SIZE(wm8994_snd_controls));
4296                snd_soc_add_component_controls(component, wm8958_snd_controls,
4297                                               ARRAY_SIZE(wm8958_snd_controls));
4298                snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4299                                          ARRAY_SIZE(wm8958_dapm_widgets));
4300                if (control->revision < 1) {
4301                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4302                                                  ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4303                        snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4304                                                  ARRAY_SIZE(wm8994_adc_revd_widgets));
4305                        snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4306                                                  ARRAY_SIZE(wm8994_dac_revd_widgets));
4307                } else {
4308                        snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4309                                                  ARRAY_SIZE(wm8994_lateclk_widgets));
4310                        snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4311                                                  ARRAY_SIZE(wm8994_adc_widgets));
4312                        snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4313                                                  ARRAY_SIZE(wm8994_dac_widgets));
4314                }
4315                break;
4316
4317        case WM1811:
4318                snd_soc_add_component_controls(component, wm8958_snd_controls,
4319                                     ARRAY_SIZE(wm8958_snd_controls));
4320                snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4321                                          ARRAY_SIZE(wm8958_dapm_widgets));
4322                snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4323                                          ARRAY_SIZE(wm8994_lateclk_widgets));
4324                snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4325                                          ARRAY_SIZE(wm8994_adc_widgets));
4326                snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4327                                          ARRAY_SIZE(wm8994_dac_widgets));
4328                break;
4329        }
4330
4331        wm_hubs_add_analogue_routes(component, 0, 0);
4332        ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4333                                 wm_hubs_dcs_done, "DC servo done",
4334                                 &wm8994->hubs);
4335        if (ret == 0)
4336                wm8994->hubs.dcs_done_irq = true;
4337        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4338
4339        switch (control->type) {
4340        case WM8994:
4341                snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4342                                        ARRAY_SIZE(wm8994_intercon));
4343
4344                if (control->revision < 4) {
4345                        snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4346                                                ARRAY_SIZE(wm8994_revd_intercon));
4347                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4348                                                ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4349                } else {
4350                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4351                                                ARRAY_SIZE(wm8994_lateclk_intercon));
4352                }
4353                break;
4354        case WM8958:
4355                if (control->revision < 1) {
4356                        snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4357                                                ARRAY_SIZE(wm8994_intercon));
4358                        snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4359                                                ARRAY_SIZE(wm8994_revd_intercon));
4360                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4361                                                ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4362                } else {
4363                        snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4364                                                ARRAY_SIZE(wm8994_lateclk_intercon));
4365                        snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4366                                                ARRAY_SIZE(wm8958_intercon));
4367                }
4368
4369                wm8958_dsp2_init(component);
4370                break;
4371        case WM1811:
4372                snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4373                                        ARRAY_SIZE(wm8994_lateclk_intercon));
4374                snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4375                                        ARRAY_SIZE(wm8958_intercon));
4376                break;
4377        }
4378
4379        return 0;
4380
4381err_irq:
4382        if (wm8994->jackdet)
4383                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4384        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4385        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4386        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4387        if (wm8994->micdet_irq)
4388                free_irq(wm8994->micdet_irq, wm8994);
4389        for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4390                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4391                                &wm8994->fll_locked[i]);
4392        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4393                        &wm8994->hubs);
4394        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4395        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4396        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4397
4398        return ret;
4399}
4400
4401static void wm8994_component_remove(struct snd_soc_component *component)
4402{
4403        struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4404        struct wm8994 *control = wm8994->wm8994;
4405        int i;
4406
4407        for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4408                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4409                                &wm8994->fll_locked[i]);
4410
4411        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4412                        &wm8994->hubs);
4413        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4414        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4415        wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4416
4417        if (wm8994->jackdet)
4418                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4419
4420        switch (control->type) {
4421        case WM8994:
4422                if (wm8994->micdet_irq)
4423                        free_irq(wm8994->micdet_irq, wm8994);
4424                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4425                                wm8994);
4426                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4427                                wm8994);
4428                wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4429                                wm8994);
4430                break;
4431
4432        case WM1811:
4433        case WM8958:
4434                if (wm8994->micdet_irq)
4435                        free_irq(wm8994->micdet_irq, wm8994);
4436                break;
4437        }
4438        release_firmware(wm8994->mbc);
4439        release_firmware(wm8994->mbc_vss);
4440        release_firmware(wm8994->enh_eq);
4441        kfree(wm8994->retune_mobile_texts);
4442}
4443
4444static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
4445        .probe                  = wm8994_component_probe,
4446        .remove                 = wm8994_component_remove,
4447        .suspend                = wm8994_component_suspend,
4448        .resume                 = wm8994_component_resume,
4449        .set_bias_level         = wm8994_set_bias_level,
4450        .idle_bias_on           = 1,
4451        .use_pmdown_time        = 1,
4452        .endianness             = 1,
4453        .non_legacy_dai_naming  = 1,
4454};
4455
4456static int wm8994_probe(struct platform_device *pdev)
4457{
4458        struct wm8994_priv *wm8994;
4459
4460        wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4461                              GFP_KERNEL);
4462        if (wm8994 == NULL)
4463                return -ENOMEM;
4464        platform_set_drvdata(pdev, wm8994);
4465
4466        mutex_init(&wm8994->fw_lock);
4467
4468        wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4469
4470        pm_runtime_enable(&pdev->dev);
4471        pm_runtime_idle(&pdev->dev);
4472
4473        return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
4474                        wm8994_dai, ARRAY_SIZE(wm8994_dai));
4475}
4476
4477static int wm8994_remove(struct platform_device *pdev)
4478{
4479        pm_runtime_disable(&pdev->dev);
4480
4481        return 0;
4482}
4483
4484#ifdef CONFIG_PM_SLEEP
4485static int wm8994_suspend(struct device *dev)
4486{
4487        struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4488
4489        /* Drop down to power saving mode when system is suspended */
4490        if (wm8994->jackdet && !wm8994->active_refcount)
4491                regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4492                                   WM1811_JACKDET_MODE_MASK,
4493                                   wm8994->jackdet_mode);
4494
4495        return 0;
4496}
4497
4498static int wm8994_resume(struct device *dev)
4499{
4500        struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4501
4502        if (wm8994->jackdet && wm8994->jackdet_mode)
4503                regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4504                                   WM1811_JACKDET_MODE_MASK,
4505                                   WM1811_JACKDET_MODE_AUDIO);
4506
4507        return 0;
4508}
4509#endif
4510
4511static const struct dev_pm_ops wm8994_pm_ops = {
4512        SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4513};
4514
4515static struct platform_driver wm8994_codec_driver = {
4516        .driver = {
4517                .name = "wm8994-codec",
4518                .pm = &wm8994_pm_ops,
4519        },
4520        .probe = wm8994_probe,
4521        .remove = wm8994_remove,
4522};
4523
4524module_platform_driver(wm8994_codec_driver);
4525
4526MODULE_DESCRIPTION("ASoC WM8994 driver");
4527MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4528MODULE_LICENSE("GPL");
4529MODULE_ALIAS("platform:wm8994-codec");
4530