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8#include <linux/clk.h>
9#include <linux/module.h>
10#include <linux/of_platform.h>
11#include <linux/pm_runtime.h>
12#include <sound/soc.h>
13#include <sound/pcm_params.h>
14
15#include "fsl_audmix.h"
16
17#define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \
18 SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts)
19
20static const char
21 *tdm_sel[] = { "TDM1", "TDM2", },
22 *mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", },
23 *width_sel[] = { "16b", "18b", "20b", "24b", "32b", },
24 *endis_sel[] = { "Disabled", "Enabled", },
25 *updn_sel[] = { "Downward", "Upward", },
26 *mask_sel[] = { "Unmask", "Mask", };
27
28static const struct soc_enum fsl_audmix_enum[] = {
29
30SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel),
31SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel),
32SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel),
33SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel),
34SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel),
35SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel),
36SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel),
37
38SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
39SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel),
40
41SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
42SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel),
43};
44
45struct fsl_audmix_state {
46 u8 tdms;
47 u8 clk;
48 char msg[64];
49};
50
51static const struct fsl_audmix_state prms[4][4] = {{
52
53 { .tdms = 0, .clk = 0, .msg = "" },
54
55 { .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
56
57 { .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
58
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
60}, {
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
62
63 { .tdms = 0, .clk = 0, .msg = "" },
64
65 { .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
66
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
68}, {
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
70
71 { .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" },
72
73 { .tdms = 0, .clk = 0, .msg = "" },
74
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
76}, {
77 { .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" },
78
79 { .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" },
80
81 { .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" },
82
83 { .tdms = 0, .clk = 0, .msg = "" }
84}, };
85
86static int fsl_audmix_state_trans(struct snd_soc_component *comp,
87 unsigned int *mask, unsigned int *ctr,
88 const struct fsl_audmix_state prm)
89{
90 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
91
92 if ((priv->tdms & prm.tdms) != prm.tdms) {
93 dev_dbg(comp->dev, "%s", prm.msg);
94 return -EINVAL;
95 }
96
97 switch (prm.clk) {
98 case 1:
99 case 2:
100
101 (*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK;
102 (*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1);
103 break;
104 default:
105 break;
106 }
107
108 return 0;
109}
110
111static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol,
112 struct snd_ctl_elem_value *ucontrol)
113{
114 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
115 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
117 unsigned int *item = ucontrol->value.enumerated.item;
118 unsigned int reg_val, val, mix_clk;
119
120
121 reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
122 mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
123 >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
124 val = snd_soc_enum_item_to_val(e, item[0]);
125
126 dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
127
128
129
130
131
132 if (!(priv->tdms & BIT(mix_clk))) {
133 dev_err(comp->dev,
134 "Started TDM%d needed for config propagation!\n",
135 mix_clk + 1);
136 return -EINVAL;
137 }
138
139 if (!(priv->tdms & BIT(val))) {
140 dev_err(comp->dev,
141 "The selected clock source has no TDM%d enabled!\n",
142 val + 1);
143 return -EINVAL;
144 }
145
146 return snd_soc_put_enum_double(kcontrol, ucontrol);
147}
148
149static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol,
150 struct snd_ctl_elem_value *ucontrol)
151{
152 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
153 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
154 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
155 unsigned int *item = ucontrol->value.enumerated.item;
156 u32 out_src, mix_clk;
157 unsigned int reg_val, val, mask = 0, ctr = 0;
158 int ret;
159
160
161 reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
162
163
164 out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)
165 >> FSL_AUDMIX_CTR_OUTSRC_SHIFT);
166 mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
167 >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
168
169
170 val = snd_soc_enum_item_to_val(e, item[0]);
171
172 dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
173
174
175 if (out_src == val)
176 return 0;
177
178
179
180
181 if (!(priv->tdms & BIT(mix_clk))) {
182 dev_err(comp->dev,
183 "Started TDM%d needed for config propagation!\n",
184 mix_clk + 1);
185 return -EINVAL;
186 }
187
188
189 ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]);
190 if (ret)
191 return ret;
192
193
194 mask |= FSL_AUDMIX_CTR_OUTSRC_MASK;
195 ctr |= FSL_AUDMIX_CTR_OUTSRC(val);
196
197 return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
198}
199
200static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
201
202 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
203 .name = "Mixing Clock Source",
204 .info = snd_soc_info_enum_double,
205 .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
206 .put = fsl_audmix_put_mix_clk_src,
207 .private_value = (unsigned long)&fsl_audmix_enum[0] },
208 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
209 .name = "Output Source",
210 .info = snd_soc_info_enum_double,
211 .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
212 .put = fsl_audmix_put_out_src,
213 .private_value = (unsigned long)&fsl_audmix_enum[1] },
214 SOC_ENUM("Output Width", fsl_audmix_enum[2]),
215 SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
216 SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
217 SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]),
218 SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]),
219
220 SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]),
221 SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]),
222 SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0,
223 2, 0x00fff, 0),
224 SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0,
225 0, 0x3ffff, 0),
226 SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0,
227 0, 0x3ffff, 0),
228 SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0,
229 0, 0x3ffff, 0),
230 SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0,
231 0, 0x3ffff, 0),
232
233 SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]),
234 SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]),
235 SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1,
236 2, 0x00fff, 0),
237 SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1,
238 0, 0x3ffff, 0),
239 SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1,
240 0, 0x3ffff, 0),
241 SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1,
242 0, 0x3ffff, 0),
243 SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1,
244 0, 0x3ffff, 0),
245};
246
247static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
248{
249 struct snd_soc_component *comp = dai->component;
250 u32 mask = 0, ctr = 0;
251
252
253 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
254 case SND_SOC_DAIFMT_DSP_A:
255 break;
256 default:
257 return -EINVAL;
258 }
259
260
261 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
262 case SND_SOC_DAIFMT_CBM_CFM:
263 case SND_SOC_DAIFMT_CBS_CFS:
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
270 case SND_SOC_DAIFMT_IB_NF:
271
272 ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0);
273 break;
274 case SND_SOC_DAIFMT_NB_NF:
275
276 ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1);
277 break;
278 default:
279 return -EINVAL;
280 }
281
282 mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK;
283
284 return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
285}
286
287static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd,
288 struct snd_soc_dai *dai)
289{
290 struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai);
291 unsigned long lock_flags;
292
293
294 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
295 return 0;
296
297 switch (cmd) {
298 case SNDRV_PCM_TRIGGER_START:
299 case SNDRV_PCM_TRIGGER_RESUME:
300 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
301 spin_lock_irqsave(&priv->lock, lock_flags);
302 priv->tdms |= BIT(dai->driver->id);
303 spin_unlock_irqrestore(&priv->lock, lock_flags);
304 break;
305 case SNDRV_PCM_TRIGGER_STOP:
306 case SNDRV_PCM_TRIGGER_SUSPEND:
307 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
308 spin_lock_irqsave(&priv->lock, lock_flags);
309 priv->tdms &= ~BIT(dai->driver->id);
310 spin_unlock_irqrestore(&priv->lock, lock_flags);
311 break;
312 default:
313 return -EINVAL;
314 }
315
316 return 0;
317}
318
319static const struct snd_soc_dai_ops fsl_audmix_dai_ops = {
320 .set_fmt = fsl_audmix_dai_set_fmt,
321 .trigger = fsl_audmix_dai_trigger,
322};
323
324static struct snd_soc_dai_driver fsl_audmix_dai[] = {
325 {
326 .id = 0,
327 .name = "audmix-0",
328 .playback = {
329 .stream_name = "AUDMIX-Playback-0",
330 .channels_min = 8,
331 .channels_max = 8,
332 .rate_min = 8000,
333 .rate_max = 96000,
334 .rates = SNDRV_PCM_RATE_8000_96000,
335 .formats = FSL_AUDMIX_FORMATS,
336 },
337 .capture = {
338 .stream_name = "AUDMIX-Capture-0",
339 .channels_min = 8,
340 .channels_max = 8,
341 .rate_min = 8000,
342 .rate_max = 96000,
343 .rates = SNDRV_PCM_RATE_8000_96000,
344 .formats = FSL_AUDMIX_FORMATS,
345 },
346 .ops = &fsl_audmix_dai_ops,
347 },
348 {
349 .id = 1,
350 .name = "audmix-1",
351 .playback = {
352 .stream_name = "AUDMIX-Playback-1",
353 .channels_min = 8,
354 .channels_max = 8,
355 .rate_min = 8000,
356 .rate_max = 96000,
357 .rates = SNDRV_PCM_RATE_8000_96000,
358 .formats = FSL_AUDMIX_FORMATS,
359 },
360 .capture = {
361 .stream_name = "AUDMIX-Capture-1",
362 .channels_min = 8,
363 .channels_max = 8,
364 .rate_min = 8000,
365 .rate_max = 96000,
366 .rates = SNDRV_PCM_RATE_8000_96000,
367 .formats = FSL_AUDMIX_FORMATS,
368 },
369 .ops = &fsl_audmix_dai_ops,
370 },
371};
372
373static const struct snd_soc_component_driver fsl_audmix_component = {
374 .name = "fsl-audmix-dai",
375 .controls = fsl_audmix_snd_controls,
376 .num_controls = ARRAY_SIZE(fsl_audmix_snd_controls),
377};
378
379static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg)
380{
381 switch (reg) {
382 case FSL_AUDMIX_CTR:
383 case FSL_AUDMIX_STR:
384 case FSL_AUDMIX_ATCR0:
385 case FSL_AUDMIX_ATIVAL0:
386 case FSL_AUDMIX_ATSTPUP0:
387 case FSL_AUDMIX_ATSTPDN0:
388 case FSL_AUDMIX_ATSTPTGT0:
389 case FSL_AUDMIX_ATTNVAL0:
390 case FSL_AUDMIX_ATSTP0:
391 case FSL_AUDMIX_ATCR1:
392 case FSL_AUDMIX_ATIVAL1:
393 case FSL_AUDMIX_ATSTPUP1:
394 case FSL_AUDMIX_ATSTPDN1:
395 case FSL_AUDMIX_ATSTPTGT1:
396 case FSL_AUDMIX_ATTNVAL1:
397 case FSL_AUDMIX_ATSTP1:
398 return true;
399 default:
400 return false;
401 }
402}
403
404static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg)
405{
406 switch (reg) {
407 case FSL_AUDMIX_CTR:
408 case FSL_AUDMIX_ATCR0:
409 case FSL_AUDMIX_ATIVAL0:
410 case FSL_AUDMIX_ATSTPUP0:
411 case FSL_AUDMIX_ATSTPDN0:
412 case FSL_AUDMIX_ATSTPTGT0:
413 case FSL_AUDMIX_ATCR1:
414 case FSL_AUDMIX_ATIVAL1:
415 case FSL_AUDMIX_ATSTPUP1:
416 case FSL_AUDMIX_ATSTPDN1:
417 case FSL_AUDMIX_ATSTPTGT1:
418 return true;
419 default:
420 return false;
421 }
422}
423
424static const struct reg_default fsl_audmix_reg[] = {
425 { FSL_AUDMIX_CTR, 0x00060 },
426 { FSL_AUDMIX_STR, 0x00003 },
427 { FSL_AUDMIX_ATCR0, 0x00000 },
428 { FSL_AUDMIX_ATIVAL0, 0x3FFFF },
429 { FSL_AUDMIX_ATSTPUP0, 0x2AAAA },
430 { FSL_AUDMIX_ATSTPDN0, 0x30000 },
431 { FSL_AUDMIX_ATSTPTGT0, 0x00010 },
432 { FSL_AUDMIX_ATTNVAL0, 0x00000 },
433 { FSL_AUDMIX_ATSTP0, 0x00000 },
434 { FSL_AUDMIX_ATCR1, 0x00000 },
435 { FSL_AUDMIX_ATIVAL1, 0x3FFFF },
436 { FSL_AUDMIX_ATSTPUP1, 0x2AAAA },
437 { FSL_AUDMIX_ATSTPDN1, 0x30000 },
438 { FSL_AUDMIX_ATSTPTGT1, 0x00010 },
439 { FSL_AUDMIX_ATTNVAL1, 0x00000 },
440 { FSL_AUDMIX_ATSTP1, 0x00000 },
441};
442
443static const struct regmap_config fsl_audmix_regmap_config = {
444 .reg_bits = 32,
445 .reg_stride = 4,
446 .val_bits = 32,
447 .max_register = FSL_AUDMIX_ATSTP1,
448 .reg_defaults = fsl_audmix_reg,
449 .num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg),
450 .readable_reg = fsl_audmix_readable_reg,
451 .writeable_reg = fsl_audmix_writeable_reg,
452 .cache_type = REGCACHE_FLAT,
453};
454
455static const struct of_device_id fsl_audmix_ids[] = {
456 {
457 .compatible = "fsl,imx8qm-audmix",
458 },
459 { }
460};
461MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
462
463static int fsl_audmix_probe(struct platform_device *pdev)
464{
465 struct device *dev = &pdev->dev;
466 struct fsl_audmix *priv;
467 void __iomem *regs;
468 int ret;
469
470 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
471 if (!priv)
472 return -ENOMEM;
473
474
475 regs = devm_platform_ioremap_resource(pdev, 0);
476 if (IS_ERR(regs))
477 return PTR_ERR(regs);
478
479 priv->regmap = devm_regmap_init_mmio(dev, regs, &fsl_audmix_regmap_config);
480 if (IS_ERR(priv->regmap)) {
481 dev_err(dev, "failed to init regmap\n");
482 return PTR_ERR(priv->regmap);
483 }
484
485 priv->ipg_clk = devm_clk_get(dev, "ipg");
486 if (IS_ERR(priv->ipg_clk)) {
487 dev_err(dev, "failed to get ipg clock\n");
488 return PTR_ERR(priv->ipg_clk);
489 }
490
491 spin_lock_init(&priv->lock);
492 platform_set_drvdata(pdev, priv);
493 pm_runtime_enable(dev);
494
495 ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
496 fsl_audmix_dai,
497 ARRAY_SIZE(fsl_audmix_dai));
498 if (ret) {
499 dev_err(dev, "failed to register ASoC DAI\n");
500 goto err_disable_pm;
501 }
502
503 priv->pdev = platform_device_register_data(dev, "imx-audmix", 0, NULL, 0);
504 if (IS_ERR(priv->pdev)) {
505 ret = PTR_ERR(priv->pdev);
506 dev_err(dev, "failed to register platform: %d\n", ret);
507 goto err_disable_pm;
508 }
509
510 return 0;
511
512err_disable_pm:
513 pm_runtime_disable(dev);
514 return ret;
515}
516
517static int fsl_audmix_remove(struct platform_device *pdev)
518{
519 struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev);
520
521 pm_runtime_disable(&pdev->dev);
522
523 if (priv->pdev)
524 platform_device_unregister(priv->pdev);
525
526 return 0;
527}
528
529#ifdef CONFIG_PM
530static int fsl_audmix_runtime_resume(struct device *dev)
531{
532 struct fsl_audmix *priv = dev_get_drvdata(dev);
533 int ret;
534
535 ret = clk_prepare_enable(priv->ipg_clk);
536 if (ret) {
537 dev_err(dev, "Failed to enable IPG clock: %d\n", ret);
538 return ret;
539 }
540
541 regcache_cache_only(priv->regmap, false);
542 regcache_mark_dirty(priv->regmap);
543
544 return regcache_sync(priv->regmap);
545}
546
547static int fsl_audmix_runtime_suspend(struct device *dev)
548{
549 struct fsl_audmix *priv = dev_get_drvdata(dev);
550
551 regcache_cache_only(priv->regmap, true);
552
553 clk_disable_unprepare(priv->ipg_clk);
554
555 return 0;
556}
557#endif
558
559static const struct dev_pm_ops fsl_audmix_pm = {
560 SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend,
561 fsl_audmix_runtime_resume,
562 NULL)
563 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
564 pm_runtime_force_resume)
565};
566
567static struct platform_driver fsl_audmix_driver = {
568 .probe = fsl_audmix_probe,
569 .remove = fsl_audmix_remove,
570 .driver = {
571 .name = "fsl-audmix",
572 .of_match_table = fsl_audmix_ids,
573 .pm = &fsl_audmix_pm,
574 },
575};
576module_platform_driver(fsl_audmix_driver);
577
578MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver");
579MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
580MODULE_ALIAS("platform:fsl-audmix");
581MODULE_LICENSE("GPL v2");
582
