1
2
3
4#include <linux/atomic.h>
5#include <linux/clk.h>
6#include <linux/device.h>
7#include <linux/dma-mapping.h>
8#include <linux/firmware.h>
9#include <linux/interrupt.h>
10#include <linux/kobject.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/miscdevice.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/sched/signal.h>
21#include <linux/sysfs.h>
22#include <linux/types.h>
23#include <linux/gcd.h>
24#include <sound/dmaengine_pcm.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/tlv.h>
29#include <sound/core.h>
30
31#include "fsl_easrc.h"
32#include "imx-pcm.h"
33
34#define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
35 SNDRV_PCM_FMTBIT_U16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE | \
37 SNDRV_PCM_FMTBIT_S24_3LE | \
38 SNDRV_PCM_FMTBIT_U24_LE | \
39 SNDRV_PCM_FMTBIT_U24_3LE | \
40 SNDRV_PCM_FMTBIT_S32_LE | \
41 SNDRV_PCM_FMTBIT_U32_LE | \
42 SNDRV_PCM_FMTBIT_S20_3LE | \
43 SNDRV_PCM_FMTBIT_U20_3LE | \
44 SNDRV_PCM_FMTBIT_FLOAT_LE)
45
46static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
47 struct snd_ctl_elem_value *ucontrol)
48{
49 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
51 struct fsl_easrc_priv *easrc_priv = easrc->private;
52 struct soc_mreg_control *mc =
53 (struct soc_mreg_control *)kcontrol->private_value;
54 unsigned int regval = ucontrol->value.integer.value[0];
55
56 easrc_priv->bps_iec958[mc->regbase] = regval;
57
58 return 0;
59}
60
61static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
62 struct snd_ctl_elem_value *ucontrol)
63{
64 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
65 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
66 struct fsl_easrc_priv *easrc_priv = easrc->private;
67 struct soc_mreg_control *mc =
68 (struct soc_mreg_control *)kcontrol->private_value;
69
70 ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase];
71
72 return 0;
73}
74
75static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
76 struct snd_ctl_elem_value *ucontrol)
77{
78 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
79 struct soc_mreg_control *mc =
80 (struct soc_mreg_control *)kcontrol->private_value;
81 unsigned int regval;
82
83 regval = snd_soc_component_read(component, mc->regbase);
84
85 ucontrol->value.integer.value[0] = regval;
86
87 return 0;
88}
89
90static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
91 struct snd_ctl_elem_value *ucontrol)
92{
93 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
94 struct soc_mreg_control *mc =
95 (struct soc_mreg_control *)kcontrol->private_value;
96 unsigned int regval = ucontrol->value.integer.value[0];
97 int ret;
98
99 ret = snd_soc_component_write(component, mc->regbase, regval);
100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
106#define SOC_SINGLE_REG_RW(xname, xreg) \
107{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
108 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
109 .info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
110 .put = fsl_easrc_set_reg, \
111 .private_value = (unsigned long)&(struct soc_mreg_control) \
112 { .regbase = xreg, .regcount = 1, .nbits = 32, \
113 .invert = 0, .min = 0, .max = 0xffffffff, } }
114
115#define SOC_SINGLE_VAL_RW(xname, xreg) \
116{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
117 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
118 .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \
119 .put = fsl_easrc_iec958_put_bits, \
120 .private_value = (unsigned long)&(struct soc_mreg_control) \
121 { .regbase = xreg, .regcount = 1, .nbits = 32, \
122 .invert = 0, .min = 0, .max = 2, } }
123
124static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
125 SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0),
126 SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0),
127 SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0),
128 SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0),
129
130 SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0),
131 SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0),
132 SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0),
133 SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0),
134
135 SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0),
136 SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1),
137 SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
138 SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
139
140 SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
141 SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
142 SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
143 SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
144 SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
145 SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
146 SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
147 SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
148 SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
149 SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
150 SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
151 SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
152 SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
153 SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
154 SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
155 SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
156 SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
157 SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
158 SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
159 SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
160 SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
161 SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
162 SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
163 SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
164};
165
166
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169
170
171
172static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx)
173{
174 struct fsl_asrc *easrc = ctx->asrc;
175 struct fsl_easrc_priv *easrc_priv = easrc->private;
176 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
177 unsigned int in_rate = ctx_priv->in_params.norm_rate;
178 unsigned int out_rate = ctx_priv->out_params.norm_rate;
179 unsigned int frac_bits;
180 u64 val;
181 u32 *r;
182
183 switch (easrc_priv->rs_num_taps) {
184 case EASRC_RS_32_TAPS:
185
186 frac_bits = 39;
187 break;
188 case EASRC_RS_64_TAPS:
189
190 frac_bits = 38;
191 break;
192 case EASRC_RS_128_TAPS:
193
194 frac_bits = 37;
195 break;
196 default:
197 return -EINVAL;
198 }
199
200 val = (u64)in_rate << frac_bits;
201 do_div(val, out_rate);
202 r = (uint32_t *)&val;
203
204 if (r[1] & 0xFFFFF000) {
205 dev_err(&easrc->pdev->dev, "ratio exceed range\n");
206 return -EINVAL;
207 }
208
209 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
210 EASRC_RRL_RS_RL(r[0]));
211 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
212 EASRC_RRH_RS_RH(r[1]));
213
214 return 0;
215}
216
217
218static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx)
219{
220 struct fsl_easrc_ctx_priv *ctx_priv;
221 int a, b;
222
223 if (!ctx)
224 return;
225
226 ctx_priv = ctx->private;
227
228 a = ctx_priv->in_params.sample_rate;
229 b = ctx_priv->out_params.sample_rate;
230
231 a = gcd(a, b);
232
233
234 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a;
235 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a;
236}
237
238
239static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
240 unsigned int ctx_id, int mem_type)
241{
242 struct device *dev;
243 u32 reg, mask, val;
244
245 if (!easrc)
246 return -ENODEV;
247
248 dev = &easrc->pdev->dev;
249
250 switch (mem_type) {
251 case EASRC_PF_COEFF_MEM:
252
253 if (ctx_id >= EASRC_CTX_MAX_NUM) {
254 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
255 return -EINVAL;
256 }
257
258 reg = REG_EASRC_CCE1(ctx_id);
259 mask = EASRC_CCE1_COEF_MEM_RST_MASK;
260 val = EASRC_CCE1_COEF_MEM_RST;
261 break;
262 case EASRC_RS_COEFF_MEM:
263
264 reg = REG_EASRC_CRCC;
265 mask = EASRC_CRCC_RS_CPR_MASK;
266 val = EASRC_CRCC_RS_CPR;
267 break;
268 default:
269 dev_err(dev, "Unknown memory type\n");
270 return -EINVAL;
271 }
272
273
274
275
276
277
278 regmap_update_bits(easrc->regmap, reg, mask, 0);
279 regmap_update_bits(easrc->regmap, reg, mask, val);
280 regmap_update_bits(easrc->regmap, reg, mask, 0);
281
282 return 0;
283}
284
285static inline uint32_t bits_taps_to_val(unsigned int t)
286{
287 switch (t) {
288 case EASRC_RS_32_TAPS:
289 return 32;
290 case EASRC_RS_64_TAPS:
291 return 64;
292 case EASRC_RS_128_TAPS:
293 return 128;
294 }
295
296 return 0;
297}
298
299static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
300{
301 struct device *dev = &easrc->pdev->dev;
302 struct fsl_easrc_priv *easrc_priv = easrc->private;
303 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr;
304 struct interp_params *interp = easrc_priv->interp;
305 struct interp_params *selected_interp = NULL;
306 unsigned int num_coeff;
307 unsigned int i;
308 u64 *coef;
309 u32 *r;
310 int ret;
311
312 if (!hdr) {
313 dev_err(dev, "firmware not loaded!\n");
314 return -ENODEV;
315 }
316
317 for (i = 0; i < hdr->interp_scen; i++) {
318 if ((interp[i].num_taps - 1) !=
319 bits_taps_to_val(easrc_priv->rs_num_taps))
320 continue;
321
322 coef = interp[i].coeff;
323 selected_interp = &interp[i];
324 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n",
325 selected_interp->num_taps,
326 selected_interp->num_phases);
327 break;
328 }
329
330 if (!selected_interp) {
331 dev_err(dev, "failed to get interpreter configuration\n");
332 return -EINVAL;
333 }
334
335
336
337
338
339
340
341 r = (uint32_t *)&selected_interp->center_tap;
342 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
343 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
344
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350
351
352 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
353 EASRC_CRCC_RS_TAPS_MASK,
354 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps));
355
356
357 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
358 if (ret)
359 return ret;
360
361
362
363
364
365
366
367
368
369 num_coeff = 16 * 128 * 4;
370
371 for (i = 0; i < num_coeff; i++) {
372 r = (uint32_t *)&coef[i];
373 regmap_write(easrc->regmap, REG_EASRC_CRCM,
374 EASRC_CRCM_RS_CWD(r[0]));
375 regmap_write(easrc->regmap, REG_EASRC_CRCM,
376 EASRC_CRCM_RS_CWD(r[1]));
377 }
378
379 return 0;
380}
381
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394
395static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
396 u64 *infilter,
397 u64 *outfilter,
398 int shift)
399{
400 struct device *dev = &easrc->pdev->dev;
401 u64 coef = *infilter;
402 s64 exp = (coef & 0x7ff0000000000000ll) >> 52;
403 u64 outcoef;
404
405
406
407
408
409 if (exp == 0 || exp == 0x7ff) {
410 *outfilter = coef;
411 return 0;
412 }
413
414
415 exp += shift;
416
417 if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) {
418 dev_err(dev, "coef out of range\n");
419 return -EINVAL;
420 }
421
422 outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52);
423 *outfilter = outcoef;
424
425 return 0;
426}
427
428static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
429 u64 *coef, int n_taps, int shift)
430{
431 struct device *dev = &easrc->pdev->dev;
432 int ret = 0;
433 int i;
434 u32 *r;
435 u64 tmp;
436
437
438 if (!n_taps)
439 return 0;
440
441 if (!coef) {
442 dev_err(dev, "coef table is NULL\n");
443 return -EINVAL;
444 }
445
446
447
448
449
450 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
451 if (ret)
452 return ret;
453
454 for (i = 0; i < (n_taps + 1) / 2; i++) {
455 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
456 if (ret)
457 return ret;
458
459 r = (uint32_t *)&tmp;
460 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
461 EASRC_PCF_CD(r[0]));
462 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
463 EASRC_PCF_CD(r[1]));
464 }
465
466 return 0;
467}
468
469static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
470 unsigned int ctx_id)
471{
472 struct prefil_params *prefil, *selected_prefil = NULL;
473 struct fsl_easrc_ctx_priv *ctx_priv;
474 struct fsl_easrc_priv *easrc_priv;
475 struct asrc_firmware_hdr *hdr;
476 struct fsl_asrc_pair *ctx;
477 struct device *dev;
478 u32 inrate, outrate, offset = 0;
479 u32 in_s_rate, out_s_rate, in_s_fmt, out_s_fmt;
480 int ret, i;
481
482 if (!easrc)
483 return -ENODEV;
484
485 dev = &easrc->pdev->dev;
486
487 if (ctx_id >= EASRC_CTX_MAX_NUM) {
488 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
489 return -EINVAL;
490 }
491
492 easrc_priv = easrc->private;
493
494 ctx = easrc->pair[ctx_id];
495 ctx_priv = ctx->private;
496
497 in_s_rate = ctx_priv->in_params.sample_rate;
498 out_s_rate = ctx_priv->out_params.sample_rate;
499 in_s_fmt = ctx_priv->in_params.sample_format;
500 out_s_fmt = ctx_priv->out_params.sample_format;
501
502 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2;
503 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
504
505 ctx_priv->st1_num_taps = 0;
506 ctx_priv->st2_num_taps = 0;
507
508 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
509 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
510
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549
550 if (out_s_rate >= in_s_rate) {
551 if (out_s_rate == in_s_rate)
552 regmap_update_bits(easrc->regmap,
553 REG_EASRC_CCE1(ctx_id),
554 EASRC_CCE1_RS_BYPASS_MASK,
555 EASRC_CCE1_RS_BYPASS);
556
557 ctx_priv->st1_num_taps = 1;
558 ctx_priv->st1_coeff = &easrc_priv->const_coeff;
559 ctx_priv->st1_num_exp = 1;
560 ctx_priv->st2_num_taps = 0;
561
562 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
563 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE)
564 ctx_priv->st1_addexp = 31;
565 else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
566 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE)
567 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
568 } else {
569 inrate = ctx_priv->in_params.norm_rate;
570 outrate = ctx_priv->out_params.norm_rate;
571
572 hdr = easrc_priv->firmware_hdr;
573 prefil = easrc_priv->prefil;
574
575 for (i = 0; i < hdr->prefil_scen; i++) {
576 if (inrate == prefil[i].insr &&
577 outrate == prefil[i].outsr) {
578 selected_prefil = &prefil[i];
579 dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n",
580 selected_prefil->insr,
581 selected_prefil->outsr,
582 selected_prefil->st1_taps,
583 selected_prefil->st2_taps);
584 break;
585 }
586 }
587
588 if (!selected_prefil) {
589 dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n",
590 in_s_rate, inrate,
591 out_s_rate, outrate);
592 return -EINVAL;
593 }
594
595
596
597
598
599
600 ctx_priv->st1_num_taps = selected_prefil->st1_taps;
601 ctx_priv->st1_coeff = selected_prefil->coeff;
602 ctx_priv->st1_num_exp = selected_prefil->st1_exp;
603
604 offset = ((selected_prefil->st1_taps + 1) / 2);
605 ctx_priv->st2_num_taps = selected_prefil->st2_taps;
606 ctx_priv->st2_coeff = selected_prefil->coeff + offset;
607
608 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
609 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) {
610
611 if (ctx_priv->st2_num_taps > 0)
612 ctx_priv->st2_addexp = 31;
613 else
614 ctx_priv->st1_addexp = 31;
615 } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
616 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) {
617 if (ctx_priv->st2_num_taps > 0)
618 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp;
619 else
620 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
621 }
622 }
623
624 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp +
625 ctx_priv->st2_num_taps / 2;
626 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
627
628 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0)
629 ctx_priv->out_missed_sample += 1;
630
631
632
633
634
635 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
636 EASRC_CC_EN_MASK, 0);
637
638 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
639 dev_err(dev, "ST1 taps [%d] mus be lower than %d\n",
640 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS);
641 ret = -EINVAL;
642 goto ctx_error;
643 }
644
645
646 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
647 EASRC_CCE2_ST1_TAPS_MASK,
648 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1));
649
650
651 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
652 EASRC_CCE1_COEF_WS_MASK,
653 EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
654
655 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
656 ctx_priv->st1_coeff,
657 ctx_priv->st1_num_taps,
658 ctx_priv->st1_addexp);
659 if (ret)
660 goto ctx_error;
661
662 if (ctx_priv->st2_num_taps > 0) {
663 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
664 dev_err(dev, "ST2 taps [%d] mus be lower than %d\n",
665 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS);
666 ret = -EINVAL;
667 goto ctx_error;
668 }
669
670 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
671 EASRC_CCE1_PF_TSEN_MASK,
672 EASRC_CCE1_PF_TSEN);
673
674
675
676
677 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
678 EASRC_CCE1_PF_ST1_WBFP_MASK,
679 EASRC_CCE1_PF_ST1_WBFP);
680
681 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
682 EASRC_CCE1_PF_EXP_MASK,
683 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1));
684
685
686 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
687 EASRC_CCE2_ST2_TAPS_MASK,
688 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1));
689
690
691 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
692 EASRC_CCE1_COEF_WS_MASK,
693 EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
694
695 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
696 ctx_priv->st2_coeff,
697 ctx_priv->st2_num_taps,
698 ctx_priv->st2_addexp);
699 if (ret)
700 goto ctx_error;
701 }
702
703 return 0;
704
705ctx_error:
706 return ret;
707}
708
709static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx,
710 struct fsl_easrc_slot *slot)
711{
712 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
713 int st1_mem_alloc = 0, st2_mem_alloc = 0;
714 int pf_mem_alloc = 0;
715 int max_channels = 8 - slot->num_channel;
716 int channels = 0;
717
718 if (ctx_priv->st1_num_taps > 0) {
719 if (ctx_priv->st2_num_taps > 0)
720 st1_mem_alloc =
721 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1;
722 else
723 st1_mem_alloc = ctx_priv->st1_num_taps;
724 }
725
726 if (ctx_priv->st2_num_taps > 0)
727 st2_mem_alloc = ctx_priv->st2_num_taps;
728
729 pf_mem_alloc = st1_mem_alloc + st2_mem_alloc;
730
731 if (pf_mem_alloc != 0)
732 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc;
733 else
734 channels = 8;
735
736 if (channels < max_channels)
737 max_channels = channels;
738
739 return max_channels;
740}
741
742static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx,
743 struct fsl_easrc_slot *slot,
744 unsigned int slot_ctx_idx,
745 unsigned int *req_channels,
746 unsigned int *start_channel,
747 unsigned int *avail_channel)
748{
749 struct fsl_asrc *easrc = ctx->asrc;
750 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
751 int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc;
752 unsigned int reg0, reg1, reg2, reg3;
753 unsigned int addr;
754
755 if (slot->slot_index == 0) {
756 reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx);
757 reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx);
758 reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx);
759 reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx);
760 } else {
761 reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx);
762 reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx);
763 reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx);
764 reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx);
765 }
766
767 if (*req_channels <= *avail_channel) {
768 slot->num_channel = *req_channels;
769 *req_channels = 0;
770 } else {
771 slot->num_channel = *avail_channel;
772 *req_channels -= *avail_channel;
773 }
774
775 slot->min_channel = *start_channel;
776 slot->max_channel = *start_channel + slot->num_channel - 1;
777 slot->ctx_index = ctx->index;
778 slot->busy = true;
779 *start_channel += slot->num_channel;
780
781 regmap_update_bits(easrc->regmap, reg0,
782 EASRC_DPCS0R0_MAXCH_MASK,
783 EASRC_DPCS0R0_MAXCH(slot->max_channel));
784
785 regmap_update_bits(easrc->regmap, reg0,
786 EASRC_DPCS0R0_MINCH_MASK,
787 EASRC_DPCS0R0_MINCH(slot->min_channel));
788
789 regmap_update_bits(easrc->regmap, reg0,
790 EASRC_DPCS0R0_NUMCH_MASK,
791 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1));
792
793 regmap_update_bits(easrc->regmap, reg0,
794 EASRC_DPCS0R0_CTXNUM_MASK,
795 EASRC_DPCS0R0_CTXNUM(slot->ctx_index));
796
797 if (ctx_priv->st1_num_taps > 0) {
798 if (ctx_priv->st2_num_taps > 0)
799 st1_mem_alloc =
800 (ctx_priv->st1_num_taps - 1) * slot->num_channel *
801 ctx_priv->st1_num_exp + slot->num_channel;
802 else
803 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel;
804
805 slot->pf_mem_used = st1_mem_alloc;
806 regmap_update_bits(easrc->regmap, reg2,
807 EASRC_DPCS0R2_ST1_MA_MASK,
808 EASRC_DPCS0R2_ST1_MA(st1_mem_alloc));
809
810 if (slot->slot_index == 1)
811 addr = PREFILTER_MEM_LEN - st1_mem_alloc;
812 else
813 addr = 0;
814
815 regmap_update_bits(easrc->regmap, reg2,
816 EASRC_DPCS0R2_ST1_SA_MASK,
817 EASRC_DPCS0R2_ST1_SA(addr));
818 }
819
820 if (ctx_priv->st2_num_taps > 0) {
821 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1);
822
823 regmap_update_bits(easrc->regmap, reg1,
824 EASRC_DPCS0R1_ST1_EXP_MASK,
825 EASRC_DPCS0R1_ST1_EXP(st1_chanxexp));
826
827 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps;
828 slot->pf_mem_used += st2_mem_alloc;
829 regmap_update_bits(easrc->regmap, reg3,
830 EASRC_DPCS0R3_ST2_MA_MASK,
831 EASRC_DPCS0R3_ST2_MA(st2_mem_alloc));
832
833 if (slot->slot_index == 1)
834 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc;
835 else
836 addr = st1_mem_alloc;
837
838 regmap_update_bits(easrc->regmap, reg3,
839 EASRC_DPCS0R3_ST2_SA_MASK,
840 EASRC_DPCS0R3_ST2_SA(addr));
841 }
842
843 regmap_update_bits(easrc->regmap, reg0,
844 EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN);
845
846 return 0;
847}
848
849
850
851
852
853
854
855
856
857
858
859
860static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
861{
862 struct fsl_easrc_priv *easrc_priv = easrc->private;
863 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
864 int req_channels = ctx->channels;
865 int start_channel = 0, avail_channel;
866 struct fsl_easrc_slot *slot0, *slot1;
867 struct fsl_easrc_slot *slota, *slotb;
868 int i, ret;
869
870 if (req_channels <= 0)
871 return -EINVAL;
872
873 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
874 slot0 = &easrc_priv->slot[i][0];
875 slot1 = &easrc_priv->slot[i][1];
876
877 if (slot0->busy && slot1->busy) {
878 continue;
879 } else if ((slot0->busy && slot0->ctx_index == ctx->index) ||
880 (slot1->busy && slot1->ctx_index == ctx->index)) {
881 continue;
882 } else if (!slot0->busy) {
883 slota = slot0;
884 slotb = slot1;
885 slota->slot_index = 0;
886 } else if (!slot1->busy) {
887 slota = slot1;
888 slotb = slot0;
889 slota->slot_index = 1;
890 }
891
892 if (!slota || !slotb)
893 continue;
894
895 avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb);
896 if (avail_channel <= 0)
897 continue;
898
899 ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels,
900 &start_channel, &avail_channel);
901 if (ret)
902 return ret;
903
904 if (req_channels > 0)
905 continue;
906 else
907 break;
908 }
909
910 if (req_channels > 0) {
911 dev_err(&easrc->pdev->dev, "no avail slot.\n");
912 return -EINVAL;
913 }
914
915 return 0;
916}
917
918
919
920
921
922
923static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
924{
925 struct fsl_easrc_priv *easrc_priv = easrc->private;
926 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
927 int i;
928
929 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
930 if (easrc_priv->slot[i][0].busy &&
931 easrc_priv->slot[i][0].ctx_index == ctx->index) {
932 easrc_priv->slot[i][0].busy = false;
933 easrc_priv->slot[i][0].num_channel = 0;
934 easrc_priv->slot[i][0].pf_mem_used = 0;
935
936 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
937 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
938 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
939 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
940 }
941
942 if (easrc_priv->slot[i][1].busy &&
943 easrc_priv->slot[i][1].ctx_index == ctx->index) {
944 easrc_priv->slot[i][1].busy = false;
945 easrc_priv->slot[i][1].num_channel = 0;
946 easrc_priv->slot[i][1].pf_mem_used = 0;
947
948 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
949 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
950 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
951 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
952 }
953 }
954
955 return 0;
956}
957
958
959
960
961
962
963static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
964{
965 struct fsl_easrc_ctx_priv *ctx_priv;
966 struct fsl_asrc_pair *ctx;
967 struct device *dev;
968 unsigned long lock_flags;
969 int ret;
970
971 if (!easrc)
972 return -ENODEV;
973
974 dev = &easrc->pdev->dev;
975
976 if (ctx_id >= EASRC_CTX_MAX_NUM) {
977 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
978 return -EINVAL;
979 }
980
981 ctx = easrc->pair[ctx_id];
982
983 ctx_priv = ctx->private;
984
985 fsl_easrc_normalize_rates(ctx);
986
987 ret = fsl_easrc_set_rs_ratio(ctx);
988 if (ret)
989 return ret;
990
991
992 ret = fsl_easrc_prefilter_config(easrc, ctx->index);
993 if (ret)
994 return ret;
995
996 spin_lock_irqsave(&easrc->lock, lock_flags);
997 ret = fsl_easrc_config_slot(easrc, ctx->index);
998 spin_unlock_irqrestore(&easrc->lock, lock_flags);
999 if (ret)
1000 return ret;
1001
1002
1003
1004
1005
1006
1007
1008
1009 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1010 EASRC_CCE1_RS_INIT_MASK,
1011 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode));
1012
1013 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1014 EASRC_CCE1_PF_INIT_MASK,
1015 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode));
1016
1017
1018
1019
1020
1021 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1022 EASRC_CC_FIFO_WTMK_MASK,
1023 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk));
1024
1025
1026
1027
1028
1029
1030 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
1031 EASRC_COC_FIFO_WTMK_MASK,
1032 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1));
1033
1034
1035 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1036 EASRC_CC_CHEN_MASK,
1037 EASRC_CC_CHEN(ctx->channels - 1));
1038 return 0;
1039}
1040
1041static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx,
1042 struct fsl_easrc_data_fmt *fmt,
1043 snd_pcm_format_t raw_fmt)
1044{
1045 struct fsl_asrc *easrc = ctx->asrc;
1046 struct fsl_easrc_priv *easrc_priv = easrc->private;
1047 int ret;
1048
1049 if (!fmt)
1050 return -EINVAL;
1051
1052
1053
1054
1055
1056
1057 fmt->floating_point = !snd_pcm_format_linear(raw_fmt);
1058 fmt->sample_pos = 0;
1059 fmt->iec958 = 0;
1060
1061
1062 switch (snd_pcm_format_width(raw_fmt)) {
1063 case 16:
1064 fmt->width = EASRC_WIDTH_16_BIT;
1065 fmt->addexp = 15;
1066 break;
1067 case 20:
1068 fmt->width = EASRC_WIDTH_20_BIT;
1069 fmt->addexp = 19;
1070 break;
1071 case 24:
1072 fmt->width = EASRC_WIDTH_24_BIT;
1073 fmt->addexp = 23;
1074 break;
1075 case 32:
1076 fmt->width = EASRC_WIDTH_32_BIT;
1077 fmt->addexp = 31;
1078 break;
1079 default:
1080 return -EINVAL;
1081 }
1082
1083 switch (raw_fmt) {
1084 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1085 fmt->width = easrc_priv->bps_iec958[ctx->index];
1086 fmt->iec958 = 1;
1087 fmt->floating_point = 0;
1088 if (fmt->width == EASRC_WIDTH_16_BIT) {
1089 fmt->sample_pos = 12;
1090 fmt->addexp = 15;
1091 } else if (fmt->width == EASRC_WIDTH_20_BIT) {
1092 fmt->sample_pos = 8;
1093 fmt->addexp = 19;
1094 } else if (fmt->width == EASRC_WIDTH_24_BIT) {
1095 fmt->sample_pos = 4;
1096 fmt->addexp = 23;
1097 }
1098 break;
1099 default:
1100 break;
1101 }
1102
1103
1104
1105
1106
1107
1108 ret = snd_pcm_format_big_endian(raw_fmt);
1109 if (ret < 0)
1110 return ret;
1111
1112 fmt->endianness = ret;
1113
1114
1115
1116
1117
1118
1119 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0;
1120
1121 return 0;
1122}
1123
1124static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx,
1125 snd_pcm_format_t *in_raw_format,
1126 snd_pcm_format_t *out_raw_format)
1127{
1128 struct fsl_asrc *easrc = ctx->asrc;
1129 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
1130 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt;
1131 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt;
1132 int ret = 0;
1133
1134
1135 if (in_raw_format && out_raw_format) {
1136 ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format);
1137 if (ret)
1138 return ret;
1139 }
1140
1141 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1142 EASRC_CC_BPS_MASK,
1143 EASRC_CC_BPS(in_fmt->width));
1144 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1145 EASRC_CC_ENDIANNESS_MASK,
1146 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT);
1147 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1148 EASRC_CC_FMT_MASK,
1149 in_fmt->floating_point << EASRC_CC_FMT_SHIFT);
1150 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1151 EASRC_CC_INSIGN_MASK,
1152 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT);
1153
1154
1155 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1156 EASRC_CC_SAMPLE_POS_MASK,
1157 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos));
1158
1159
1160 if (in_raw_format && out_raw_format) {
1161 ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1167 EASRC_COC_BPS_MASK,
1168 EASRC_COC_BPS(out_fmt->width));
1169 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1170 EASRC_COC_ENDIANNESS_MASK,
1171 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT);
1172 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1173 EASRC_COC_FMT_MASK,
1174 out_fmt->floating_point << EASRC_COC_FMT_SHIFT);
1175 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1176 EASRC_COC_OUTSIGN_MASK,
1177 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT);
1178
1179
1180 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1181 EASRC_COC_SAMPLE_POS_MASK,
1182 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos));
1183
1184 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1185 EASRC_COC_IEC_EN_MASK,
1186 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT);
1187
1188 return ret;
1189}
1190
1191
1192
1193
1194
1195
1196
1197static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx)
1198{
1199 struct fsl_easrc_ctx_priv *ctx_priv;
1200 struct fsl_asrc *easrc;
1201
1202 if (!ctx)
1203 return -ENODEV;
1204
1205 easrc = ctx->asrc;
1206 ctx_priv = ctx->private;
1207
1208
1209 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1210 EASRC_CIA_ITER_MASK,
1211 EASRC_CIA_ITER(ctx_priv->in_params.iterations));
1212 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1213 EASRC_CIA_GRLEN_MASK,
1214 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len));
1215 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1216 EASRC_CIA_ACCLEN_MASK,
1217 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len));
1218
1219
1220 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1221 EASRC_COA_ITER_MASK,
1222 EASRC_COA_ITER(ctx_priv->out_params.iterations));
1223 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1224 EASRC_COA_GRLEN_MASK,
1225 EASRC_COA_GRLEN(ctx_priv->out_params.group_len));
1226 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1227 EASRC_COA_ACCLEN_MASK,
1228 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len));
1229
1230 return 0;
1231}
1232
1233
1234
1235
1236
1237
1238
1239static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx)
1240{
1241 enum asrc_pair_index index = ASRC_INVALID_PAIR;
1242 struct fsl_asrc *easrc = ctx->asrc;
1243 struct device *dev;
1244 unsigned long lock_flags;
1245 int ret = 0;
1246 int i;
1247
1248 dev = &easrc->pdev->dev;
1249
1250 spin_lock_irqsave(&easrc->lock, lock_flags);
1251
1252 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
1253 if (easrc->pair[i])
1254 continue;
1255
1256 index = i;
1257 break;
1258 }
1259
1260 if (index == ASRC_INVALID_PAIR) {
1261 dev_err(dev, "all contexts are busy\n");
1262 ret = -EBUSY;
1263 } else if (channels > easrc->channel_avail) {
1264 dev_err(dev, "can't give the required channels: %d\n",
1265 channels);
1266 ret = -EINVAL;
1267 } else {
1268 ctx->index = index;
1269 ctx->channels = channels;
1270 easrc->pair[index] = ctx;
1271 easrc->channel_avail -= channels;
1272 }
1273
1274 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1275
1276 return ret;
1277}
1278
1279
1280
1281
1282
1283
1284static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx)
1285{
1286 unsigned long lock_flags;
1287 struct fsl_asrc *easrc;
1288
1289 if (!ctx)
1290 return;
1291
1292 easrc = ctx->asrc;
1293
1294 spin_lock_irqsave(&easrc->lock, lock_flags);
1295
1296 fsl_easrc_release_slot(easrc, ctx->index);
1297
1298 easrc->channel_avail += ctx->channels;
1299 easrc->pair[ctx->index] = NULL;
1300
1301 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1302}
1303
1304
1305
1306
1307
1308
1309static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx)
1310{
1311 struct fsl_asrc *easrc = ctx->asrc;
1312
1313 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1314 EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE);
1315 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1316 EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE);
1317 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1318 EASRC_CC_EN_MASK, EASRC_CC_EN);
1319 return 0;
1320}
1321
1322
1323
1324
1325
1326
1327static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx)
1328{
1329 struct fsl_asrc *easrc = ctx->asrc;
1330 int val, i;
1331 int size;
1332 int retry = 200;
1333
1334 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
1335
1336 if (val & EASRC_CC_EN_MASK) {
1337 regmap_update_bits(easrc->regmap,
1338 REG_EASRC_CC(ctx->index),
1339 EASRC_CC_STOP_MASK, EASRC_CC_STOP);
1340 do {
1341 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
1342 val &= EASRC_SFS_NSGO_MASK;
1343 size = val >> EASRC_SFS_NSGO_SHIFT;
1344
1345
1346 for (i = 0; i < size * ctx->channels; i++)
1347 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
1348
1349 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1350 if (val & EASRC_IRQF_RSD(1 << ctx->index)) {
1351
1352 regmap_write_bits(easrc->regmap,
1353 REG_EASRC_IRQF,
1354 EASRC_IRQF_RSD(1 << ctx->index),
1355 EASRC_IRQF_RSD(1 << ctx->index));
1356 break;
1357 }
1358 udelay(100);
1359 } while (--retry);
1360
1361 if (retry == 0)
1362 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
1363 }
1364
1365 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1366 EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0);
1367 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1368 EASRC_CC_FWMDE_MASK, 0);
1369 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1370 EASRC_COC_FWMDE_MASK, 0);
1371 return 0;
1372}
1373
1374static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx,
1375 bool dir)
1376{
1377 struct fsl_asrc *easrc = ctx->asrc;
1378 enum asrc_pair_index index = ctx->index;
1379 char name[8];
1380
1381
1382 sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't');
1383
1384 return dma_request_slave_channel(&easrc->pdev->dev, name);
1385};
1386
1387static const unsigned int easrc_rates[] = {
1388 8000, 11025, 12000, 16000,
1389 22050, 24000, 32000, 44100,
1390 48000, 64000, 88200, 96000,
1391 128000, 176400, 192000, 256000,
1392 352800, 384000, 705600, 768000,
1393};
1394
1395static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = {
1396 .count = ARRAY_SIZE(easrc_rates),
1397 .list = easrc_rates,
1398};
1399
1400static int fsl_easrc_startup(struct snd_pcm_substream *substream,
1401 struct snd_soc_dai *dai)
1402{
1403 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1404 SNDRV_PCM_HW_PARAM_RATE,
1405 &easrc_rate_constraints);
1406}
1407
1408static int fsl_easrc_trigger(struct snd_pcm_substream *substream,
1409 int cmd, struct snd_soc_dai *dai)
1410{
1411 struct snd_pcm_runtime *runtime = substream->runtime;
1412 struct fsl_asrc_pair *ctx = runtime->private_data;
1413 int ret;
1414
1415 switch (cmd) {
1416 case SNDRV_PCM_TRIGGER_START:
1417 case SNDRV_PCM_TRIGGER_RESUME:
1418 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1419 ret = fsl_easrc_start_context(ctx);
1420 if (ret)
1421 return ret;
1422 break;
1423 case SNDRV_PCM_TRIGGER_STOP:
1424 case SNDRV_PCM_TRIGGER_SUSPEND:
1425 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1426 ret = fsl_easrc_stop_context(ctx);
1427 if (ret)
1428 return ret;
1429 break;
1430 default:
1431 return -EINVAL;
1432 }
1433
1434 return 0;
1435}
1436
1437static int fsl_easrc_hw_params(struct snd_pcm_substream *substream,
1438 struct snd_pcm_hw_params *params,
1439 struct snd_soc_dai *dai)
1440{
1441 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
1442 struct snd_pcm_runtime *runtime = substream->runtime;
1443 struct device *dev = &easrc->pdev->dev;
1444 struct fsl_asrc_pair *ctx = runtime->private_data;
1445 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
1446 unsigned int channels = params_channels(params);
1447 unsigned int rate = params_rate(params);
1448 snd_pcm_format_t format = params_format(params);
1449 int ret;
1450
1451 ret = fsl_easrc_request_context(channels, ctx);
1452 if (ret) {
1453 dev_err(dev, "failed to request context\n");
1454 return ret;
1455 }
1456
1457 ctx_priv->ctx_streams |= BIT(substream->stream);
1458
1459
1460
1461
1462
1463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1464 ctx_priv->in_params.sample_rate = rate;
1465 ctx_priv->in_params.sample_format = format;
1466 ctx_priv->out_params.sample_rate = easrc->asrc_rate;
1467 ctx_priv->out_params.sample_format = easrc->asrc_format;
1468 } else {
1469 ctx_priv->out_params.sample_rate = rate;
1470 ctx_priv->out_params.sample_format = format;
1471 ctx_priv->in_params.sample_rate = easrc->asrc_rate;
1472 ctx_priv->in_params.sample_format = easrc->asrc_format;
1473 }
1474
1475 ctx->channels = channels;
1476 ctx_priv->in_params.fifo_wtmk = 0x20;
1477 ctx_priv->out_params.fifo_wtmk = 0x20;
1478
1479
1480
1481
1482
1483 ret = fsl_easrc_set_ctx_format(ctx,
1484 &ctx_priv->in_params.sample_format,
1485 &ctx_priv->out_params.sample_format);
1486 if (ret) {
1487 dev_err(dev, "failed to set format %d", ret);
1488 return ret;
1489 }
1490
1491 ret = fsl_easrc_config_context(easrc, ctx->index);
1492 if (ret) {
1493 dev_err(dev, "failed to config context\n");
1494 return ret;
1495 }
1496
1497 ctx_priv->in_params.iterations = 1;
1498 ctx_priv->in_params.group_len = ctx->channels;
1499 ctx_priv->in_params.access_len = ctx->channels;
1500 ctx_priv->out_params.iterations = 1;
1501 ctx_priv->out_params.group_len = ctx->channels;
1502 ctx_priv->out_params.access_len = ctx->channels;
1503
1504 ret = fsl_easrc_set_ctx_organziation(ctx);
1505 if (ret) {
1506 dev_err(dev, "failed to set fifo organization\n");
1507 return ret;
1508 }
1509
1510 return 0;
1511}
1512
1513static int fsl_easrc_hw_free(struct snd_pcm_substream *substream,
1514 struct snd_soc_dai *dai)
1515{
1516 struct snd_pcm_runtime *runtime = substream->runtime;
1517 struct fsl_asrc_pair *ctx = runtime->private_data;
1518 struct fsl_easrc_ctx_priv *ctx_priv;
1519
1520 if (!ctx)
1521 return -EINVAL;
1522
1523 ctx_priv = ctx->private;
1524
1525 if (ctx_priv->ctx_streams & BIT(substream->stream)) {
1526 ctx_priv->ctx_streams &= ~BIT(substream->stream);
1527 fsl_easrc_release_context(ctx);
1528 }
1529
1530 return 0;
1531}
1532
1533static const struct snd_soc_dai_ops fsl_easrc_dai_ops = {
1534 .startup = fsl_easrc_startup,
1535 .trigger = fsl_easrc_trigger,
1536 .hw_params = fsl_easrc_hw_params,
1537 .hw_free = fsl_easrc_hw_free,
1538};
1539
1540static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai)
1541{
1542 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
1543
1544 snd_soc_dai_init_dma_data(cpu_dai,
1545 &easrc->dma_params_tx,
1546 &easrc->dma_params_rx);
1547 return 0;
1548}
1549
1550static struct snd_soc_dai_driver fsl_easrc_dai = {
1551 .probe = fsl_easrc_dai_probe,
1552 .playback = {
1553 .stream_name = "ASRC-Playback",
1554 .channels_min = 1,
1555 .channels_max = 32,
1556 .rate_min = 8000,
1557 .rate_max = 768000,
1558 .rates = SNDRV_PCM_RATE_KNOT,
1559 .formats = FSL_EASRC_FORMATS,
1560 },
1561 .capture = {
1562 .stream_name = "ASRC-Capture",
1563 .channels_min = 1,
1564 .channels_max = 32,
1565 .rate_min = 8000,
1566 .rate_max = 768000,
1567 .rates = SNDRV_PCM_RATE_KNOT,
1568 .formats = FSL_EASRC_FORMATS |
1569 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1570 },
1571 .ops = &fsl_easrc_dai_ops,
1572};
1573
1574static const struct snd_soc_component_driver fsl_easrc_component = {
1575 .name = "fsl-easrc-dai",
1576 .controls = fsl_easrc_snd_controls,
1577 .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls),
1578};
1579
1580static const struct reg_default fsl_easrc_reg_defaults[] = {
1581 {REG_EASRC_WRFIFO(0), 0x00000000},
1582 {REG_EASRC_WRFIFO(1), 0x00000000},
1583 {REG_EASRC_WRFIFO(2), 0x00000000},
1584 {REG_EASRC_WRFIFO(3), 0x00000000},
1585 {REG_EASRC_RDFIFO(0), 0x00000000},
1586 {REG_EASRC_RDFIFO(1), 0x00000000},
1587 {REG_EASRC_RDFIFO(2), 0x00000000},
1588 {REG_EASRC_RDFIFO(3), 0x00000000},
1589 {REG_EASRC_CC(0), 0x00000000},
1590 {REG_EASRC_CC(1), 0x00000000},
1591 {REG_EASRC_CC(2), 0x00000000},
1592 {REG_EASRC_CC(3), 0x00000000},
1593 {REG_EASRC_CCE1(0), 0x00000000},
1594 {REG_EASRC_CCE1(1), 0x00000000},
1595 {REG_EASRC_CCE1(2), 0x00000000},
1596 {REG_EASRC_CCE1(3), 0x00000000},
1597 {REG_EASRC_CCE2(0), 0x00000000},
1598 {REG_EASRC_CCE2(1), 0x00000000},
1599 {REG_EASRC_CCE2(2), 0x00000000},
1600 {REG_EASRC_CCE2(3), 0x00000000},
1601 {REG_EASRC_CIA(0), 0x00000000},
1602 {REG_EASRC_CIA(1), 0x00000000},
1603 {REG_EASRC_CIA(2), 0x00000000},
1604 {REG_EASRC_CIA(3), 0x00000000},
1605 {REG_EASRC_DPCS0R0(0), 0x00000000},
1606 {REG_EASRC_DPCS0R0(1), 0x00000000},
1607 {REG_EASRC_DPCS0R0(2), 0x00000000},
1608 {REG_EASRC_DPCS0R0(3), 0x00000000},
1609 {REG_EASRC_DPCS0R1(0), 0x00000000},
1610 {REG_EASRC_DPCS0R1(1), 0x00000000},
1611 {REG_EASRC_DPCS0R1(2), 0x00000000},
1612 {REG_EASRC_DPCS0R1(3), 0x00000000},
1613 {REG_EASRC_DPCS0R2(0), 0x00000000},
1614 {REG_EASRC_DPCS0R2(1), 0x00000000},
1615 {REG_EASRC_DPCS0R2(2), 0x00000000},
1616 {REG_EASRC_DPCS0R2(3), 0x00000000},
1617 {REG_EASRC_DPCS0R3(0), 0x00000000},
1618 {REG_EASRC_DPCS0R3(1), 0x00000000},
1619 {REG_EASRC_DPCS0R3(2), 0x00000000},
1620 {REG_EASRC_DPCS0R3(3), 0x00000000},
1621 {REG_EASRC_DPCS1R0(0), 0x00000000},
1622 {REG_EASRC_DPCS1R0(1), 0x00000000},
1623 {REG_EASRC_DPCS1R0(2), 0x00000000},
1624 {REG_EASRC_DPCS1R0(3), 0x00000000},
1625 {REG_EASRC_DPCS1R1(0), 0x00000000},
1626 {REG_EASRC_DPCS1R1(1), 0x00000000},
1627 {REG_EASRC_DPCS1R1(2), 0x00000000},
1628 {REG_EASRC_DPCS1R1(3), 0x00000000},
1629 {REG_EASRC_DPCS1R2(0), 0x00000000},
1630 {REG_EASRC_DPCS1R2(1), 0x00000000},
1631 {REG_EASRC_DPCS1R2(2), 0x00000000},
1632 {REG_EASRC_DPCS1R2(3), 0x00000000},
1633 {REG_EASRC_DPCS1R3(0), 0x00000000},
1634 {REG_EASRC_DPCS1R3(1), 0x00000000},
1635 {REG_EASRC_DPCS1R3(2), 0x00000000},
1636 {REG_EASRC_DPCS1R3(3), 0x00000000},
1637 {REG_EASRC_COC(0), 0x00000000},
1638 {REG_EASRC_COC(1), 0x00000000},
1639 {REG_EASRC_COC(2), 0x00000000},
1640 {REG_EASRC_COC(3), 0x00000000},
1641 {REG_EASRC_COA(0), 0x00000000},
1642 {REG_EASRC_COA(1), 0x00000000},
1643 {REG_EASRC_COA(2), 0x00000000},
1644 {REG_EASRC_COA(3), 0x00000000},
1645 {REG_EASRC_SFS(0), 0x00000000},
1646 {REG_EASRC_SFS(1), 0x00000000},
1647 {REG_EASRC_SFS(2), 0x00000000},
1648 {REG_EASRC_SFS(3), 0x00000000},
1649 {REG_EASRC_RRL(0), 0x00000000},
1650 {REG_EASRC_RRL(1), 0x00000000},
1651 {REG_EASRC_RRL(2), 0x00000000},
1652 {REG_EASRC_RRL(3), 0x00000000},
1653 {REG_EASRC_RRH(0), 0x00000000},
1654 {REG_EASRC_RRH(1), 0x00000000},
1655 {REG_EASRC_RRH(2), 0x00000000},
1656 {REG_EASRC_RRH(3), 0x00000000},
1657 {REG_EASRC_RUC(0), 0x00000000},
1658 {REG_EASRC_RUC(1), 0x00000000},
1659 {REG_EASRC_RUC(2), 0x00000000},
1660 {REG_EASRC_RUC(3), 0x00000000},
1661 {REG_EASRC_RUR(0), 0x7FFFFFFF},
1662 {REG_EASRC_RUR(1), 0x7FFFFFFF},
1663 {REG_EASRC_RUR(2), 0x7FFFFFFF},
1664 {REG_EASRC_RUR(3), 0x7FFFFFFF},
1665 {REG_EASRC_RCTCL, 0x00000000},
1666 {REG_EASRC_RCTCH, 0x00000000},
1667 {REG_EASRC_PCF(0), 0x00000000},
1668 {REG_EASRC_PCF(1), 0x00000000},
1669 {REG_EASRC_PCF(2), 0x00000000},
1670 {REG_EASRC_PCF(3), 0x00000000},
1671 {REG_EASRC_CRCM, 0x00000000},
1672 {REG_EASRC_CRCC, 0x00000000},
1673 {REG_EASRC_IRQC, 0x00000FFF},
1674 {REG_EASRC_IRQF, 0x00000000},
1675 {REG_EASRC_CS0(0), 0x00000000},
1676 {REG_EASRC_CS0(1), 0x00000000},
1677 {REG_EASRC_CS0(2), 0x00000000},
1678 {REG_EASRC_CS0(3), 0x00000000},
1679 {REG_EASRC_CS1(0), 0x00000000},
1680 {REG_EASRC_CS1(1), 0x00000000},
1681 {REG_EASRC_CS1(2), 0x00000000},
1682 {REG_EASRC_CS1(3), 0x00000000},
1683 {REG_EASRC_CS2(0), 0x00000000},
1684 {REG_EASRC_CS2(1), 0x00000000},
1685 {REG_EASRC_CS2(2), 0x00000000},
1686 {REG_EASRC_CS2(3), 0x00000000},
1687 {REG_EASRC_CS3(0), 0x00000000},
1688 {REG_EASRC_CS3(1), 0x00000000},
1689 {REG_EASRC_CS3(2), 0x00000000},
1690 {REG_EASRC_CS3(3), 0x00000000},
1691 {REG_EASRC_CS4(0), 0x00000000},
1692 {REG_EASRC_CS4(1), 0x00000000},
1693 {REG_EASRC_CS4(2), 0x00000000},
1694 {REG_EASRC_CS4(3), 0x00000000},
1695 {REG_EASRC_CS5(0), 0x00000000},
1696 {REG_EASRC_CS5(1), 0x00000000},
1697 {REG_EASRC_CS5(2), 0x00000000},
1698 {REG_EASRC_CS5(3), 0x00000000},
1699 {REG_EASRC_DBGC, 0x00000000},
1700 {REG_EASRC_DBGS, 0x00000000},
1701};
1702
1703static const struct regmap_range fsl_easrc_readable_ranges[] = {
1704 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH),
1705 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)),
1706 regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS),
1707};
1708
1709static const struct regmap_access_table fsl_easrc_readable_table = {
1710 .yes_ranges = fsl_easrc_readable_ranges,
1711 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges),
1712};
1713
1714static const struct regmap_range fsl_easrc_writeable_ranges[] = {
1715 regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)),
1716 regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)),
1717 regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH),
1718 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC),
1719};
1720
1721static const struct regmap_access_table fsl_easrc_writeable_table = {
1722 .yes_ranges = fsl_easrc_writeable_ranges,
1723 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges),
1724};
1725
1726static const struct regmap_range fsl_easrc_volatileable_ranges[] = {
1727 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)),
1728 regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)),
1729 regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF),
1730 regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS),
1731};
1732
1733static const struct regmap_access_table fsl_easrc_volatileable_table = {
1734 .yes_ranges = fsl_easrc_volatileable_ranges,
1735 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges),
1736};
1737
1738static const struct regmap_config fsl_easrc_regmap_config = {
1739 .reg_bits = 32,
1740 .reg_stride = 4,
1741 .val_bits = 32,
1742
1743 .max_register = REG_EASRC_DBGS,
1744 .reg_defaults = fsl_easrc_reg_defaults,
1745 .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults),
1746 .rd_table = &fsl_easrc_readable_table,
1747 .wr_table = &fsl_easrc_writeable_table,
1748 .volatile_table = &fsl_easrc_volatileable_table,
1749 .cache_type = REGCACHE_RBTREE,
1750};
1751
1752#ifdef DEBUG
1753static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
1754{
1755 struct fsl_easrc_priv *easrc_priv = easrc->private;
1756 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr;
1757 struct interp_params *interp = easrc_priv->interp;
1758 struct prefil_params *prefil = easrc_priv->prefil;
1759 struct device *dev = &easrc->pdev->dev;
1760 int i;
1761
1762 if (firm->magic != FIRMWARE_MAGIC) {
1763 dev_err(dev, "Wrong magic. Something went wrong!");
1764 return;
1765 }
1766
1767 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version);
1768 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen);
1769 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen);
1770 dev_dbg(dev, "\nInterpolation scenarios:\n");
1771
1772 for (i = 0; i < firm->interp_scen; i++) {
1773 if (interp[i].magic != FIRMWARE_MAGIC) {
1774 dev_dbg(dev, "%d. wrong interp magic: %x\n",
1775 i, interp[i].magic);
1776 continue;
1777 }
1778 dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i,
1779 interp[i].num_taps, interp[i].num_phases,
1780 interp[i].center_tap);
1781 }
1782
1783 for (i = 0; i < firm->prefil_scen; i++) {
1784 if (prefil[i].magic != FIRMWARE_MAGIC) {
1785 dev_dbg(dev, "%d. wrong prefil magic: %x\n",
1786 i, prefil[i].magic);
1787 continue;
1788 }
1789 dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i,
1790 prefil[i].insr, prefil[i].outsr,
1791 prefil[i].st1_taps, prefil[i].st2_taps);
1792 }
1793
1794 dev_dbg(dev, "end of firmware dump\n");
1795}
1796#endif
1797
1798static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
1799{
1800 struct fsl_easrc_priv *easrc_priv;
1801 const struct firmware **fw_p;
1802 u32 pnum, inum, offset;
1803 const u8 *data;
1804 int ret;
1805
1806 if (!easrc)
1807 return -EINVAL;
1808
1809 easrc_priv = easrc->private;
1810 fw_p = &easrc_priv->fw;
1811
1812 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
1813 if (ret)
1814 return ret;
1815
1816 data = easrc_priv->fw->data;
1817
1818 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data;
1819 pnum = easrc_priv->firmware_hdr->prefil_scen;
1820 inum = easrc_priv->firmware_hdr->interp_scen;
1821
1822 if (inum) {
1823 offset = sizeof(struct asrc_firmware_hdr);
1824 easrc_priv->interp = (struct interp_params *)(data + offset);
1825 }
1826
1827 if (pnum) {
1828 offset = sizeof(struct asrc_firmware_hdr) +
1829 inum * sizeof(struct interp_params);
1830 easrc_priv->prefil = (struct prefil_params *)(data + offset);
1831 }
1832
1833#ifdef DEBUG
1834 fsl_easrc_dump_firmware(easrc);
1835#endif
1836
1837 return 0;
1838}
1839
1840static irqreturn_t fsl_easrc_isr(int irq, void *dev_id)
1841{
1842 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
1843 struct device *dev = &easrc->pdev->dev;
1844 int val;
1845
1846 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1847
1848 if (val & EASRC_IRQF_OER_MASK)
1849 dev_dbg(dev, "output FIFO underflow\n");
1850
1851 if (val & EASRC_IRQF_IFO_MASK)
1852 dev_dbg(dev, "input FIFO overflow\n");
1853
1854 return IRQ_HANDLED;
1855}
1856
1857static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
1858{
1859 return REG_EASRC_FIFO(dir, index);
1860}
1861
1862static const struct of_device_id fsl_easrc_dt_ids[] = {
1863 { .compatible = "fsl,imx8mn-easrc",},
1864 {}
1865};
1866MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids);
1867
1868static int fsl_easrc_probe(struct platform_device *pdev)
1869{
1870 struct fsl_easrc_priv *easrc_priv;
1871 struct device *dev = &pdev->dev;
1872 struct fsl_asrc *easrc;
1873 struct resource *res;
1874 struct device_node *np;
1875 void __iomem *regs;
1876 int ret, irq;
1877
1878 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
1879 if (!easrc)
1880 return -ENOMEM;
1881
1882 easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL);
1883 if (!easrc_priv)
1884 return -ENOMEM;
1885
1886 easrc->pdev = pdev;
1887 easrc->private = easrc_priv;
1888 np = dev->of_node;
1889
1890 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1891 if (IS_ERR(regs))
1892 return PTR_ERR(regs);
1893
1894 easrc->paddr = res->start;
1895
1896 easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config);
1897 if (IS_ERR(easrc->regmap)) {
1898 dev_err(dev, "failed to init regmap");
1899 return PTR_ERR(easrc->regmap);
1900 }
1901
1902 irq = platform_get_irq(pdev, 0);
1903 if (irq < 0)
1904 return irq;
1905
1906 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
1907 dev_name(dev), easrc);
1908 if (ret) {
1909 dev_err(dev, "failed to claim irq %u: %d\n", irq, ret);
1910 return ret;
1911 }
1912
1913 easrc->mem_clk = devm_clk_get(dev, "mem");
1914 if (IS_ERR(easrc->mem_clk)) {
1915 dev_err(dev, "failed to get mem clock\n");
1916 return PTR_ERR(easrc->mem_clk);
1917 }
1918
1919
1920 easrc->channel_avail = 32;
1921 easrc->get_dma_channel = fsl_easrc_get_dma_channel;
1922 easrc->request_pair = fsl_easrc_request_context;
1923 easrc->release_pair = fsl_easrc_release_context;
1924 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
1925 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
1926
1927 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS;
1928 easrc_priv->const_coeff = 0x3FF0000000000000;
1929
1930 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
1931 if (ret) {
1932 dev_err(dev, "failed to asrc rate\n");
1933 return ret;
1934 }
1935
1936 ret = of_property_read_u32(np, "fsl,asrc-format", &easrc->asrc_format);
1937 if (ret) {
1938 dev_err(dev, "failed to asrc format\n");
1939 return ret;
1940 }
1941
1942 if (!(FSL_EASRC_FORMATS & (1ULL << easrc->asrc_format))) {
1943 dev_warn(dev, "unsupported format, switching to S24_LE\n");
1944 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1945 }
1946
1947 ret = of_property_read_string(np, "firmware-name",
1948 &easrc_priv->fw_name);
1949 if (ret) {
1950 dev_err(dev, "failed to get firmware name\n");
1951 return ret;
1952 }
1953
1954 platform_set_drvdata(pdev, easrc);
1955 pm_runtime_enable(dev);
1956
1957 spin_lock_init(&easrc->lock);
1958
1959 regcache_cache_only(easrc->regmap, true);
1960
1961 ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
1962 &fsl_easrc_dai, 1);
1963 if (ret) {
1964 dev_err(dev, "failed to register ASoC DAI\n");
1965 return ret;
1966 }
1967
1968 ret = devm_snd_soc_register_component(dev, &fsl_asrc_component,
1969 NULL, 0);
1970 if (ret) {
1971 dev_err(&pdev->dev, "failed to register ASoC platform\n");
1972 return ret;
1973 }
1974
1975 return 0;
1976}
1977
1978static int fsl_easrc_remove(struct platform_device *pdev)
1979{
1980 pm_runtime_disable(&pdev->dev);
1981
1982 return 0;
1983}
1984
1985static __maybe_unused int fsl_easrc_runtime_suspend(struct device *dev)
1986{
1987 struct fsl_asrc *easrc = dev_get_drvdata(dev);
1988 struct fsl_easrc_priv *easrc_priv = easrc->private;
1989 unsigned long lock_flags;
1990
1991 regcache_cache_only(easrc->regmap, true);
1992
1993 clk_disable_unprepare(easrc->mem_clk);
1994
1995 spin_lock_irqsave(&easrc->lock, lock_flags);
1996 easrc_priv->firmware_loaded = 0;
1997 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1998
1999 return 0;
2000}
2001
2002static __maybe_unused int fsl_easrc_runtime_resume(struct device *dev)
2003{
2004 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2005 struct fsl_easrc_priv *easrc_priv = easrc->private;
2006 struct fsl_easrc_ctx_priv *ctx_priv;
2007 struct fsl_asrc_pair *ctx;
2008 unsigned long lock_flags;
2009 int ret;
2010 int i;
2011
2012 ret = clk_prepare_enable(easrc->mem_clk);
2013 if (ret)
2014 return ret;
2015
2016 regcache_cache_only(easrc->regmap, false);
2017 regcache_mark_dirty(easrc->regmap);
2018 regcache_sync(easrc->regmap);
2019
2020 spin_lock_irqsave(&easrc->lock, lock_flags);
2021 if (easrc_priv->firmware_loaded) {
2022 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2023 goto skip_load;
2024 }
2025 easrc_priv->firmware_loaded = 1;
2026 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2027
2028 ret = fsl_easrc_get_firmware(easrc);
2029 if (ret) {
2030 dev_err(dev, "failed to get firmware\n");
2031 goto disable_mem_clk;
2032 }
2033
2034
2035
2036
2037
2038
2039 ret = fsl_easrc_resampler_config(easrc);
2040 if (ret) {
2041 dev_err(dev, "resampler config failed\n");
2042 goto disable_mem_clk;
2043 }
2044
2045 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
2046 ctx = easrc->pair[i];
2047 if (!ctx)
2048 continue;
2049
2050 ctx_priv = ctx->private;
2051 fsl_easrc_set_rs_ratio(ctx);
2052 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample *
2053 ctx_priv->out_params.sample_rate /
2054 ctx_priv->in_params.sample_rate;
2055 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate
2056 % ctx_priv->in_params.sample_rate != 0)
2057 ctx_priv->out_missed_sample += 1;
2058
2059 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2060 ctx_priv->st1_coeff,
2061 ctx_priv->st1_num_taps,
2062 ctx_priv->st1_addexp);
2063 if (ret)
2064 goto disable_mem_clk;
2065
2066 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2067 ctx_priv->st2_coeff,
2068 ctx_priv->st2_num_taps,
2069 ctx_priv->st2_addexp);
2070 if (ret)
2071 goto disable_mem_clk;
2072 }
2073
2074skip_load:
2075 return 0;
2076
2077disable_mem_clk:
2078 clk_disable_unprepare(easrc->mem_clk);
2079 return ret;
2080}
2081
2082static const struct dev_pm_ops fsl_easrc_pm_ops = {
2083 SET_RUNTIME_PM_OPS(fsl_easrc_runtime_suspend,
2084 fsl_easrc_runtime_resume,
2085 NULL)
2086 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2087 pm_runtime_force_resume)
2088};
2089
2090static struct platform_driver fsl_easrc_driver = {
2091 .probe = fsl_easrc_probe,
2092 .remove = fsl_easrc_remove,
2093 .driver = {
2094 .name = "fsl-easrc",
2095 .pm = &fsl_easrc_pm_ops,
2096 .of_match_table = fsl_easrc_dt_ids,
2097 },
2098};
2099module_platform_driver(fsl_easrc_driver);
2100
2101MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");
2102MODULE_LICENSE("GPL v2");
2103
